CN111031209A - Image processing apparatus - Google Patents
Image processing apparatus Download PDFInfo
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- CN111031209A CN111031209A CN201911303767.0A CN201911303767A CN111031209A CN 111031209 A CN111031209 A CN 111031209A CN 201911303767 A CN201911303767 A CN 201911303767A CN 111031209 A CN111031209 A CN 111031209A
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- circuit board
- image processing
- chip
- processing apparatus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Studio Devices (AREA)
Abstract
The application provides an image processing apparatus, including: a first circuit board; the photosensitive chips are arranged on the first circuit board at intervals; and the control chip comprises a control part which is electrically connected with the first circuit board so as to send a synchronous control signal to each photosensitive chip. In the image processing device, the control part transmits the control signals to the first circuit board, and then the control signals are transmitted to the photosensitive chip through the first circuit board, so that the synchronism of the signals received by the photosensitive chip is good, the control chip is difficult to delay relative to the controller, the synchronism of the signals is further guaranteed to be good, and the problem that the controller transmits the control signals to the cameras respectively to cause unsynchronized signals is avoided.
Description
Technical Field
The application relates to the technical field of sensors, in particular to an image processing device.
Background
The current camera systems are all single cameras or combination of a plurality of cameras, each camera is internally provided with only one photosensitive chip, the used light sources are all external light sources, and the light sources and the cameras are controlled through a controller.
In some cases, a camera with a large format, high speed and high resolution is required to take a picture, so that in the traditional case, a plurality of single cameras and a plurality of external light sources are required to be installed and fixed in a space range according to functional requirements. And then the camera data processing and the control of the light source are connected to the corresponding controllers.
The traditional mode solves the corresponding problem to a certain extent, but has the following disadvantages:
1. when the data volume is large, frames are easy to be staggered, data are easy to be lost, and a controller is difficult to simultaneously transmit control signals to each camera, so that the synchronism among a plurality of cameras is poor;
2. the time sequence control between the light source and the camera, the external light source needs longer lighting time to meet the imaging quality, and under the condition of high-speed scanning, the moving distance of the original cannot be ignored, so that imaging ghost images exist;
3. occupies a large space;
4. the cost is high.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The main objective of the present application is to provide an image processing apparatus to solve the problem of poor synchronization when a plurality of cameras in the prior art synchronously photograph.
According to an aspect of an embodiment of the present invention, there is provided an image processing apparatus including: a first circuit board; a plurality of photosensitive chips arranged on the first circuit board at intervals; and the control chip comprises a control part which is electrically connected with the first circuit board so as to send a synchronous control signal to each photosensitive chip.
Further, the image processing apparatus further includes: and the light source is electrically connected with the control chip, and the control chip controls the lighting of the light source.
Further, the control chip further comprises: and the storage part is electrically connected with the first circuit board to store the electric signals obtained by the photosensitive chips.
Further, the image processing apparatus further includes: the second circuit board, control chip sets up on the second circuit board, first circuit board passes through the second circuit board with control chip electricity is connected.
Further, the image processing apparatus further includes: and the cable is used for connecting the first circuit board and the second circuit board.
Further, a plurality of the photosensitive chips are arranged in an array.
Further, each of the photosensitive chips is an area array photoelectric conversion chip.
Further, the control chip is an FPGA chip.
Further, the image processing apparatus further includes: the frame body is provided with an accommodating cavity, and the first circuit board and the photosensitive chip are located in the accommodating cavity.
Further, the control part controls the photosensitive chip and the light source to start working simultaneously, and the control part controls the photosensitive chip to send the obtained electric signal to the control chip and controls the light source to stop working simultaneously.
In the embodiment of the present invention, in the image processing apparatus, the plurality of photosensitive chips are disposed on the first circuit board at intervals, the control portion of the control chip is electrically connected to the first circuit board to send the synchronous control signal to each photosensitive chip, that is, the control portion transmits the control signal to the first circuit board, and then the control signal is sent to the photosensitive chip through the first circuit board, so that the signals received by the photosensitive chips are synchronized well, and the control chip is not easy to delay with respect to the controller, thereby further ensuring good signal synchronization and avoiding the problem of signal asynchronization caused by the controller sending the plurality of control signals to the plurality of cameras respectively.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 shows a schematic configuration diagram of an image processing apparatus according to an embodiment of the present application;
FIG. 2 is a schematic diagram showing an arrangement of photo-sensitive chips on a first circuit board according to an embodiment of the present application;
FIG. 3 is a schematic diagram showing an arrangement of photo-sensing chips on a first circuit board according to another embodiment of the present application;
FIG. 4 is a schematic diagram showing an arrangement of photo-sensing chips on a first circuit board according to yet another embodiment of the present application;
FIG. 5 shows a front view of an image processing apparatus performing image scanning according to an embodiment of the present application;
FIG. 6 shows a side view of the image processing apparatus of FIG. 5 performing an image scan; and
FIG. 7 shows a control timing diagram of a control chip according to an embodiment of the present application.
Wherein the figures include the following reference numerals:
01. an object to be scanned; 10. a first circuit board; 20. a photosensitive chip; 30. a control chip; 40. a light source; 50. a second circuit board; 60. a cable; 70. a frame body.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, in the prior art, when a plurality of cameras perform synchronous photographing, the synchronism is poor, and in order to solve the above problem, the present application provides an image processing apparatus.
Fig. 1 is a schematic configuration diagram of an image processing apparatus according to an embodiment of the present invention, as shown in fig. 1, the image processing apparatus including:
a first wiring board 10;
a plurality of photosensitive chips 20 disposed at intervals on the first wiring board 10;
the control chip 30 includes a control portion electrically connected to the first circuit board 10 to send a synchronization control signal to each of the photosensitive chips 20.
Among the above-mentioned image processing apparatus, a plurality of sensitization chips set up on first circuit board at interval, control chip's control part is connected with first circuit board electricity in order to send synchronous control signal to each sensitization chip, control part all conveys control signal to first circuit board promptly, the first circuit board of rethread sends control signal to sensitization chip like this, make the synchronism of the signal that sensitization chip received better, and, control chip is difficult for postponing to the controller, further guaranteed that the synchronism of signal is better, the problem of signal asynchronization that has avoided the controller to send a plurality of control signals respectively to a plurality of cameras to lead to has been avoided.
In an embodiment of the present application, the image processing apparatus further includes a light source 40 electrically connected to the control chip 30, and the control chip 30 controls lighting of the light source 40. Specifically, the control chip is adopted to control the light source, so that the light source is lighted and synchronized with the frame signal, and the signal synchronism is further improved.
In an embodiment of the present application, the control chip further includes a storage portion, and the storage portion is electrically connected to the first circuit board to store the electrical signals obtained by the photosensitive chips. Specifically, the first circuit board is connected to the synchronous control signal of the control part, and the electric signals of the photosensitive chips are simultaneously transmitted to the storage part, so that frame error and data loss caused by time asynchronism are avoided, and the quality of scanned images is ensured.
In an embodiment of the present application, the image processing apparatus further includes a second circuit board 50, the control chip 30 is disposed on the second circuit board 50, and the first circuit board 10 is electrically connected to the control chip 30 through the second circuit board 50. Specifically, the first circuit board transmits the electric signals obtained by the photosensitive chips to the second circuit board, and then the second circuit board transmits the control signals to the control chip, so that the synchronism of the electric signals received by the photosensitive chips is further improved.
In an embodiment of the present application, as shown in fig. 1, the image processing apparatus further includes a cable 60, and the cable 60 is used for connecting the first circuit board 10 and the second circuit board 50. Specifically, the cables are multiple, each photosensitive chip is connected with the control chip through the cable, the transmission speed cannot be slowed down due to the increase of the number of the photosensitive chips, and meanwhile the control chip is adopted to process the data of the photosensitive chips at a high speed.
In an embodiment of the present application, as shown in fig. 2, the plurality of photosensitive chips are arranged in an array to satisfy high-speed and high-resolution scanning of a larger format, and of course, the arrangement of the photosensitive chips is not limited thereto, and those skilled in the art can select the number and arrangement of the photosensitive chips according to practical situations, for example, as shown in fig. 3, the plurality of photosensitive chips are arranged in rows, and as shown in fig. 4, the plurality of photosensitive chips are arranged in columns.
In an embodiment of the present application, each of the photosensitive chips is an area array photoelectric conversion chip. The plurality of area array photoelectric conversion chips may be of the same type or of different types, and certainly, the photosensitive chip is not limited to the area array photoelectric conversion chip, and those skilled in the art may select a suitable photosensitive chip according to actual conditions.
In an embodiment of the present application, the control chip is an FPGA chip. Particularly, the FPGA chip can meet the data processing requirements of a plurality of high-resolution high-speed photosensitive chips so as to avoid data loss caused by untimely processing when the data processing capacity is large.
In an embodiment of the present application, as shown in fig. 5 and 6, the image processing apparatus further includes a frame 70, the frame 70 has an accommodating cavity, and the first circuit board 10 and the photosensitive chip 20 are located in the accommodating cavity. Specifically, the first circuit board and the photosensitive chip are arranged in the accommodating cavity of the frame body, so that the image processing device can be conveniently arranged at a proper position for image scanning, the length of a scanning area of the image processing device is larger than or equal to the width d of an object to be scanned, and a complete image can be obtained through scanning.
In an embodiment of the application, the control portion controls the photosensitive chip and the light source to start to operate simultaneously, and the control portion controls the photosensitive chip to send the obtained electric signal to the control chip and controls the light source to stop operating simultaneously. Specifically, the control mode ensures that the photosensitive chip and the light source start to work simultaneously, and the photosensitive chip stops working after obtaining an electric signal, namely the control chip controls the lighting time sequence of the light source to be synchronous with a frame signal, so that the problem that the imaging quality is satisfied by long-time lighting due to poor synchronism in the prior art is solved, and electric energy is saved.
More specifically, fig. 7 shows a control timing diagram of the control chip according to an embodiment of the present application, where a curve 1 is a timing diagram of a frame pulse, a curve 2 is a timing diagram of one exposure for one frame, t is a time of one exposure, a curve 3 is a timing diagram of one unit pixel through which an object to be scanned passes, t1 is a time of one unit pixel through which a light source is turned on, a curve 4 is a timing diagram of turning on the light source, and t2 is a time of one turning on the light source. As shown in fig. 6, the object to be scanned moves in the arrow direction, the time t1 when the object to be scanned passes through one unit pixel is longer than the power lighting time t2, and the moving distance of the object to be scanned relative to the photosensitive chip in the lighting time t2 does not exceed the width of one unit pixel or is much shorter than the width of one unit pixel, and in the limit, the object to be scanned is considered to have almost no movement, so that the imaging ghost image can be avoided in one exposure time t of one frame.
In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the technical solutions of the present application will be described below with reference to specific embodiments.
Examples
As shown in fig. 1, the image processing apparatus of the present embodiment includes a first circuit board 10, photosensitive chips 20, a control chip 30, a light source 40, a second circuit board 50 and a cable 60, wherein the control chip 30 is an FPGA chip, the cable 60 is a flat cable, 4 photosensitive chips 20 are arranged on the first circuit board at intervals and are arranged in a row, the control chip 30 is arranged on the second circuit board 50 and is electrically connected with the light source 40, the first circuit board 10 and the second circuit board 50 are connected by a cable, 4 cables 60 are in one-to-one correspondence with 4 photosensitive chips 20, and one cable 60 transmits an electrical signal of one photosensitive chip 20.
In the working process of the image processing apparatus of this embodiment, the control chip 30 sends a synchronous control signal to each of the photosensitive chips 20 and the light source 40, and controls each of the photosensitive chips 20 and the light source 40 to start working at the same time, each of the photosensitive chips 20 converts an optical signal reflected by an object to be scanned into an electrical signal, each of the photosensitive chips 20 synchronously transmits the electrical signal to the control chip 30 through the corresponding cable 60, and the control chip 30 controls the light source 40 to stop working at the same time as the data is synchronously transmitted.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
in the image processing apparatus of this application, a plurality of sensitization chips set up on first circuit board at interval, control chip's control part is connected with first circuit board electricity in order to send synchronous control signal to each sensitization chip, control part all conveys control signal to first circuit board promptly, first circuit board of rethread sends control signal to sensitization chip like this, make the synchronism of the signal that sensitization chip received better, and, control chip is difficult for postponing to the controller, the synchronism of signal has further been guaranteed better, the problem of signal asynchronization that the controller sent a plurality of control signals respectively to a plurality of cameras to lead to has been avoided.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. An image processing apparatus characterized by comprising:
a first circuit board;
a plurality of photosensitive chips arranged on the first circuit board at intervals;
and the control chip comprises a control part which is electrically connected with the first circuit board so as to send a synchronous control signal to each photosensitive chip.
2. The image processing apparatus according to claim 1, characterized by further comprising:
and the light source is electrically connected with the control chip, and the control chip controls the lighting of the light source.
3. The image processing apparatus according to claim 1, wherein the control chip further comprises:
and the storage part is electrically connected with the first circuit board to store the electric signals obtained by the photosensitive chips.
4. The image processing apparatus according to claim 1, characterized by further comprising:
the second circuit board, control chip sets up on the second circuit board, first circuit board passes through the second circuit board with control chip electricity is connected.
5. The image processing apparatus according to claim 4, characterized in that the image processing apparatus further comprises:
and the cable is used for connecting the first circuit board and the second circuit board.
6. The image processing apparatus according to any one of claims 1 to 5, wherein a plurality of the photosensitive chips are arranged in an array.
7. The image processing apparatus according to any one of claims 1 to 5, wherein each of the photosensitive chips is an area array photoelectric conversion chip.
8. The image processing apparatus according to any one of claims 1 to 5, wherein the control chip is an FPGA chip.
9. The image processing apparatus according to any one of claims 1 to 5, characterized by further comprising:
the frame body is provided with an accommodating cavity, and the first circuit board and the photosensitive chip are located in the accommodating cavity.
10. The image processing apparatus according to claim 2, wherein the control section controls the photosensitive chip and the light source to start operating simultaneously, and the control section controls the photosensitive chip to send the obtained electric signal to the control chip and controls the light source to stop operating simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911303767.0A CN111031209B (en) | 2019-12-17 | 2019-12-17 | Image processing apparatus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911303767.0A CN111031209B (en) | 2019-12-17 | 2019-12-17 | Image processing apparatus |
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| CN111031209A true CN111031209A (en) | 2020-04-17 |
| CN111031209B CN111031209B (en) | 2021-11-05 |
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