CN111030229B - Charge-discharge control circuit - Google Patents
Charge-discharge control circuit Download PDFInfo
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- CN111030229B CN111030229B CN201911339013.0A CN201911339013A CN111030229B CN 111030229 B CN111030229 B CN 111030229B CN 201911339013 A CN201911339013 A CN 201911339013A CN 111030229 B CN111030229 B CN 111030229B
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- 238000007599 discharging Methods 0.000 claims abstract description 40
- 238000007600 charging Methods 0.000 claims abstract description 39
- 238000006243 chemical reaction Methods 0.000 claims abstract description 34
- 239000003990 capacitor Substances 0.000 claims description 18
- 238000010277 constant-current charging Methods 0.000 claims description 6
- 230000003247 decreasing effect Effects 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 3
- 238000007781 pre-processing Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 5
- 230000009123 feedback regulation Effects 0.000 abstract description 3
- 230000004044 response Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010281 constant-current constant-voltage charging Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000010076 replication Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0068—Battery or charger load switching, e.g. concurrent charging and load supply
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- Charge And Discharge Circuits For Batteries Or The Like (AREA)
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Abstract
A charge and discharge control circuit comprising: the device comprises a signal acquisition unit, an A/D conversion unit, a charge and discharge control unit, a charge and discharge management unit, a D/A conversion unit and a power output unit. The charge and discharge control circuit is controlled based on a Field Programmable Gate Array (FPGA), has high processing speed and real-time response, small area and controllable cost, and can be produced in large scale. The method realizes various charging and discharging control management such as high-precision constant current, constant voltage, constant resistance, constant power and slope control through direct output, proportional-integral feedback regulation, AD/zero calibration and other modes.
Description
Technical Field
The invention belongs to the technical field of power battery charging and discharging, and particularly relates to a charging and discharging control circuit.
Background
The power battery charging and discharging control is realized by a general hardware circuit or a microcontroller (CPU) or a Digital Signal Processor (DSP) and other controllers. The hardware circuit mode has large area, high debugging difficulty and high cost, and is not beneficial to large-scale replication production; the CPU/DSP mode is easy to realize, but has low speed and poor real-time performance.
Disclosure of Invention
In order to solve the above problems, the present invention provides a charge and discharge control circuit, including:
the signal acquisition unit is used for acquiring circuit signals in the circuit and sending the circuit signals to the A/D conversion unit;
the A/D conversion unit is used for converting the circuit signal sent by the signal acquisition unit into a digital signal and sending the digital signal to the charge and discharge control unit; the A/D conversion unit is connected with the signal acquisition unit;
the charging and discharging control unit is used for sending the digital signals sent by the A/D conversion unit to the charging and discharging management unit, executing a preset operation mode according to the instruction of the charging and discharging management unit and sending a mode control signal to the D/A conversion unit; the charging and discharging control unit is connected with the A/D conversion unit through an SPI bus;
the charge and discharge management unit is used for controlling the charge and discharge control unit to execute a preset operation mode according to the digital signal sent by the charge and discharge control unit; the charging and discharging management unit is connected with the charging and discharging control unit through an isolation SPI bus;
the D/A conversion unit is used for converting the mode control signal sent by the charge and discharge control unit into an analog signal; the D/A conversion unit is connected with the charge and discharge control unit through the SPI bus;
the power output unit is used for controlling the output of the circuit according to the analog signal sent by the D/A conversion unit; the power output unit is connected with the D/A conversion unit.
Preferably, the circuit signal comprises a voltage and/or a current.
Preferably, the charge and discharge control unit includes an FPGA, and the charge and discharge management unit includes an MCU.
Preferably, the power output unit includes: a diode D1, a diode D2, a comparator U1, a comparator U2, a comparator U3, a comparator U4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C1, a capacitor C2, a transistor M1, and a transistor M2, wherein an anode of the diode D1 is connected to a power supply and a cathode of the diode D1 is connected to a collector of the transistor M1, an emitter of the transistor M1 is connected to the resistor R2 and a first terminal of the resistor R4, respectively, a second terminal of the resistor R2 is connected to a cathode of the diode D2 and a first input terminal of the comparator U2, an anode of the diode D2 is connected to a collector of the transistor M2, an emitter of the transistor M2 is connected to a first terminal of the resistor R7, a first terminal of the resistor R8 and a first terminal of the comparator U4, and a second terminal of the comparator U4 are grounded, a second end of the resistor R7 is connected to a base of the transistor M2 and a first end of the resistor R6, a second end of the resistor R6 is connected to an output end of the comparator U3 and a first end of the capacitor C2, a second end of the capacitor C2 is connected to a first end of the resistor R5, a second end of the resistor R5 is connected to a first input end of the comparator U3, an output end of the comparator U4 is connected to a second input end of the comparator U3, a first input end of the comparator U3 is connected to a discharging D/a control port, a second input end of the comparator U3626 is connected to a discharging feedback signal port, a second input end of the comparator U2 is connected to a first end of the resistor R2, an output end of the comparator U1 is connected to a first end of the resistor R1, and an output end of the comparator U1 is connected to a first end of the capacitor C1 and a first end of the resistor R539r 3, the second end of the capacitor C1 is connected to the second end of the resistor R1, the second end of the resistor R3 is connected to the second end of the resistor R4 and the base of the transistor M1, respectively, and the first input end of the comparator U1 is connected to the charging feedback signal port and the second input end is connected to the charging D/a control port.
Preferably, the preset operation mode includes a constant current charging mode, a constant resistance mode, a constant power mode, a PI mode, and a slope mode.
Preferably, when the circuit is in the constant current charging mode, the charging and discharging control unit controls the power output unit to charge the circuit with a constant current.
Preferably, when the circuit is in the constant-resistance mode, the signal acquisition unit acquires a current voltage value of the circuit, and the charge-discharge control unit calculates a current control value according to the current voltage value and a preset constant resistance value and controls the power output unit to charge the circuit with the current control value.
Preferably, when the circuit is in the constant power mode, the signal acquisition unit acquires a current voltage value of the circuit, and the charge-discharge control unit calculates a current control value according to the current voltage value and a preset constant power value and controls the power output unit to charge the circuit with the current control value.
Preferably, when in the PI mode, the signal acquisition unit acquires the current voltage value of the circuit three times and takes a median value, the charge and discharge control unit sets an initial value, and sequentially calculates E (k), (Kp + Ki) xe (k), Kp (k-1), U (k-1) + (Kp + Ki) E (k) and U (k-1) + (Kp + Ki) E (k) -Kp E (k-1) to generate a PI increment U (k), and limits an output range, outputs preprocessing, and sets a next calculation initial value, thereby outputting U (k), and the power output unit charges and discharges the circuit by U (k); wherein, E (k) is the current error signal, E (k-1) is the last error signal, U (k) is the current output signal, E (k-1) is the last output signal, Kp is the proportionality coefficient, and Ki is the integral coefficient.
Preferably, when the circuit is in the slope mode, the signal acquisition unit acquires the initial current of the circuit, and the charge and discharge control unit judges whether the step length increasing/decreasing operation time is reached, if so; executing step size adding/subtracting operation; if not, returning to the signal acquisition unit to acquire the initial current operation of the circuit; the charge and discharge control unit judges whether the step length is increased or decreased and then whether the step length exceeds the termination current, if not, the charge and discharge control unit returns to the signal acquisition unit to acquire the initial current operation of the circuit; and if so, the charge and discharge control unit executes amplitude limiting processing, and the power output unit charges and discharges the circuit by using the current value after the amplitude limiting processing until the time is finished.
The charge and discharge control circuit is controlled based on a Field Programmable Gate Array (FPGA), has high processing speed and real-time response, small area and controllable cost, and can be produced in large scale. The method realizes various charging and discharging control management such as high-precision constant current, constant voltage, constant resistance, constant power and slope control through direct output, proportional-integral feedback regulation, AD/zero calibration and other modes.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a connection block diagram of a charge and discharge control circuit according to the present invention;
FIG. 2 is a schematic diagram of a charge/discharge control circuit according to the present invention;
FIG. 3 is a schematic diagram of a power output unit of a charge/discharge control circuit according to the present invention;
fig. 4 is a schematic flow chart of a constant current charging mode of the charge and discharge control circuit according to the present invention;
FIG. 5 is a schematic diagram of a constant-resistance mode of the charge/discharge control circuit according to the present invention;
fig. 6 is a schematic diagram of a constant power mode flow of a charge and discharge control circuit according to the present invention;
FIG. 7 is a schematic diagram of a PI mode flow of a charge/discharge control circuit according to the present invention;
fig. 8 is a schematic diagram of a slope mode process of a charge/discharge control circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
As shown in fig. 1 to 3, in an embodiment of the present application, the present application provides a charge and discharge control circuit, including: the system comprises a signal acquisition unit, an A/D conversion unit, a charge and discharge control unit, a charge and discharge management unit, a D/A conversion unit and a power output unit, and the detailed description of each part is described below.
As shown in fig. 1 to 3, in an embodiment of the present application, the present application provides a charge and discharge control circuit, including:
the signal acquisition unit is used for acquiring circuit signals in the circuit and sending the circuit signals to the A/D conversion unit;
the A/D conversion unit is used for converting the circuit signal sent by the signal acquisition unit into a digital signal and sending the digital signal to the charge and discharge control unit; the A/D conversion unit is connected with the signal acquisition unit;
the charging and discharging control unit is used for sending the digital signals sent by the A/D conversion unit to the charging and discharging management unit, executing a preset operation mode according to the instruction of the charging and discharging management unit and sending a mode control signal to the D/A conversion unit; the charging and discharging control unit is connected with the A/D conversion unit through an SPI bus;
the charge and discharge management unit is used for controlling the charge and discharge control unit to execute a preset operation mode according to the digital signal sent by the charge and discharge control unit; the charging and discharging management unit is connected with the charging and discharging control unit through an isolation SPI bus;
the D/A conversion unit is used for converting the mode control signal sent by the charge and discharge control unit into an analog signal; the D/A conversion unit is connected with the charge and discharge control unit through the SPI bus;
the power output unit is used for controlling the output of the circuit according to the analog signal sent by the D/A conversion unit; the power output unit is connected with the D/A conversion unit.
In an embodiment of the application, the circuit signal comprises a voltage and/or a current.
In the embodiment of the application, the charge and discharge control unit comprises an FPGA, and the charge and discharge management unit comprises an MCU.
As shown in fig. 3, in the embodiment of the present application, the power output unit includes: a diode D1, a diode D2, a comparator U1, a comparator U2, a comparator U3, a comparator U4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C1, a capacitor C2, a transistor M1, and a transistor M2, wherein an anode of the diode D1 is connected to a power supply and a cathode of the diode D1 is connected to a collector of the transistor M1, an emitter of the transistor M1 is connected to the resistor R2 and a first terminal of the resistor R4, respectively, a second terminal of the resistor R2 is connected to a cathode of the diode D2 and a first input terminal of the comparator U2, an anode of the diode D2 is connected to a collector of the transistor M2, an emitter of the transistor M2 is connected to a first terminal of the resistor R7, a first terminal of the resistor R8 and a first terminal of the comparator U4, and a second terminal of the comparator U4 are grounded, a second end of the resistor R7 is connected to a base of the transistor M2 and a first end of the resistor R6, a second end of the resistor R6 is connected to an output end of the comparator U3 and a first end of the capacitor C2, a second end of the capacitor C2 is connected to a first end of the resistor R5, a second end of the resistor R5 is connected to a first input end of the comparator U3, an output end of the comparator U4 is connected to a second input end of the comparator U3, a first input end of the comparator U3 is connected to a discharging D/a control port, a second input end of the comparator U3626 is connected to a discharging feedback signal port, a second input end of the comparator U2 is connected to a first end of the resistor R2, an output end of the comparator U1 is connected to a first end of the resistor R1, and an output end of the comparator U1 is connected to a first end of the capacitor C1 and a first end of the resistor R539r 3, the second end of the capacitor C1 is connected to the second end of the resistor R1, the second end of the resistor R3 is connected to the second end of the resistor R4 and the base of the transistor M1, respectively, and the first input end of the comparator U1 is connected to the charging feedback signal port and the second input end is connected to the charging D/a control port.
As shown in fig. 4-8, in the embodiment of the present application, a charge and discharge control mode based on the charge and discharge control circuit is designed according to the charge and discharge requirements of the power battery and the charge and discharge characteristics of the power battery, where a constant current charge mode flow is shown in fig. 4, a constant resistance charge and discharge mode flow is shown in fig. 5, a constant power charge and discharge mode flow is shown in fig. 6, a constant current and constant voltage charge and constant current discharge mode flow is shown in fig. 7, and a slope charge and discharge mode flow is shown in fig. 8.
The constant-current constant-voltage charging and constant-current discharging mode adopts a proportional integral mode, the quick adjusting function of charging and discharging is realized, the operation of a test system is stable, and the coefficient setting of the proportional integral can be adjusted on line through an SPI bus.
In the embodiment of the present application, as shown in fig. 4, when in the constant current charging mode, the charging and discharging control unit controls the power output unit to charge the circuit with a constant current.
As shown in fig. 5, in the embodiment of the present application, when the circuit is in the constant resistance mode, the signal acquisition unit acquires a current voltage value of the circuit, and the charge and discharge control unit calculates a current control value according to the current voltage value and a preset constant resistance value, and controls the power output unit to charge the circuit with the current control value.
As shown in fig. 6, in the embodiment of the present application, when the circuit is in the constant power mode, the signal acquisition unit acquires a current voltage value of the circuit, and the charge and discharge control unit calculates a current control value according to the current voltage value and a preset constant power value, and controls the power output unit to charge the circuit with the current control value.
As shown in fig. 7, in the embodiment of the present application, when in the PI mode, the signal acquisition unit acquires three current voltage values of the circuit and takes a median value, the charge and discharge control unit sets an initial value, and sequentially calculates E (k), (Kp + Ki) × E (k), Kp × E (k-1), U (k-1) + (Kp + Ki) × E (k) and U (k-1) + (Kp + Ki) (k) -Kp × E (k-1) to generate a PI increment U (k), and limits an output range, outputs preprocessing, and sets a next calculation initial value to output U (k), and the power output unit outputs U (k) to the charge and discharge circuit; wherein, E (k) is the current error signal, E (k-1) is the last error signal, U (k) is the current output signal, E (k-1) is the last output signal, Kp is the proportionality coefficient, and Ki is the integral coefficient.
As shown in fig. 8, in the embodiment of the present application, when the circuit is in the slope mode, the signal acquisition unit acquires the initial current of the circuit, and the charge/discharge control unit determines whether the step length increasing/decreasing operation time is reached, if so; executing step size adding/subtracting operation; if not, returning to the signal acquisition unit to acquire the initial current operation of the circuit; the charge and discharge control unit judges whether the step length is increased or decreased and then whether the step length exceeds the termination current, if not, the charge and discharge control unit returns to the signal acquisition unit to acquire the initial current operation of the circuit; and if so, the charge and discharge control unit executes amplitude limiting processing, and the power output unit charges and discharges the circuit by using the current value after the amplitude limiting processing until the time is finished.
The charge and discharge control circuit is controlled based on a Field Programmable Gate Array (FPGA), has high processing speed and real-time response, small area and controllable cost, and can be produced in large scale. The method realizes various charging and discharging control management such as high-precision constant current, constant voltage, constant resistance, constant power and slope control through direct output, proportional-integral feedback regulation, AD/zero calibration and other modes.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.
Claims (9)
1. A charge and discharge control circuit, comprising:
the signal acquisition unit is used for acquiring circuit signals in the circuit and sending the circuit signals to the A/D conversion unit;
the A/D conversion unit is used for converting the circuit signal sent by the signal acquisition unit into a digital signal and sending the digital signal to the charge and discharge control unit; the A/D conversion unit is connected with the signal acquisition unit;
the charging and discharging control unit is used for sending the digital signals sent by the A/D conversion unit to the charging and discharging management unit, executing a preset operation mode according to the instruction of the charging and discharging management unit and sending a mode control signal to the D/A conversion unit; the charging and discharging control unit is connected with the A/D conversion unit through an SPI bus;
the charge and discharge management unit is used for controlling the charge and discharge control unit to execute a preset operation mode according to the digital signal sent by the charge and discharge control unit; the charging and discharging management unit is connected with the charging and discharging control unit through an isolation SPI bus;
the D/A conversion unit is used for converting the mode control signal sent by the charge and discharge control unit into an analog signal; the D/A conversion unit is connected with the charge and discharge control unit through the SPI bus;
the power output unit is used for controlling the output of the circuit according to the analog signal sent by the D/A conversion unit; the power output unit is connected with the D/A conversion unit;
wherein the power output unit includes: a diode D1, a diode D2, a comparator U1, a comparator U2, a comparator U3, a comparator U4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C1, a capacitor C2, a transistor M1, and a transistor M2, wherein an anode of the diode D1 is connected to a power supply and a cathode of the diode D1 is connected to a collector of the transistor M1, an emitter of the transistor M1 is connected to the resistor R2 and a first terminal of the resistor R4, respectively, a second terminal of the resistor R2 is connected to a cathode of the diode D2 and a first input terminal of the comparator U2, an anode of the diode D2 is connected to a collector of the transistor M2, an emitter of the transistor M2 is connected to a first terminal of the resistor R7, a first terminal of the resistor R8 and a first terminal of the comparator U4, and a second terminal of the comparator U4 are grounded, a second end of the resistor R7 is connected to a base of the transistor M2 and a first end of the resistor R6, a second end of the resistor R6 is connected to an output end of the comparator U3 and a first end of the capacitor C2, a second end of the capacitor C2 is connected to a first end of the resistor R5, a second end of the resistor R5 is connected to a first input end of the comparator U3, an output end of the comparator U4 is connected to a second input end of the comparator U3, a first input end of the comparator U3 is connected to a discharging D/a control port, a second input end of the comparator U3626 is connected to a discharging feedback signal port, a second input end of the comparator U2 is connected to a first end of the resistor R2, an output end of the comparator U1 is connected to a first end of the resistor R1, and an output end of the comparator U1 is connected to a first end of the capacitor C1 and a first end of the resistor R539r 3, the second end of the capacitor C1 is connected to the second end of the resistor R1, the second end of the resistor R3 is connected to the second end of the resistor R4 and the base of the transistor M1, respectively, and the first input end of the comparator U1 is connected to the charging feedback signal port and the second input end is connected to the charging D/a control port.
2. The charge and discharge control circuit of claim 1, wherein the circuit signal comprises a voltage and/or a current.
3. The charge and discharge control circuit according to claim 1, wherein the charge and discharge control unit comprises an FPGA, and the charge and discharge management unit comprises an MCU.
4. The charge and discharge control circuit of claim 1, wherein the preset operation modes include a constant current charging mode, a constant resistance mode, a constant power mode, a PI mode, and a slope mode.
5. The charge and discharge control circuit according to claim 4, wherein when in the constant current charging mode, the charge and discharge control unit controls the power output unit to charge the circuit with a constant current.
6. The charging and discharging control circuit according to claim 4, wherein when the circuit is in the constant resistance mode, the signal acquisition unit acquires a current voltage value of the circuit, and the charging and discharging control unit calculates a current control value according to the current voltage value and a preset constant resistance value, and controls the power output unit to charge the circuit with the current control value.
7. The charging and discharging control circuit according to claim 4, wherein when the circuit is in the constant power mode, the signal acquisition unit acquires a current voltage value of the circuit, and the charging and discharging control unit calculates a current control value according to the current voltage value and a preset constant power value and controls the power output unit to charge the circuit with the current control value.
8. The charge and discharge control circuit according to claim 4, wherein when in the PI mode, the signal acquisition unit acquires three times of current voltage values of the circuit and takes a median value, the charge and discharge control unit sets an initial value, and sequentially calculates E (k), (Kp + Ki) xe (k), Kp E (k-1), U (k-1) + (Kp + Ki) E (k), and U (k-1) + (Kp + Ki) E (k) -Kp E (k-1) to generate a PI increment U (k), and limits an output range, outputs the preprocessing, and sets a next calculation initial value to output U (k), and the power output unit charges and discharges the circuit with U (k); wherein, E (k) is the current error signal, E (k-1) is the last error signal, U (k) is the current output signal, U (k-1) is the last output signal, Kp is the proportionality coefficient, and Ki is the integral coefficient.
9. The charging and discharging control circuit according to claim 4, wherein when in the slope mode, the signal acquisition unit acquires the circuit initial current, and the charging and discharging control unit determines whether the step length increasing/decreasing operation time is reached, and if so; executing step size adding/subtracting operation; if not, returning to the signal acquisition unit to acquire the initial current operation of the circuit; the charge and discharge control unit judges whether the step length is increased or decreased and then whether the step length exceeds the termination current, if not, the charge and discharge control unit returns to the signal acquisition unit to acquire the initial current operation of the circuit; and if so, the charge and discharge control unit executes amplitude limiting processing, and the power output unit charges and discharges the circuit by using the current value after the amplitude limiting processing until the time is finished.
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| CN201911339013.0A CN111030229B (en) | 2019-12-23 | 2019-12-23 | Charge-discharge control circuit |
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Effective date of registration: 20211122 Address after: 300384 No. 6 Huake No. 7 Road, Binhai New Area, Tianjin Binhai High-tech Industrial Development Zone Patentee after: CETC Energy Co.,Ltd. Address before: 300384 No. 6 Huake No. 7 Road, Binhai New Area, Tianjin Binhai High-tech Industrial Development Zone Patentee before: The 18th Research Institute of China Electronics Technology Group Corporation |
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Address after: 300384 No. 6 Huake No. 7 Road, Binhai New Area, Tianjin Binhai High-tech Industrial Development Zone Patentee after: CETC Blue Sky Technology Co.,Ltd. Address before: 300384 No. 6 Huake No. 7 Road, Binhai New Area, Tianjin Binhai High-tech Industrial Development Zone Patentee before: CETC Energy Co.,Ltd. |