CN111029303B - Integrated circuit package and method of forming the same - Google Patents

Integrated circuit package and method of forming the same Download PDF

Info

Publication number
CN111029303B
CN111029303B CN201910955789.9A CN201910955789A CN111029303B CN 111029303 B CN111029303 B CN 111029303B CN 201910955789 A CN201910955789 A CN 201910955789A CN 111029303 B CN111029303 B CN 111029303B
Authority
CN
China
Prior art keywords
dies
die
dielectric
forming
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910955789.9A
Other languages
Chinese (zh)
Other versions
CN111029303A (en
Inventor
余振华
余国宠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/529,235 external-priority patent/US11171076B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN111029303A publication Critical patent/CN111029303A/en
Application granted granted Critical
Publication of CN111029303B publication Critical patent/CN111029303B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2512—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2512—Layout
    • H01L2224/25171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

The method includes placing a first plurality of dies over a carrier. The first plurality of dies includes at least a first logic die and a first memory die, and a second plurality of dies is placed over the first plurality of dies. The second plurality of dies is electrically coupled to the first plurality of dies and includes at least a second logic die and a second memory die. The third plurality of dies is disposed over the second plurality of dies and is electrically coupled to the first plurality of dies and the second plurality of dies. The third plurality of dies includes at least a third logic die and a third memory die. The method also includes forming electrical connections over the first, second, and third pluralities of dies that are electrically coupled to the first, second, and third pluralities of dies. Embodiments of the invention also relate to integrated circuit packages and methods of forming the same.

Description

Integrated circuit package and method of forming the same
Technical Field
Embodiments of the invention relate to integrated circuit packages and methods of forming the same.
Background
Packages for integrated circuits are becoming more complex, with more device dies integrated into the same package to achieve more functionality. For example, integrated system dies (soics) have been developed to include multiple device dies, such as processor and memory cubes, in the same package. In SoIC, device dies formed using different technologies and having different functions can be bonded in 2D side-by-side and 3D stacked fashion to form a system with higher computational efficiency, bandwidth, functional packing density, lower communication delay, and energy consumption per bit of data.
Disclosure of Invention
Some embodiments of the invention relate to a method of forming an integrated circuit package, the method comprising: placing a first plurality of dies over a carrier, wherein the first plurality of dies includes at least a first logic die and a first memory die; placing a second plurality of dies over the first plurality of dies, wherein the second plurality of dies is electrically coupled to the first plurality of dies, and wherein the second plurality of dies includes at least a second logic die and a second memory die; placing a third plurality of dies over the second plurality of dies, wherein the third plurality of dies is electrically coupled to the first plurality of dies and the second plurality of dies, and wherein the third plurality of dies includes at least a third logic die and a third memory die; and forming electrical connections over the first, second, and third plurality of dies that are electrically coupled to the first, second, and third plurality of dies.
Another embodiment of the invention is directed to a method of forming an integrated circuit package, the method comprising: placing a first layer of dies; bonding a second tier die to the first tier die; filling a first gap filling dielectric material, wherein the first gap filling dielectric material is filled into gaps between the first layer of dies and gaps between the second layer of dies; forming a first via through the second tier die, wherein the first via electrically couples the second tier die to the first tier die; forming a metal pad electrically coupled to the first via over the first gap-filling dielectric material; forming a dielectric layer covering the metal pad; bonding a third tier die to the dielectric layer, wherein each tier of the first tier die, the second tier die, and the third tier die includes at least a logic die and a memory die; and forming a second via through the third level die to electrically couple to the metal pad.
Yet another embodiment of the invention is directed to an integrated circuit package comprising: a first plurality of dies located over a carrier, wherein the first plurality of dies includes at least a first logic die and a first memory die; a second plurality of dies located above the first plurality of dies, wherein the second plurality of dies is electrically coupled to the first plurality of dies, and wherein the second plurality of dies includes at least a second logic die and a second memory die; a first dielectric layer over the second plurality of dies; a first via penetrating the first dielectric layer and the second plurality of dies to electrically couple to the first plurality of dies; a first metal pad over and contacting the first via; a second dielectric layer covering the first metal pad; a third plurality of dies over and bonded to the second dielectric layer; and a second via penetrating the second dielectric layer and the third plurality of dies to electrically couple to the first metal pad.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1 illustrates a cross-sectional view of a package according to some embodiments.
Fig. 2, 3, and 4 illustrate top views of tri-layer packages according to some embodiments.
Fig. 5-12 illustrate cross-sectional views of some packages according to some embodiments.
Fig. 13-24 illustrate cross-sectional views of systems having packages contained therein, according to some embodiments.
Fig. 25-31 illustrate cross-sectional views of intermediate stages in formation of a package, according to some embodiments.
Fig. 32-39 illustrate cross-sectional views of intermediate stages in formation of a package, according to some embodiments.
Fig. 40-44 illustrate cross-sectional views of intermediate stages in formation of a package, according to some embodiments.
Figure 45 illustrates a process flow for forming a package according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Packages and methods of forming the same are provided according to various embodiments. An intermediate stage of formation of a package is shown according to some embodiments. Some variations of some embodiments are discussed. Like reference numerals are used to refer to like elements throughout the various views and exemplary embodiments. According to some embodiments of the invention, an in-memory computing package is formed. The in-memory computing package includes a plurality of layers, each layer including a logic die and a memory die. The logic dies in a layer may be submerged in memory dies (and possibly other logic dies) in the same layer or in other layers above and/or below the layer. Similarly, memory dies in a layer may be submerged in logic dies (and possibly other logic dies) in the same layer or in other layers above and/or below the layer. With this arrangement, computational efficiency may be improved, the bandwidth of the system may be increased, and latency may be reduced due to the close proximity and efficient layout of the die.
Fig. 1 illustrates a cross-sectional view of an in-memory computing package 100. According to some embodiments of the invention, the term "in-memory computation" refers to a structure in which a logic die implementing a computation function is submerged in a memory die accessed by the logic die. The in-memory computing package 100 is sometimes referred to as a system-on-integrated-chip (SoIC) package. In fig. 1 and subsequent figures, the letter "L" is used to indicate that the respective die is a logic die, and the letter "M" is used to indicate that the respective die is a memory die. The logic die L and the memory die M may be followed by numbers for identification purposes. It should be understood that fig. 1 shows an example, and in other embodiments, each die as shown in fig. 1 (and fig. 2-12) may be a logic die or a memory die. Further, the number of logic die and the number of memory die in each layer may be any number equal to or greater than 1, depending on design requirements. It should be understood that although a three-layer package is shown as an example, the in-memory computing package may include more than three layers, such as four, five, or more layers.
According to some embodiments of the invention, the logic die comprises a single core die or a multi-core logic die. The logic die may be an Application Processor (AP) die, a Graphics Processing Unit (GPU) die, a Field Programmable Gate Array (FPGA) die, an Application Specific Integrated Circuit (ASIC) die, an input-output (IO) die, a Network Processing Unit (NPU) die, a Tensor Processing Unit (TPU) die, an Artificial Intelligence (AI) engine die, and so forth. In the in-memory computing package 100, and possibly in each layer, different types of logic dies may be mixed.
According to some embodiments of the invention, the memory die may include a Static Random Access Memory (SRAM) die, a Dynamic Random Access Memory (DRAM) die, a wide I/O memory die, a NAND memory die, a Resistive Random Access Memory (RRAM) die, a Magnetoresistive Random Access Memory (MRAM) die, and the like. The memory die may or may not have a controller therein. The memory die may also be in the form of a single memory die or pre-stacked memory cells. In the in-memory computing package 100, and possibly in each layer, different types of memory dies may be mixed.
Referring again to FIG. 1, according to some example embodiments, there is a layer-1, a layer-2 located above layer-1, and a layer-3 located above layer-2. Adjacent layers are joined to one another by direct dielectric bonding (also sometimes referred to as dielectric-to-dielectric bonding or fusion bonding) or hybrid bonding. Hybrid bonding includes dielectric-to-dielectric bonding and metal-to-metal bonding. Each layer may include one or more logic dies L and one or more memory dies M. The logic die L and the memory die M may include a semiconductor substrate 20, which may be a silicon substrate. Interconnect structures 22 are formed on the respective semiconductor substrates 20 and are used to interconnect devices in the respective dies. Further, bond pads 24 may be formed within interconnect structure 22 or coplanar with a surface of a respective die L or M.
Vias 30 (including 30-1, 30-2, and 30-3) are formed through semiconductor substrate 20 and are used to electrically and signally couple dies L and M (in different layers or the same layer) together. Vias 30 may be used in different ways to interconnect dies in different layers. For example, vias 30-1 and 30-2 are used in combination to interconnect a metal pad (pad 24A) in logic die L2 with a metal pad (pad 24B) in memory M3 through metal pad 76, metal pad 76 being located over vias 30-1 and 30-2 and contacting vias 30-1 and 30-2. Vias 30-3, on the other hand, are used to connect metal pad 24A in logic die L2 with metal pad 24B in memory M3. Vias 32 through dielectric region 38 are used to connect memory die M1 (in layer-1) to top metal pads 80 through metal pads 76.
FIG. 2 shows a top view of layer-1, with an exemplary layout shown. For example, the illustrative embodiment includes a memory die M1 surrounded (immersed) by logic die L1, L2, L1 ', and L2'. As noted above, the illustrated layout of layer-1 (and layer-2 in FIG. 3 or layer-3 in FIG. 4) is an example, and in other embodiments, each of the illustrated dies L and M may also be a logic die or a memory die. According to some embodiments, memory die M1 is a single memory die. According to an alternative embodiment, memory die M1 is shown to represent multiple memory dies. For example, memory die M1A and M1B may be placed at the location of memory die M1, according to some embodiments. Memory dies M1A and M1B may be the same type of memory die, or may be different types of memory dies. According to an alternative embodiment, memory die M1C, M1D, M1E, and M1F may be placed at the location of memory die M1.
Fig. 3 shows a top view of layer-2, which includes logic die L3 surrounded by memory dies M2, M3, M2 ', and M3'. According to some embodiments, logic die L3 is a single logic die. According to an alternative embodiment, the illustrated logic die L3 represents multiple logic dies. For example, the logic die L3A and L3B may be placed at the location of the logic die L3, according to some embodiments. Logic die L3A and L3B may be the same type of logic die or may be different types of logic die. According to an alternative embodiment, the logic die L3C, L3D, L3E, and L3F may be placed at the location of the logic die L3.
Fig. 4 shows a top view of layer-3, which includes logic die L4 on the sides of memory dies M4 and M4'. According to some embodiments, logic die L4 is a single logic die. According to an alternative embodiment, the illustrated logic die L4 represents multiple logic dies. For example, the logic die L4A and L4B may be placed at the location of the logic die L4, according to some embodiments. Logic die L4A and L4B may be the same type of logic die or may be different types of logic die. According to an alternative embodiment, the logic die L4C, L4D, L4E, and L4F may be placed at the location of the logic die L4.
Fig. 5-12 illustrate cross-sectional views of an in-memory computing package according to some embodiments. These embodiments include different combinations of arrangements of logic die L and memory die M, where the dies L and M in different layers may be arranged face up or face down, and the bonding between adjacent layers may be face-to-face back bonding or face-to-face bonding. These embodiments also include different types of bonding methods, including direct dielectric bonding and hybrid bonding. Further, the interface of the in-memory computing package may include redistribution lines (RDLs) and solder areas, or alternatively metal pillars. The RDL and solder regions may be used for flip chip bonding and the metal posts may be used to form an integrated fan out (InFO) package. It should be understood that fig. 5 and 12 illustrate some exemplary combinations, and that the present invention encompasses other combinations. The embodiments shown in fig. 5 and 12 are also discussed in detail in the processes shown in fig. 25-44.
Referring to fig. 5, an in-memory computing package 100 includes a die in layer-1 placed face up. Throughout this specification, when a die is referred to as face-up, it means that a device (active device such as a transistor or a passive device such as a resistor, capacitor, or the like) faces upward toward the top surface of the corresponding semiconductor substrate in the die. Likewise, when a die is referred to as being face down, this means that the device is facing down toward the top surface of the corresponding substrate in the die. Layer-2 die such as M2, L3, and M3 are placed face down and bonded to the underlying layer-1 die by direct dielectric bonding and by face-to-face bonding. Layer-3 die L4 and M4 are placed face down and bonded to dielectric layer 78 in layer-2 by direct dielectric bonding. Layer-3 die L4 and M4 are bonded to the underlying layer-2 die by face-to-back bonding. RDL40 is formed over the layer-3 die and is electrically connected to the layer-1, layer-2, and layer-3 die through vias and metal pads. Solder regions 42 are formed over RDL40 and electrically coupled to RDL 40. The solder regions 42 may be used to bond the in-memory computing package 100 to other structures by flip-chip bonding.
FIG. 6 illustrates an in-memory computing package 100 according to some embodiments. These embodiments are similar to the embodiment in fig. 5, except that metal pillars 44 are formed above layer-3 die L4 and M4. The metal posts 44 may be formed of copper, copper alloy, or other similar metal. Dielectric layer 46 is formed to embed metal pillar 44 therein, and the top surface of dielectric layer 46 may be coplanar with the top surface of metal pillar 44. The dielectric layer 46 may be formed of a polymer, such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. The dielectric layer 46 may also be formed of an inorganic dielectric material, such as an oxide (e.g., silicon oxide or silicon oxynitride).
FIG. 7 illustrates an in-memory computing package 100 according to some embodiments. These embodiments are similar to the embodiment of fig. 5, except that the bonding between adjacent layers is a hybrid bonding rather than a direct dielectric bonding. For example, die L1 and M2 are bonded to each other by hybrid bonding, which includes metal-to-metal bonding between metal pads 24A and 24B, and dielectric-to-dielectric bonding between surface dielectric layer 26A in die L1 and surface dielectric layer 26B in die M2. M4 is bonded to underlying dielectric layer 78 and metal pad 76 by hybrid bonding, which includes bonding between dielectric layer 78 and surface dielectric layer 26C in die M4, and bonding between metal pad 24C and metal pad 76 in die M4. In the in-memory computing package 100, the RDL40 and the solder regions 42 are formed for bonding the in-memory computing package 100 to other package components.
FIG. 8 illustrates an in-memory computing package 100 according to some embodiments. These embodiments are similar to the embodiment in fig. 7, except that metal pillars 44 are formed above layer-3 die L4 and M4. The metal posts 44 may be formed of copper, copper alloy, or other similar metal. In the in-memory computing package 100, metal pillars 44 are formed in the dielectric layer 46 for bonding purposes, and the top surfaces of the metal pillars 44 are coplanar with the top surface of the dielectric layer 46.
FIG. 9 illustrates an in-memory computing package 100 according to some embodiments. These embodiments are similar to the embodiment in fig. 5, except that the dies are placed in the reverse order, such that the layer-1 die includes dies L4 and M4, and the layer-3 die includes dies L1, M2, and L2. However, it should be recognized that a tier-1 die may also include die L1, M1, and L2 (instead of die L4 and M4) as shown in the previous embodiments, and a tier-3 die may also include die L4 and M4 (instead of die L1, M1, and L2). Tier-1 dies, such as logic die L4 and memory die M4, are placed face down, and the bonding of tier-2 dies, such as logic die L3 and memory dies M2 and M3, to tier-1 dies L4 and M4 is a face-to-back bonding, which is achieved by direct dielectric bonding. For example, die L3, M2, and M3 are bonded to underlying dielectric layer 38A by direct dielectric bonding. In addition, layer-3 die L1, M1, and L2 were bonded to the layer-2 die by face-to-back bonding and direct dielectric bonding. In the in-memory computing package 100 as shown in fig. 9, the RDL40 and the solder area 42 are formed for bonding the in-memory computing package 100 to other package components.
FIG. 10 illustrates an in-memory computing package 100 according to some embodiments. These embodiments are similar to the embodiment in fig. 9, except that over layer-3 die L1, M1, and L2, metal pillar 44 is formed in dielectric layer 46 for bonding purposes, and the top surface of metal pillar 44 is coplanar with the top surface of dielectric layer 46.
FIG. 11 illustrates an in-memory computing package 100 according to some embodiments. These embodiments are similar to the embodiment in fig. 9, except that the layer-1 die, such as logic die L4 and memory die M4, are placed face down, and the layer-2 die to layer-1 die bonding, such as logic die L3 and memory dies M2 and M3, is a hybrid bonding by face-to-back bonding, according to some embodiments. Likewise, layer-3 die such as L1, M1, and L2 are also bonded to layer-2 die by face-to-back bonding and by hybrid bonding. In the in-memory computing package 100, the RDL40 and the solder areas 42 are formed for bonding the in-memory computing package 100 to other package components.
FIG. 12 illustrates an in-memory computing package 100 according to some embodiments. These embodiments are similar to the embodiment in fig. 11, except that over layer-3 die L1, M1, and L2, metal pillar 44 is formed in dielectric layer 46 for bonding purposes, and the top surface of metal pillar 44 is coplanar with the top surface of dielectric layer 46.
The package 100 as shown in fig. 5-12 is formed as a reconstituted wafer, which includes a plurality of packages having the structure shown in one of fig. 5-12. The respective wafer is then sawed such that the packages as shown in one of fig. 5 to 12 are formed into discrete packages 100.
Fig. 13-24 illustrate some exemplary embodiments to show how the in-memory computing package 100 may be used to form a larger package or system. According to some embodiments, the use of the device die is similar to the use of the in-memory computing package 100 shown in fig. 5-12. Details of the in-memory computing package 100 as shown in fig. 13-24 are not shown and may be found with reference to the embodiments shown in fig. 5-12. A surface bonding configuration of the in-memory computing package 100 is shown that indicates whether solder areas or metal posts are employed, depending on whether a flip-chip bonding or an InFO configuration is used. Also, some of the bond pads and RDLs for connecting to the solder regions and/or metal posts are not shown and do exist in the package. When there is more than one in-memory computing enclosure 100 in the same enclosure, the letter "a" or "B" may be added to the reference numeral "100" to identify the individual enclosures 100.
Fig. 13 illustrates the face-to-back bonding of computing packages 100A and 100B within a memory. The bonding is performed by flip-chip bonding, and the underfill 48 is disposed between the in- memory computing packages 100A and 100B. The resulting package 102 has metal posts 44 at its surface. Thus, package 102 may be used to form an InFO package.
Fig. 14 shows a package 102 comprising two packages 104A bonded to a package 104B by flip-chip bonding. Packages 104A and 104B are InFO packages. In accordance with some embodiments of the present invention, the formation of the InFO package 104A includes placing the corresponding in-memory computing package 100A over a carrier (not shown) through the die attach film 49 (adhesive film), encapsulating the in-memory computing package 100A in an encapsulant 50A such as a molding compound, performing planarization to make the surfaces (bottom surfaces shown) of the metal pillars 44 in the in-memory computing package 100A flush with the surface of the encapsulant 50A, and then forming the RDL52 and the solder regions 54. Package 104B is similarly formed except that additional vias 56 are formed prior to applying encapsulant 50B. The package 102 shown in fig. 14 may be used for flip chip bonding.
Fig. 15 shows a chip-on-package configuration in which in-memory computing package 100B is first used to form an InFO package 104B, and then in-memory computing package 100A (used as a chip) is bonded to InFO package 104B by flip-chip bonding. Sealant 50A is then dispensed to seal the in-memory computing package 100A therein. The package 102 shown in fig. 15 may be used for flip chip bonding. RDL51 is part of forming package 104B. The details of RDL51 are not shown.
Fig. 16 shows a package 102, which is an InFO package formed based on in-memory computing package 100. The formation process has already been described with reference to package 104A in fig. 14, and details are not repeated here. The packaging process used to form package 102 as shown in fig. 16 is a post RDL process, in which in-memory computing package 100 is first encapsulated in encapsulant 50, and after encapsulating in-memory computing package 100 in encapsulant 50, formation of RDL52 and corresponding dielectric layer 53 is performed.
Fig. 17 shows a package 102, which is a flip chip package formed based on the in-memory computing package 100. The packaging process used to form 102 as shown in fig. 16 is a RDL-first process in which RDL52 and corresponding dielectric layer 53 are formed first and in-memory computing package 100 is bonded to RDL52 by flip-chip bonding. The in-memory computing package 100 is then sealed in the encapsulant 50.
Fig. 18 illustrates a package 102' that includes the package 102 shown in fig. 16 bonded to a package substrate 58. The package substrate 58 may be a coreless substrate. Optionally, the package substrate 58 includes a core, and the RDLs are formed on opposite sides of the core. Underfill 48 is disposed between package 102 and package substrate 58.
Fig. 19 shows a package 102, which is an InFO package formed based on in-memory computing package 100. The formation process has already been described with reference to package 104B in fig. 14, and details are not repeated here. The packaging process used to form the package 102 as shown in fig. 19 is also a post RDL process.
Fig. 20 shows an enclosure 102' that includes an in-memory computing enclosure 100 and a memory stack (cube) 60, forming an InFO enclosure. Each memory stack 60 includes a plurality of memory dies 62 that are stacked and electrically interconnected. Memory stack 60 may be a High Bandwidth Memory (HBM) unit. The memory stack 60 and the in-memory computing package 100 are encapsulated in an encapsulant 50. RDL52 is formed to connect to memory stack 60 and in-memory computing package 100. According to some embodiments of the invention, the respective package is a high performance package. Thus, a heat sink 64 and metal lid 66 may be formed to connect to the in-memory computing package 100. The heat dissipation members 64 may be metal rods, metal fins, or the like. The InFO package is further bonded to a package substrate 58.
Fig. 21 illustrates a package 102' according to some embodiments of the invention. These embodiments are similar to the embodiment shown in FIG. 20, except that two in-memory computing packages 100 are shown. It should be understood that while two in-memory computing packages 100 are shown, there may be more (such as four, six, eight, etc.) in-memory computing packages 100. Similarly, in fig. 20 and 21, two memory stacks 60 are shown, while in a corresponding package 102', there may be more (such as four, six, eight, etc.) memory stacks 60.
Fig. 22 illustrates a package 102' according to some embodiments of the invention. These embodiments are similar to the embodiment shown in FIG. 20, except that instead of forming RDL52 on sealed in-memory computing package 100 (FIG. 20), in-memory computing package 100 is bonded to interposer 68. Interposer 68 includes a substrate 70, which may be a semiconductor substrate such as a silicon substrate, and vias 72 that penetrate substrate 70. The RDLs are formed on opposite sides of the substrate 70 and are interconnected by vias 72.
Fig. 23 illustrates a package 102' according to some embodiments of the invention. The enclosure 102' is similar to the embodiment shown in FIG. 22, except that two in-memory computing enclosures 100 are shown.
Fig. 24 illustrates a package 102' in which the in-memory computing package 100 is bonded to the package substrate 58 by flip-chip bonding, according to some embodiments of the invention. Underfill 48 is disposed in the gap between the computing package 100 and the package substrate 58 within the memory. The sealant 50 is sealed in the in-memory computing package 100.
Fig. 25-31 illustrate cross-sectional views of intermediate stages of formation of the in-memory computing package 100 as shown in fig. 5, according to some embodiments of the invention. The corresponding process is also schematically reflected in the process flow shown in fig. 45.
Referring to fig. 25, a layer-1 die, such as logic dies L1 and L2 and memory die M1, is placed on carrier 74, for example, by a die attach film (not shown). The corresponding process is shown as process 202 in the process flow shown in fig. 45. The front side of the layer-1 die is facing up. The metal pads 24A in the layer-1 die are covered by respective dielectric layers 26A. According to some embodiments of the present invention, dielectric layer 26A is formed of an oxide such as silicon oxide, silicon oxynitride, silicon carbonitride, or the like. The gaps between layer-1 die L1, L2, and M1 are then filled with dielectric film 38A using a further surface planarization process. The dielectric film may be formed of an oxide (such as silicon oxide), SiCN, SiN, SiOC, or the like. The corresponding process is shown as process 203 in the process flow shown in fig. 45.
Next, as shown in fig. 26, the layer-2 die, such as logic die L3 and memory dies M2 and M3, are bonded to layer-1 die L1, L2 and M1 by direct dielectric bonding, with dielectric layer 26B bonded to respective dielectric layer 26A by fusion bonding. The corresponding process is shown as process 204 in the process flow shown in fig. 45. Some dies, such as die M3, may be bonded to more than one die (such as die M1 and L2). According to some embodiments, there is no direct electrical connection between die M3 and die M1. However, since the die M3 is bonded on the die L2 and M1, the bonding stability is improved. After bonding, the layer-2 die may be thinned.
Next, as shown in fig. 27, a gap filling process is performed, and a dielectric region 38B is formed to fill the gap as shown in fig. 26. The corresponding process is shown as process 206 in the process flow shown in fig. 45. The gap fill may be performed using suitable methods including, but not limited to, Chemical Vapor Deposition (CVD), spin coating, Flowable Chemical Vapor Deposition (FCVD), and the like. The dielectric region 38B may be formed of an oxide (such as silicon oxide), SiCN, SiN, SiOC, or the like. A planarization process such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process may be performed to make the top surface of the dielectric region 38B flush. According to an alternative embodiment, the layer-1 die and the layer-2 die are encapsulated in the same encapsulation process, wherein dielectric regions 38A and 38B form a continuous dielectric region, referred to as dielectric region 38.
Fig. 28 further illustrates the formation of vias 30 (including 30-1, 30-2, and 30-3) that penetrate through dielectric region 38 and a substrate in the layer-2 die (such as a silicon substrate or other type of semiconductor substrate) to electrically couple to metal pads 24A. The corresponding process is shown as process 208 in the process flow shown in fig. 45. Thus, the layer-1 die is electrically coupled to the layer-2 die. The electrical coupling of metal pad 24B to corresponding metal pad 24A may be through a single via 30-3, or through two vias 30-1 and 30-2. Vias 32 are also formed through dielectric region 38 and connect to metal pads 24A. Metal pads 76 are formed on the top surface of dielectric region 38 and are electrically connected to the layer-1 die and the layer-2 die. The corresponding process is shown as process 210 in the process flow shown in fig. 45.
Fig. 29 illustrates the deposition and planarization of a dielectric layer 78, which dielectric layer 78 may be formed of an oxide such as silicon oxide, SiOC, SiCN, SiN, etc. The corresponding process is shown as process 212 in the process flow shown in fig. 45. Thus, metal pad 76 is covered by dielectric layer 78. Next, as shown in FIG. 30, layer-3 dies, such as logic die L4 and memory die M4, are bonded to dielectric layer 78. The corresponding process is shown as process 214 in the process flow shown in fig. 45. The surface dielectric layer 26C of the layer-3 die is bonded to the dielectric layer 78 by direct dielectric bonding. Then, for example, in a CMP process or a mechanical grinding process, layer-3 die L4 and M4 are thinned. A dielectric layer 79 is then deposited to encapsulate the layer-3 die, followed by a planarization process. A via 81 is formed to penetrate the substrate in the level-3 die and the top of the dielectric layer 79. Then, a metal pad 80 is formed on the surface of the dielectric layer 79, and the metal pad 80 is connected to the via hole 81. The corresponding process is shown as process 216 in the process flow shown in fig. 45. A dielectric layer 82 is then deposited and planarized. The corresponding process is shown as process 218 in the process flow shown in fig. 45. After planarization, the metal pad 80 may be exposed, or remain covered by the dielectric 82.
Fig. 31 illustrates the formation of RDL40, dielectric layer 41, and solder region 42. The corresponding process is shown as process 220 in the process flow shown in fig. 45. The RDL40 and solder regions 42 are electrically connected to the underlying layer-1, layer-2 and layer-3 die. The resulting structure is also shown in fig. 5. The carrier 74 (fig. 30) is then debonded and a singulation process is performed to form a plurality of packages 100 identical to one another. The structure shown in fig. 6 may be formed in a similar process, except that metal posts 44 and dielectric layer 46 are formed.
Fig. 32-39 illustrate cross-sectional views of intermediate stages in the formation of the in-memory computing package 100 as shown in fig. 7, according to some embodiments of the invention. Unless otherwise noted, the materials and formation processes of the components in fig. 32-39 (and 40-44) are substantially the same as the same components, and are identified by the same reference numerals in the embodiment shown in fig. 25-31. Accordingly, details regarding the formation processes and materials of the components shown in fig. 32-44 may be found in the discussion of the embodiments shown in fig. 25-31.
Referring to fig. 32, a layer-1 die, such as logic dies L1 and L2 and memory die M1, is placed on carrier 74, for example, by a die attach film (not shown). The front side of the layer-1 die is facing up. The gaps between layer-1 die L1, L2, and M1 are then filled with dielectric film 38A using a further surface planarization process. The dielectric film may be formed of an oxide (such as silicon oxide), SiCN, SiN, SiOC, or the like. The metal pads 24A in the layer-1 die are exposed and coplanar with the corresponding surface dielectric layer 26A.
Next, as shown in fig. 33, the layer-2 die, such as logic die L3 and memory dies M2 and M3, are bonded to layer-1 die L1, M1 and L2 by hybrid bonding, while dielectric layer 26B in the layer-2 die is bonded to dielectric layer 26A in the layer-1 die, and metal pad 24B is bonded to metal pad 24A. The layer-2 die may then be thinned. Next, as shown in fig. 34, a gap filling process is performed, and a dielectric region 38B is formed to fill the gap shown in fig. 33. A planarization process such as a CMP process or a mechanical polishing process may be performed to make the top surface of the dielectric region 38B flush. According to an alternative embodiment, the layer-1 die and the layer-2 die are encapsulated in the same encapsulation process, wherein dielectric regions 38A and 38B form a continuous dielectric region, referred to as dielectric region 38.
Fig. 35 illustrates the formation of vias 30 and 32. Some of vias 30 are electrically connected to bond pad 24B, and bond pad 24B is further connected to bond pad 24A. Some of the vias 30 are directly connected to the pads 24A. The via 32 is also formed to penetrate the dielectric region 38 and is connected to the metal pad 24A. Metal pads 76 are formed on top of dielectric region 38 and are electrically connected to the layer-1 die and the layer-2 die.
Fig. 35 also illustrates the deposition and planarization of dielectric layer 78. Metal pad 76 is exposed by the planarization and has a top surface that is coplanar with the top surface of dielectric layer 78. Next, as shown in fig. 36, layer-3 dies, such as logic die L4 and memory die M4, are bonded to dielectric layer 78 and metal pads 76 by hybrid bonding. Then, for example, in a CMP process or a mechanical grinding process, layer-3 die L4 and M4 are thinned.
Referring to fig. 37, a dielectric layer 82 is deposited and planarized. Then, via holes 81 and metal pads 80 are formed as shown in fig. 38. A dielectric layer 82 is then formed and planarized. In the resulting structure, the metal pad 80 may be exposed after planarization or remain covered by the dielectric 82.
Fig. 39 illustrates the formation of RDL40, dielectric layer 41, and solder region 42. The RDL40 and solder regions 42 are electrically connected to the underlying layer-1, layer-2 and layer-3 die. The resulting structure is also shown in fig. 7. The carrier 74 (fig. 38) is then debonded and a singulation process is performed to form a plurality of packages 100 identical to one another. The structure shown in fig. 8 may be formed in a similar process, except that metal posts 44 and dielectric layer 46 are formed.
Fig. 40-44 illustrate cross-sectional views of intermediate stages in the formation of an in-memory computing package 100 as shown in fig. 9, according to some embodiments of the invention. According to some embodiments, the layer-1 die is die L4 and M4, and the layer-1 die may also be die L1, M1, and L2, according to alternative embodiments.
Referring to fig. 40, a layer-1 die, such as logic die L4 and memory die M4, is placed on carrier 74, for example, by a die attach film (not shown). The front side of the layer-1 die is facing down. The metal pads 25 are formed on the back surfaces of the respective semiconductor substrates 20, and the vias 81 interconnect the metal pads 25 and 24C. In order to avoid diffusion of Cu into the silicon substrate, a dielectric insulating film (not shown) is deposited between the metal pad 25 and the silicon substrate, and filled so as to surround the through-hole 81. Next, as shown in fig. 41, a dielectric region 38A is formed to encapsulate the layer-1 die therein, and then planarized. The dielectric region 38A may be formed of an oxide such as silicon oxide or SiON.
Next, as shown in fig. 42, layer-2 dies, such as logic die L3 and memory dies M2 and M3, are bonded to dielectric region 38A by direct dielectric bonding, with dielectric layer 26B in layer-2 die bonded to dielectric region 38A. The layer-2 die may then be thinned, followed by the formation of vias 33. Next, as shown in fig. 42, a gap filling process is performed, and a dielectric region 38B is formed to fill the gaps between layer-2 die L3, M2, and M3, wherein a portion of dielectric region 38B overlaps layer-2 die L3, M2, and M3. A planarization process such as a CMP process or a mechanical polishing process may be performed to make the top surface of the dielectric region 38B flush.
Fig. 42 also illustrates the formation of metal pad 76 on the top surface of dielectric region 38B, and the deposition and planarization of dielectric layer 78. The metal pad 76 is covered by a dielectric layer 78.
Next, as shown in fig. 43, layer-3 dies, such as logic dies L1 and L2 and memory die M1, are bonded to dielectric layer 78 by direct dielectric bonding. The layer-3 die is then thinned, for example, in a CMP process or a mechanical grinding process. A dielectric layer 79 is then deposited and planarized.
With further reference to fig. 43, vias 30 are formed and metal pads 80 are formed to connect to vias 30. A metal pad 80 is formed on the dielectric layer 79 and contacts the via 30. A dielectric layer 82 is then formed and planarized. In the resulting structure, the metal pads 80 may be exposed after planarization or remain covered by the dielectric 82.
Fig. 44 illustrates the formation of RDL40, dielectric layer 41, and solder region 42. The RDL40 and solder regions 42 are electrically connected to the underlying layer-1, layer-2 and layer-3 die. The resulting structure is also shown in fig. 9. The carrier 74 (fig. 43) is then debonded and a singulation process is performed to form a plurality of packages 100 identical to one another. The structure shown in fig. 10 may be formed in a similar process, except that metal posts 44 and dielectric layer 46 are formed.
The process flow for forming the structures shown in fig. 11 and 12 may be implemented by processes as shown in fig. 25-44 and are not shown here.
In the embodiments illustrated above, some processes and components are discussed in accordance with some embodiments of the present invention. Other components and processes may also be included. For example, a test structure may be included to facilitate verification testing of a 3D package or a 3DIC device. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate, thereby allowing testing of a 3D package or 3DIC, use of probes and/or probe cards, and the like. The verification test may be performed on the intermediate structure as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.
Embodiments of the present invention have some advantageous features. By immersing the logic die in the memory die and the logic die in the memory die, computational efficiency may be improved, bandwidth of the system may be increased, and latency may be reduced due to the close proximity and efficient layout of the dies.
According to some embodiments of the invention, a method of forming an integrated circuit package includes placing a first plurality of dies over a carrier, wherein the first plurality of dies includes at least a first logic die and a first memory die; placing a second plurality of dies over the first plurality of dies, wherein the second plurality of dies is electrically coupled to the first plurality of dies, and wherein the second plurality of dies includes at least a second logic die and a second memory die; placing a third plurality of dies over the second plurality of dies, wherein the third plurality of dies is electrically coupled to the first plurality of dies and the second plurality of dies, and wherein the third plurality of dies includes at least a third logic die and a third memory die; and forming electrical connections over the first, second, and third pluralities of dies that are electrically connected to the first, second, and third pluralities of dies. In an embodiment, the method further comprises bonding the second plurality of dies to the first plurality of dies by direct dielectric bonding. In an embodiment, the method further includes bonding the second plurality of dies to the first plurality of dies by hybrid bonding. In an embodiment, the method further includes filling the first dielectric material, wherein the first dielectric material extends continuously into gaps between the first plurality of dies and into gaps between the second plurality of dies, wherein the first dielectric material has a portion that covers the second plurality of dies; forming a metal pad over the first dielectric material; forming a second dielectric material to cover the metal pad; the third plurality of dies is bonded to the second dielectric material by dielectric-to-dielectric bonding. In an embodiment, a die of the second plurality of dies is physically bonded to a first die and a second die of the first plurality of dies. In an embodiment, the method further includes forming a via physically connecting one of the second plurality of dies to a first die of the first plurality of dies, and without a direct electrical connection between the die of the second plurality of dies and a second die of the first plurality of dies. In an embodiment, forming the electrical connection includes forming a solder region. In an embodiment, forming the electrical connection comprises: forming a dielectric layer over the third plurality of dies; and forming a metal pillar in the dielectric layer, a top surface of the metal pillar being coplanar with a top surface of the dielectric layer. In an embodiment, the method further comprises performing sawing to form a plurality of packages, wherein the first plurality of dies, the second plurality of dies, and the third plurality of dies are located in one of the plurality of packages. In an embodiment, the method further comprises bonding one of the plurality of packages to the package assembly by flip-chip bonding; and sealing one of the plurality of packages in the sealant. In an embodiment, the method further comprises sealing one of the plurality of packages in a sealant; and forming a redistribution line and a dielectric layer overlapping the sealant and one of the plurality of packages.
According to some embodiments of the invention, a method of forming an integrated circuit package includes placing a first tier die; bonding a second tier die to the first tier die; filling a first gap filling dielectric material, wherein the first gap filling dielectric material is filled into the gaps between the first layer of dies and the gaps between the second layer of dies; forming a first via through the second tier die, wherein the first via electrically couples the second tier die to the first tier die; forming a metal pad electrically coupled to the first via over the first gap-filling dielectric material; forming a dielectric layer covering the metal pad; bonding a third tier die to the dielectric layer, wherein each tier of the first tier die, the second tier die, and the third tier die includes at least a logic die and a memory die; and forming a second via through the third level die to electrically couple to the metal pad. In an embodiment, the first via includes a first via terminating in one of the second tier dies and a second via terminating in one of the first tier dies. In an embodiment, the second tier die is bonded to the first tier die by hybrid bonding. In an embodiment, one of the first vias penetrates through a metal pad in the second tier die to be positioned on a metal pad in one of the first tier dies.
According to some embodiments of the invention, an integrated circuit package includes a first plurality of dies positioned over a carrier, wherein the first plurality of dies includes at least a first logic die and a first memory die; a second plurality of dies located above the first plurality of dies, wherein the second plurality of dies is electrically coupled to the first plurality of dies, and wherein the second plurality of dies includes at least a second logic die and a second memory die; a first dielectric layer over the second plurality of dies; a first via penetrating the first dielectric layer and the second plurality of dies to electrically couple to the first plurality of dies; a first metal pad over and contacting the first via; a second dielectric layer covering the first metal pad; a third plurality of dies over and bonded to the second dielectric layer; a second via penetrating the second dielectric layer and the third plurality of dies to electrically couple to the first metal pad. In an embodiment, the integrated circuit package further includes a second metal pad located over and physically connected to the second via. In an embodiment, the surface dielectric layer of the second plurality of dies is bonded to the surface dielectric layer of the first plurality of dies by direct dielectric bonding, wherein the second plurality of dies is electrically coupled to the first plurality of dies by the first vias. In an embodiment, the first via includes a via that physically contacts a metal pad in one of the second plurality of dies and a metal pad in one of the first plurality of dies. In an embodiment, the surface dielectric layers of the second plurality of dies are bonded to the surface dielectric layers of the first plurality of dies, and the bond pads of the second plurality of dies are bonded to the bond pads of the first plurality of dies.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

1. A method of forming an integrated circuit package, the method comprising:
placing a first plurality of dies over a carrier, wherein the first plurality of dies includes at least a first logic die and a first memory die;
placing a second plurality of dies over the first plurality of dies, wherein the second plurality of dies is electrically coupled to the first plurality of dies, and wherein the second plurality of dies includes at least a second logic die and a second memory die;
after placing the second plurality of dies, forming a via extending into one of the second plurality of dies, wherein the via is located on a metal pad in one of the second plurality of dies;
placing a third plurality of dies over the second plurality of dies, wherein the third plurality of dies is electrically coupled to the first plurality of dies and the second plurality of dies, and wherein the third plurality of dies includes at least a third logic die and a third memory die; and
forming electrical connections over the first, second, and third plurality of dies that are electrically coupled to the first, second, and third plurality of dies.
2. The method of claim 1, further comprising bonding the second plurality of dies to the first plurality of dies by direct dielectric bonding.
3. The method of claim 1, further comprising bonding the second plurality of dies to the first plurality of dies by hybrid bonding.
4. The method of claim 1, further comprising:
filling a first dielectric material, wherein the first dielectric material extends continuously into gaps between the first plurality of dies and gaps between the second plurality of dies, wherein the first dielectric material has a portion that covers the second plurality of dies;
forming a metal pad over the first dielectric material;
forming a second dielectric material to cover the metal pad; and
bonding the third plurality of dies to the second dielectric material by dielectric-to-dielectric bonding.
5. The method of claim 1, wherein one of the second plurality of dies is physically bonded to a first die and a second die of the first plurality of dies.
6. The method of claim 5, further comprising forming a via physically connecting one of the second plurality of dies to a first die of the first plurality of dies, and without a direct electrical connection between the one of the second plurality of dies and a second die of the first plurality of dies.
7. The method of claim 1, wherein forming the electrical connection comprises forming a solder region.
8. The method of claim 1, wherein forming the electrical connection comprises:
forming a dielectric layer over the third plurality of dies; and
forming a metal pillar in the dielectric layer, a top surface of the metal pillar being coplanar with a top surface of the dielectric layer.
9. The method of claim 1, further comprising:
sawing is performed to form a plurality of packages, wherein the first, second, and third plurality of dies are in one of the plurality of packages.
10. The method of claim 9, further comprising:
bonding one of the plurality of packages to a package assembly by flip-chip bonding; and
one of the plurality of packages is encapsulated in an encapsulant.
11. The method of claim 9, further comprising:
sealing one of the plurality of packages in an encapsulant; and
forming a redistribution line and a dielectric layer overlapping one of the plurality of packages and the encapsulant.
12. A method of forming an integrated circuit package, the method comprising:
placing a first layer of dies;
bonding a second tier die to the first tier die;
filling a first gap filling dielectric material, wherein the first gap filling dielectric material is filled into gaps between the first layer of dies and gaps between the second layer of dies;
forming a first via through the second tier die, wherein the first via electrically couples the second tier die to the first tier die;
forming a metal pad electrically coupled to the first via over the first gap-filling dielectric material;
forming a dielectric layer covering the metal pad;
bonding a third tier die to the dielectric layer, wherein each tier of the first tier die, the second tier die, and the third tier die includes at least a logic die and a memory die; and
forming a second via through the third level die to electrically couple to the metal pad.
13. The method of claim 12, wherein the first via comprises a first via terminating in one of the second tier dies and a second via terminating in one of the first tier dies.
14. The method of claim 12, wherein the second tier die is bonded to the first tier die by hybrid bonding.
15. The method of claim 12, wherein one of the first vias passes through a metal pad in the second tier die to be positioned on a metal pad on one of the first tier die.
16. An integrated circuit package, comprising:
a first plurality of dies located over a carrier, wherein the first plurality of dies includes at least a first logic die and a first memory die;
a second plurality of dies located above the first plurality of dies, wherein the second plurality of dies is electrically coupled to the first plurality of dies, and wherein the second plurality of dies includes at least a second logic die and a second memory die;
a first dielectric layer over the second plurality of dies;
a first via penetrating the first dielectric layer and the second plurality of dies to electrically couple to the first plurality of dies;
a first metal pad over and contacting the first via;
a second dielectric layer covering the first metal pad;
a third plurality of dies over and bonded to the second dielectric layer; and
a second via penetrating the second dielectric layer and the third plurality of dies to electrically couple to the first metal pad.
17. The integrated circuit package of claim 16, further comprising a second metal pad located over and physically connected to the second via.
18. The integrated circuit package of claim 16, wherein the surface dielectric layers of the second plurality of dies are bonded to the surface dielectric layers of the first plurality of dies by direct dielectric bonding, wherein the second plurality of dies are electrically coupled to the first plurality of dies through the first vias.
19. The integrated circuit package of claim 18, wherein the first via comprises a via that physically contacts a metal pad in one of the second plurality of dies and a metal pad in one of the first plurality of dies.
20. The integrated circuit package of claim 16, wherein the surface dielectric layers of the second plurality of dies are bonded to the surface dielectric layers of the first plurality of dies, and the bond pads of the second plurality of dies are bonded to the bond pads of the first plurality of dies.
CN201910955789.9A 2018-10-10 2019-10-09 Integrated circuit package and method of forming the same Active CN111029303B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862743693P 2018-10-10 2018-10-10
US62/743,693 2018-10-10
US16/529,235 US11171076B2 (en) 2018-10-10 2019-08-01 Compute-in-memory packages and methods forming the same
US16/529,235 2019-08-01

Publications (2)

Publication Number Publication Date
CN111029303A CN111029303A (en) 2020-04-17
CN111029303B true CN111029303B (en) 2021-12-28

Family

ID=69954524

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910955789.9A Active CN111029303B (en) 2018-10-10 2019-10-09 Integrated circuit package and method of forming the same

Country Status (2)

Country Link
CN (1) CN111029303B (en)
DE (1) DE102019121087A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220108158A1 (en) * 2020-10-02 2022-04-07 Sandisk Technologies Llc Ultralow power inference engine with external magnetic field programming assistance

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101542701A (en) * 2008-06-05 2009-09-23 香港应用科技研究院有限公司 Bonding method of three dimensional wafer lamination based on silicon through holes
CN102169845A (en) * 2011-02-22 2011-08-31 中国科学院微电子研究所 Multi-layer mixed synchronization bonding structure and method for three-dimensional packaging
CN106449609A (en) * 2015-07-30 2017-02-22 联发科技股份有限公司 Semiconductor package structure and method for forming the same
CN110235253A (en) * 2017-02-09 2019-09-13 索尼半导体解决方案公司 The manufacturing method of semiconductor devices and semiconductor devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102007259B1 (en) * 2012-09-27 2019-08-06 삼성전자주식회사 Semiconductor package and method for manufacturing the same
US9184128B2 (en) * 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
US9620488B2 (en) * 2015-08-19 2017-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional integrated circuit structure and bonded structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101542701A (en) * 2008-06-05 2009-09-23 香港应用科技研究院有限公司 Bonding method of three dimensional wafer lamination based on silicon through holes
CN102169845A (en) * 2011-02-22 2011-08-31 中国科学院微电子研究所 Multi-layer mixed synchronization bonding structure and method for three-dimensional packaging
CN106449609A (en) * 2015-07-30 2017-02-22 联发科技股份有限公司 Semiconductor package structure and method for forming the same
CN110235253A (en) * 2017-02-09 2019-09-13 索尼半导体解决方案公司 The manufacturing method of semiconductor devices and semiconductor devices

Also Published As

Publication number Publication date
CN111029303A (en) 2020-04-17
DE102019121087A1 (en) 2020-04-16

Similar Documents

Publication Publication Date Title
KR102308487B1 (en) Compute-in-memory packages and methods forming the same
US20210028147A1 (en) Multi-Die Package Structures Including Redistribution Layers
KR102033865B1 (en) Independent 3D Stacking
CN102931173B (en) Multi-chip wafer level package
KR102318303B1 (en) Die stacks and methods forming same
TWI763198B (en) Method for manufactoring semiconductor package and semiconductor package
KR20210065353A (en) Semiconductor package
US11462495B2 (en) Chiplets 3D SoIC system integration and fabrication methods
US20220310570A1 (en) Vertical semiconductor package including horizontally stacked dies and methods of forming the same
KR102331814B1 (en) Ipd modules with flexible connection scheme in packaging
US20240088077A1 (en) Chiplets 3d soic system integration and fabrication methods
US11715696B2 (en) Semiconductor devices with recessed pads for die stack interconnections
US20240021576A1 (en) Through-dielectric vias for direct connection and method forming same
CN111029303B (en) Integrated circuit package and method of forming the same
TW202245161A (en) Info packages including thermal dissipation blocks and fabrication method thereof
US20230343764A1 (en) Package structure
US20230361048A1 (en) Semiconductor package and method of fabricating semiconductor package
KR100851108B1 (en) Wafer level system in package and fabrication method thereof
TW202101728A (en) Semiconductor structure and method manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant