CN111028758B

CN111028758B - Display panel, driving method thereof and display device

Info

Publication number: CN111028758B
Application number: CN201911364722.4A
Authority: CN
Inventors: 解红军
Original assignee: Yungu Guan Technology Co Ltd
Current assignee: Yungu Guan Technology Co Ltd
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2023-02-28
Anticipated expiration: 2039-12-26
Also published as: CN111028758A

Abstract

The embodiment of the invention discloses a display panel, a driving method thereof and a display device, wherein the display panel comprises: the pixel circuit comprises a plurality of pixel circuits, a plurality of data lines, a plurality of detection lines and control circuits which correspond to the data lines and the detection lines one by one; the pixel circuit comprises a driving transistor, a detecting transistor and a data writing transistor, wherein the data writing transistor is used for writing data voltage into the grid electrode of the driving transistor, and the detecting transistor is electrically connected with the source electrode of the driving transistor; the control circuit is used for controlling the communication between the detection lines and the initialization terminals and the communication between the data lines and the corresponding data terminals in the display mode; the control circuit is also used for controlling the communication between the detection lines and the corresponding detection terminals and controlling the communication between the data lines and the initialization terminals in a detection mode; at least part of the data terminals are multiplexed as detection terminals. According to the technical scheme, the pixel density is improved while the display uniformity is improved; and is advantageous for reducing the number of data terminals and sense terminals.

Description

Display panel, driving method thereof and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.

Background

With the development of display technology, the requirements on display quality are higher and higher.

In the conventional display panel, in order to achieve a higher pixel density, a pixel circuit with a smaller number of transistors is generally used.

However, in a pixel circuit having a small number of transistors, a problem of poor display uniformity tends to occur.

Disclosure of Invention

The invention provides a display panel, a driving method thereof and a display device, aiming at improving the display uniformity on the premise of ensuring higher pixel density.

In a first aspect, an embodiment of the present invention provides a display panel, including: the pixel circuit comprises a plurality of pixel circuits, a plurality of data lines, a plurality of detection lines and control circuits which correspond to the data lines and the detection lines one to one;

the pixel circuit comprises a driving transistor, a detection transistor and a data writing transistor, wherein the data writing transistor is used for writing data voltage into the grid electrode of the driving transistor, the detection transistor is electrically connected with the source electrode of the driving transistor, the data writing transistor is electrically connected with a corresponding data line, and the detection transistor is electrically connected with a corresponding detection line;

the control circuit is used for controlling the detection line to be communicated with the initialization terminal and controlling the data line to be communicated with the corresponding data terminal in the display mode;

the control circuit is also used for controlling the communication between the detection lines and the corresponding detection terminals and controlling the communication between the data lines and the initialization terminals in a detection mode;

at least part of the data terminals are multiplexed as detection terminals.

Optionally, the control circuit includes a first control unit and a second control unit;

the first control unit comprises a first control end, a second control end, a first end, a second end and a third end, wherein the first end is electrically connected with the detection terminal, the second end is electrically connected with the initialization terminal, and the third end is electrically connected with the detection line; the first control unit is used for controlling the communication between the second end and the third end according to a signal input by the second control end in a display mode and controlling the communication between the first end and the third end according to a signal input by the first control end in a detection mode;

the second control unit comprises a third control end, a fourth end, a fifth end and a sixth end, the fourth end is electrically connected with the data terminal, the fifth end is electrically connected with the initialization terminal, and the sixth end is electrically connected with the data line; the second control unit is used for controlling the communication between the fourth end and the sixth end according to a signal input by the third control end in the display mode and controlling the communication between the fifth end and the sixth end according to a signal input by the fourth control end in the detection mode.

Optionally, the first control unit includes a first switch and a second switch; the control end of the first switch is used as the first control end of the first control unit, the first end of the first switch is used as the first end of the first control unit, and the second end of the first switch is electrically connected with the third end of the first control unit; the control end of the second switch is used as the second control end of the first control unit, the first end of the second switch is used as the second end of the first control unit, and the second end of the second switch is electrically connected with the third end of the first control unit.

Optionally, the second control unit includes a third switch and a fourth switch; a control end of the third switch is used as a third control end of the second control unit, a first end of the third switch is used as a fourth end of the second control unit, and a second end of the third switch is electrically connected with a sixth end of the second control unit; the control end of the third switch is used as the fourth control end of the second control unit, the first end of the fourth switch is used as the fifth end of the second control unit, and the second end of the fourth switch is electrically connected with the sixth end of the second control unit.

Optionally, each detection terminal is connected to the first ends of at least two first control units, and each data terminal is connected to the fourth ends of at least two second control units; the first control end of the first control unit electrically connected with the same detection terminal is connected with different control signal lines, and the third control end of the second control unit electrically connected with the same data terminal is connected with different control signal lines.

Optionally, the display panel at least includes a first pixel circuit, a second pixel circuit, and a third pixel circuit corresponding to the sub-pixels with different light emitting colors;

one first data line and one first detection line of each column of the first pixel circuits; each column of the second pixel circuits is connected with a second data line and a second detection line; each column of the third pixel circuits is connected with a third data line and a third detection line;

each detection terminal is electrically connected with at least two of the three first control units corresponding to the first detection line, the second detection line and the third detection line;

each data terminal is electrically connected with at least two of the three second control units corresponding to the first data line, the second data line and the third data line;

the first control end of the first control unit electrically connected with the first detection line is connected with the first control signal line, the first control end of the first control unit electrically connected with the second detection line is connected with the second control signal line, and the first control end of the first control unit electrically connected with the third detection line is connected with the third control signal line.

Optionally, the driving transistor is an N-type transistor.

In a second aspect, an embodiment of the present invention further provides a driving method for a display panel, where the display panel includes a plurality of pixel circuits, a plurality of data lines, a plurality of sense lines, and control circuits corresponding to the data lines and the sense lines one to one; multiplexing at least part of the data terminals as detection terminals; the driving method comprises the following steps:

in the display mode, the detection lines are controlled to be communicated with the initialization terminals through the control circuit, and the data lines are controlled to be communicated with the corresponding data terminals through the control circuit;

in the detection mode, the detection lines are controlled to be communicated with the corresponding detection terminals through the control circuit, and the data lines are controlled to be communicated with the initialization terminals through the control circuit.

Optionally, the control circuit includes a first control unit and a second control unit; the first control unit comprises a first control end, a second control end, a first end, a second end and a third end, wherein the first end is electrically connected with the detection terminal, the second end is electrically connected with the initialization terminal, and the third end is electrically connected with the detection line; the second control unit comprises a third control end, a fourth end, a fifth end and a sixth end, wherein the fourth end is electrically connected with the data terminal, the fifth end is electrically connected with the initialization terminal, and the sixth end is electrically connected with the data line;

the pixel circuit at least comprises a first pixel circuit, a second pixel circuit and a third pixel circuit which correspond to the sub-pixels with different light-emitting colors;

one first data line and one first detection line of each column of first pixel circuits; each column of the second pixel circuits is connected with a second data line and a second detection line; each column of the third pixel circuits is connected with a third data line and a third detection line;

the first control end of the first control unit electrically connected with the first detection line is connected with a first control signal line, the first control end of the first control unit electrically connected with the second detection line is connected with a second control signal line, and the first control end of the first control unit electrically connected with the third detection line is connected with a third control signal line;

under the mode of listening, through control circuit control detection line and the corresponding terminal intercommunication of listening, include:

in the detection mode, when each row of pixel circuits in the display panel is scanned, the conduction control signals are sequentially input to the first control signal line, the second control signal line and the third control signal line.

in the detection mode, scanning the whole display panel at least three times;

when the display panel is scanned for the first time, inputting a conduction control signal to the first control signal line when each row of pixel circuits in the display panel is scanned;

when the display panel is scanned for the second time, inputting a conduction control signal to the second control signal line when each row of pixel circuits in the display panel is scanned;

when the display panel is scanned for the third time, the conducting control signal is input to the third control signal line when each row of pixel circuits in the display panel is scanned.

In a third aspect, an embodiment of the present invention further provides a display device, including the display panel provided in the first aspect; the driver chip further comprises a driver chip and an initialization power supply, wherein the initialization power supply comprises an initialization terminal, and the driver chip comprises a data terminal and a detection terminal.

The embodiment of the invention provides a display panel, a driving method thereof and a display device, wherein a detection line is controlled to be communicated with an initialization terminal and a data line is controlled to be communicated with a corresponding data terminal by a control circuit in a display mode, so that the source electrode potential of a driving transistor is kept unchanged when data writing is carried out in the display mode, the influence on driving current caused by unfixed source electrode potential of the driving transistor in data writing is further avoided, and the display uniformity of the display panel is further favorably ensured; and the control circuit controls the detection lines to be communicated with the corresponding detection terminals and controls the data lines to be communicated with the initialization terminals in the detection mode, so that the threshold voltage of the driving transistor can be compensated through the outside by detecting the threshold voltage in the detection mode, the display uniformity is improved, and meanwhile, the quantity of transistors and capacitance elements contained in the pixel circuit is less, and the pixel density is improved. And, through multiplexing as listening the terminal at least part of data terminal, be favorable to reducing the data terminal and listen the quantity of terminal for data terminal and the area occupied of listening the terminal on display panel reduce, and then are favorable to the realization of narrow frame. And when the data terminal and the detection terminal are directly used as the output port of the driving chip, the miniaturization of the driving chip is further facilitated.

Drawings

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another display panel provided in the embodiment of the present invention;

FIG. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 6 is a timing diagram of a display panel according to an embodiment of the present invention;

FIG. 7 is a timing diagram illustrating a driving sequence of a display panel according to an embodiment of the present invention;

FIG. 8 is a timing diagram illustrating the driving of the display panel in the first detection phase of FIG. 7 according to an embodiment of the present invention;

FIG. 9 is a timing diagram illustrating a driving sequence of a display panel according to an embodiment of the present invention;

fig. 10 is a flowchart of a driving method of a display panel according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background, in the conventional display panel, in order to realize a higher pixel density, a pixel circuit having a smaller number of transistors is generally used. However, in a pixel circuit having a small number of transistors, a problem of poor display uniformity is likely to occur. The inventor has found that the above problem occurs because, in the conventional display panel, in order to achieve a higher pixel density, the pixel circuit is usually a 2T1C pixel circuit, and in the process of forming the thin film transistor, threshold voltages of different transistors are different due to process reasons, and the 2T1C pixel circuit is not provided with a threshold compensation transistor, so that the threshold voltage cannot be compensated through the inside of the pixel circuit, and when the same data voltage is written into the gate of the driving transistor, the driving currents generated are different in magnitude, and therefore, under the same gray scale, the light emitting luminances of different light emitting devices are different, so that the display uniformity is poor. The existing pixel circuit also comprises a 3T1C pixel circuit, namely, a transistor is added in the original 2T1C pixel circuit and is electrically connected with a source electrode of a driving transistor, so that the detection of the threshold voltage of the driving transistor is realized by detecting the source electrode potential through a driving chip, and the compensation of the threshold voltage of the driving transistor is realized through the outside. However, no matter the 2T1C pixel circuit or the 3T1C pixel circuit, when the display panel displays, the source potential of the driving transistor is uncertain, for example, when the driving transistor is an N-type transistor, the source of the driving transistor is connected to the power source end through the light emitting device, so that the source potential of the driving transistor is affected by the voltage drop of the power trace, and further when the gate of the driving transistor writes data voltage, the source potentials of the driving transistors in the pixel circuits at different positions may be inconsistent, resulting in a difference between the gate voltage and the source voltage of the driving transistor in the pixel circuits at different positions, further resulting in a difference between the driving currents of the light emitting devices in the pixel circuits at different positions at the same display gray scale, and a difference in display brightness, resulting in a poor uniformity of the display panel.

In addition, a plurality of terminals for transmitting display signals to the pixel circuits in the display area are arranged in the frame of the display panel, the number of the pixel circuits is increased along with the improvement of the resolution of the display panel, the number of the terminals in the frame area is increased gradually, and then the frame of the display panel is large, which is not beneficial to the realization of narrow frames.

For the above reasons, an embodiment of the present invention provides a display panel, and fig. 1 is a schematic structural diagram of the display panel provided in the embodiment of the present invention, and referring to fig. 1, the display panel includes: a plurality of pixel circuits 110, a plurality of data lines (DL 1, DL2, DL3, DL4 \8230;), a plurality of sensing lines (SL 1, SL2, SL3, SL4 \8230;), and control circuits 120 corresponding to the data lines and the sensing lines one to one;

the pixel circuit 110 includes a driving transistor T1, a detecting transistor T2 and a data writing transistor T3, the data writing transistor T3 is used for writing a data voltage to the gate g of the driving transistor T1, the detecting transistor T2 is electrically connected to the source s of the driving transistor T1, the data writing transistor T3 is electrically connected to a corresponding data line, and the detecting transistor T2 is electrically connected to a corresponding detecting line;

the control circuit 120 is used for controlling the detection lines to be communicated with the initialization terminal Vrefn and the data lines to be communicated with the corresponding data terminals in the display mode;

the control circuit 120 is further configured to control the detection lines to communicate with the corresponding detection terminals and control the data lines to communicate with the initialization terminal Vrefn in the detection mode;

at least part of the data terminals are multiplexed as detection terminals.

Referring to fig. 1, alternatively, the pixel circuits 110 are arranged in an array in the display panel, four circuits in one row of the pixel circuits 110 are shown as an example in fig. 1, and a specific structure of one of the pixel circuits 110 is shown, and each pixel circuit 110 includes the driving transistor T1, the detecting transistor T2, and the data writing transistor T3 shown in fig. 1.

The display panel includes a plurality of data terminals (D1, D2, D3, D4 \8230;) and a plurality of sensing terminals (S1, S2, S3, S4 \8230;). Each control circuit 120 corresponds to a data line and a detection line, each data line is connected to a column of pixel circuits 110, and each detection line is connected to a column of pixel circuits 110. Specifically, each control circuit 120 is connected to one data line and one sensing line; the control circuit 120 is further electrically connected to a data terminal, a detection terminal and an initialization terminal Vrefn, optionally, each data terminal is connected to at least one control circuit 120, and each detection terminal is connected to at least one control circuit 120, and fig. 1 shows a case where each control circuit 120 is connected to one data terminal and one detection terminal, where for a display device in which the driving chip 130 is directly disposed on the display panel, the data terminal and the detection terminal may be a data voltage output terminal and a detection signal terminal of the driving chip 130; for a display panel in which the driving chip 130 is not directly disposed on the display panel, for example, in a display device in which the driving chip 130 is integrated on a flexible PCB, the data terminal and the detecting terminal may be pads disposed on the display panel, and both the data terminal and the detecting terminal are electrically connected to the driving chip 130. Fig. 1 schematically illustrates a situation in which the driving chip 130 is disposed on the display panel, wherein the data terminal is configured to output a data voltage provided by the driving chip 130, the detection terminal may serve as a collecting terminal of an electric potential of a source s of the driving transistor T1 in the pixel circuit 110 by the driving chip 130, and the initialization terminal Vrefn is configured to output an initialization voltage, wherein the initialization voltage may be provided by the initialization power supply 140, and the initialization power supply 140 may be disposed on the display panel or other portions of the display device including the display panel, which is not specifically limited herein.

Optionally, the driving transistor T1 in each pixel circuit 110 is an N-type transistor as shown in fig. 1.

Specifically, the working process of the display panel may include a detection mode and a display mode. Referring to fig. 1, the gate g of the data writing transistor T3 in the pixel circuit 110 is electrically connected to the first Scan signal input terminal Scan1, and the gate g of the detecting transistor T2 is electrically connected to the second Scan signal input terminal Scan2, because the display panel is usually scanned line by line, the source s potential of the driving transistor T1 in the pixel circuit 110 can be detected line by line in the detection mode.

Specifically, in the detection mode, the control circuit 120 controls the initialization terminal Vrefn to be connected to the data line, and accordingly, the first Scan signal input terminal Scan1 can input an on control signal to turn on the data writing transistor T3 in the pixel circuit 110, so that the gate g of the driving transistor T1 is written into the initialization voltage output by the initialization terminal Vrefn, that is, the potential of the gate g of the driving transistor T1 is a fixed voltage which is the initialization voltage output by the initialization terminal Vrefn in the detection mode. In the detection mode, the control circuit 120 controls the conduction between the detection lines and the corresponding detection terminals, for example, for the display panel shown in fig. 1, each detection line corresponds to one detection terminal, and in the detection mode, the control circuit 120 respectively controls the conduction between the detection line SL1 and the detection terminal S1, the conduction between the detection line SL2 and the detection terminal S2, the conduction between the detection line SL3 and the detection terminal S3, and the conduction between the detection line SL4 and the detection terminal S4 \8230, and further causes each detection terminal to respectively transmit the collected source S potential of the driving transistor T1 to the driving chip 130. In the detection mode, the gate g of the driving transistor T1 is fixed in potential, so that the threshold voltage of the driving transistor T1 can be obtained by detecting the source s potential. When the gate g of the driving transistor T1 is the initialization voltage, the driving transistor T1 is turned on, the first power voltage input terminal gradually charges the source s of the driving transistor T1, and when the gate-source voltage difference of the driving transistor T1 is Vth, the potential of the source s does not change any more, for example, the potential of the source s is stabilized at Vsen, and the difference between the initialization voltage of the gate g of the driving transistor T1 and the potential Vsen of the source s is the threshold voltage of the driving transistor T1. By detecting the threshold voltage in the detection mode, the threshold voltage of the driving transistor T1 is compensated from the outside, so that the display uniformity is improved, and the number of transistors and capacitors included in the pixel circuit 110 is reduced, thereby improving the pixel density.

In the display mode, the detection line is controlled to be connected to the initialization terminal Vrefn, and meanwhile, the on control signal is input to the second Scan signal input terminal Scan2, so that the detection transistor T2 is turned on, and the initialization voltage transmitted by the detection line is written into the source s of the driving transistor T1 through the turned-on detection transistor T2, so that the potential of the source s of the driving transistor T1 is fixed. And in the display mode, the control circuit 120 controls the data lines to be connected to the corresponding data terminals, wherein each data terminal may correspond to at least one data line, and the display panel shown in fig. 1 shows that each data terminal corresponds to one data line, and in the display mode, the control circuit 120 controls the data lines DL1 and D1 to be connected, the data lines DL2 and D2 to be connected, the data lines DL3 and D3 to be connected, and the data lines DL4 and D4 to be connected \8230, and simultaneously inputs a conduction control signal to the first Scan signal input terminal Scan1 in the pixel circuit 110, so that the data voltage transmitted from the data terminals through the data lines is transmitted to the gate g of the driving transistor T1 through the data writing transistor T3. Therefore, when data is written, the source s potential of the driving transistor T1 remains unchanged, so that the influence of the unfixed source s potential of the driving transistor T1 on the driving current during data writing is avoided, and the display uniformity of the display panel is further ensured. Specifically, taking the pixel circuit 110 shown in fig. 1 as an example where each transistor is an N-type transistor, the first power voltage input terminal may be connected to a first power line, and the second power voltage input terminal may be connected to a second power line, because the second power voltage data terminal is electrically connected to the source s of the driving transistor T1 through the organic light emitting device, and the voltage drop of the organic light emitting device is usually constant, if the second power voltage input by the second power voltage input terminal is different, the potential of the source s of the driving transistor T1 is different. Because there is an unavoidable voltage drop on the power line, the second power voltages input by the second power voltage input terminals in the pixel circuits 110 at different positions are different, and the potentials of the sources s of the driving transistors T1 are different, so that the driving currents generated by the driving transistors T1 with the same data voltage written into the gates g are different, resulting in poor uniformity. In the display panel of the embodiment, when data is written, the control circuit 120 controls the detection line to be conducted with the initialization terminal Vrefn and controls the detection transistor T2 to be conducted, so that the potential of the source s of the driving transistor T1 is fixed to the initialization voltage, thereby avoiding the influence of the voltage drop on the power line on the display uniformity and improving the display effect.

In addition, in the display panel provided by the embodiment, at least part of the data terminals are multiplexed as the detection terminals. Specifically, in the detection mode, the control circuit 120 controls the initialization terminal Vrefn to be connected to the data line, so that the initialization voltage output by the initialization terminal Vrefn is transmitted to the data line, and thus the data terminal does not need to output the data voltage in the detection mode; in the display mode, the control circuit 120 controls the initialization terminal Vrefn to be communicated with the detection line, so that the initialization voltage output by the initialization terminal Vrefn is transmitted to the detection line, and therefore, in the display mode, the detection terminal does not need to collect the source S potential of the driving transistor T1, and therefore, the data terminal can be reused as the detection terminal, for example, the data terminal D1 in fig. 1 is reused as the detection terminal S1, and in the display mode, the control circuit 120 controls the data terminal D1 (the detection terminal S1) to be communicated with the data line, and the data terminal D1 outputs the data voltage; in the detection mode, the control circuit 120 controls the data terminal D1 (the detection terminal S1) to be connected to the detection line, so as to collect the source S potential of the driving transistor T1 of the pixel circuit 110. Through multiplexing the terminal for listening with partial data terminal, reduce data terminal and the quantity of listening the terminal for data terminal and the area occupied of listening the terminal on display panel reduce, all set up in the non-display area usually for data terminal and listening the terminal, and then are favorable to the realization of narrow frame. And when the data terminal and the detection terminal are directly used as the output ports of the driving chip 130, the number of the ports of the driving chip 130 can be reduced, thereby being beneficial to the miniaturization of the driving chip 130.

According to the display panel provided by the embodiment, the detection lines are controlled to be communicated with the initialization terminals and the data lines are controlled to be communicated with the corresponding data terminals through the control circuit in the display mode, so that the source electrode potential of the driving transistor is kept unchanged when data are written in the display mode, the influence on the driving current caused by unfixed source electrode potential of the driving transistor is further avoided when the data are written in the display mode, and the display uniformity of the display panel is further ensured; and the control circuit controls the detection lines to be communicated with the corresponding detection terminals and controls the data lines to be communicated with the initialization terminals in the detection mode, so that the threshold voltage of the driving transistor can be compensated through the outside by detecting the threshold voltage in the detection mode, the display uniformity is improved, and meanwhile, the quantity of transistors and capacitance elements contained in the pixel circuit is less, and the pixel density is improved. And, through multiplexing as listening the terminal at least part of data terminal, be favorable to reducing the data terminal and listen the quantity of terminal for data terminal and the area occupied of listening the terminal on display panel reduce, and then are favorable to the realization of narrow frame. And when the data terminal and the detection terminal are directly used as output ports of the driving chip, the miniaturization of the driving chip is further facilitated.

Fig. 2 is a schematic structural diagram of another display panel provided in an embodiment of the present invention, and referring to fig. 2, optionally, the control circuit 120 includes a first control unit 121 and a second control unit 122;

the first control unit 121 includes a first control terminal C1, a second control terminal C2, a first terminal A1, a second terminal A2, and a third terminal A3, where the first terminal A1 is electrically connected to the detection terminal, the second terminal A2 is electrically connected to the initialization terminal Vrefn, and the third terminal A3 is electrically connected to the detection line; the first control unit 121 is configured to control the second terminal A2 to communicate with the third terminal A3 according to a signal input from the second control terminal C2 in the display mode, and control the first terminal A1 to communicate with the third terminal A3 according to a signal input from the first control terminal C1 in the detection mode;

the second control unit 122 includes a third control end C3, a fourth control end C4, a fourth end A4, a fifth end A5 and a sixth end A6, the fourth end A4 is electrically connected to the data terminal, the fifth end A5 is electrically connected to the initialization terminal Vrefn, and the sixth end A6 is electrically connected to the data line; the second control unit 122 is used for controlling the communication between the fourth terminal A4 and the sixth terminal A6 according to the signal inputted from the third control terminal C3 in the display mode, and controlling the communication between the fifth terminal A5 and the sixth terminal A6 according to the signal inputted from the fourth control terminal C4 in the detection mode.

Specifically, in the display mode, a conduction control signal may be input to the second control terminal C2 of the first control unit 121, so that the first control unit 121 controls the second terminal A2 and the third terminal A3 to be connected according to the conduction control signal input by the second control terminal C2, thereby realizing the connection between the initialization terminal Vrefn and the detection line, and simultaneously controlling the detection transistor T2 to be connected, so that the initialization voltage output by the initialization terminal Vrefn is transmitted to the source s of the driving transistor T1. In addition, in the display mode, a turn-on control signal may be input to the third control terminal C3 of the second control unit 122, so that the fourth terminal A4 and the sixth terminal A6 of the second control unit 122 are communicated, and further, the data terminal is communicated with the data line, and meanwhile, the data writing transistor T3 is controlled to be turned on, so that the data voltage output by the data terminal is transmitted to the gate g of the driving transistor T1.

In the detection mode, a conduction control signal can be input to the first control terminal C1 of the first control unit 121, so that the first control unit 121 controls the first terminal A1 and the third terminal A3 to be communicated according to the conduction control signal input by the first control terminal C1, thereby realizing the communication between the detection terminal and the detection line, and simultaneously controlling the conduction of the detection transistor T2, thereby enabling the source s potential of the driving transistor T1 to be transmitted to the detection terminal through the detection transistor T2 and the detection line. In addition, in the detection mode, an on-control signal may be input to the fourth control terminal C4 of the second control unit 122, so that the fifth terminal A5 and the sixth terminal A6 of the second control unit 122 are communicated, and further, the communication between the initialization terminal Vrefn and the data line is realized, and meanwhile, the data writing transistor T3 is controlled to be turned on, so that the initialization voltage output by the initialization terminal Vrefn is transmitted to the gate g of the driving transistor T1, and the potential of the gate g of the driving transistor T1 is fixed in the detection mode.

Fig. 3 is a schematic structural diagram of another display panel provided in the embodiment of the present invention, and referring to fig. 3, optionally, the first control unit 121 includes a first switch 1211 and a second switch 1212; a control terminal of the first switch 1211 is used as a first control terminal C1 of the first control unit 121, a first terminal of the first switch 1211 is used as a first terminal A1 of the first control unit 121, and a second terminal of the first switch 1211 is electrically connected to a third terminal A3 of the first control unit 121; the control terminal of the second switch 1212 serves as the second control terminal C2 of the first control unit 121, the first terminal of the second switch 1212 serves as the second terminal A2 of the first control unit 121, and the second terminal of the second switch 1212 is electrically connected to the third terminal A3 of the first control unit 121.

Specifically, in the display mode, the second switch 1212 may be controlled to be turned on, so as to communicate the initialization terminal Vrefn with the detection line, and the detection transistor T2 is controlled to be turned on, so that the initialization voltage output by the initialization terminal Vrefn is transmitted to the source s of the driving transistor T1.

In the detection mode, the first switch 1211 is controlled to be turned on, so as to connect the detection terminal and the detection line, and the detection transistor T2 is controlled to be turned on, so that the source s potential of the driving transistor T1 can be transmitted to the detection terminal through the detection transistor T2 and the detection line.

Optionally, the first switch 1211 and the second switch 1212 may be thin film transistors, so that both the first switch 1211 and the second switch 1212 may be manufactured by the same process as the transistors in the pixel circuit 110, and the manufacturing process of the display panel is relatively simplified. Moreover, when the types of the thin film transistors included in the pixel circuits 110 in the display panel are the same, for example, when the thin film transistors in the pixel circuits 110 are all N-type transistors, the first switch 1211 and the second switch 1212 are also N-type transistors, thereby further simplifying the manufacturing process of the display panel.

With continued reference to fig. 3, optionally, the second control unit 122 includes a third switch 1221 and a fourth switch 1222; a control terminal of the third switch 1221 serves as a third control terminal C3 of the second control unit 122, a first terminal of the third switch 1221 serves as a fourth terminal A4 of the second control unit 122, and a second terminal of the third switch 1221 is electrically connected to a sixth terminal A6 of the second control unit 122; a control terminal of the third switch 1221 serves as a fourth control terminal C4 of the second control unit 122, a first terminal of the fourth switch 1222 is electrically connected to a fifth terminal A5 serving as the second control unit 122, and a second terminal of the fourth switch 1222 is electrically connected to a sixth terminal A6 of the second control unit 122.

Specifically, in the display mode, the third switch 1221 may be controlled to be turned on, so as to communicate the data terminal with the data line, and the data writing transistor T3 may be controlled to be turned on, so that the data voltage output from the data terminal is transmitted to the gate g of the driving transistor T1.

In the detection mode, the fourth switch 1222 can be controlled to be turned on, so as to connect the initialization terminal Vrefn to the data line, and at the same time, the data writing transistor T3 is controlled to be turned on, so that the initialization voltage output by the initialization terminal Vrefn is transmitted to the gate g of the driving transistor T1, and the potential of the gate g of the driving transistor T1 is fixed in the detection mode.

Optionally, the third switch 1221 and the fourth switch 1222 may be thin film transistors, so that both the third switch 1221 and the fourth switch 1222 may be fabricated by the same process as the transistors in the pixel circuit 110, and the fabrication process of the display panel is relatively simplified. Moreover, when the types of the thin film transistors included in the pixel circuits 110 in the display panel are the same, for example, when the thin film transistors in the pixel circuits 110 are all N-type transistors, the third switch 1221 and the fourth switch 1222 are also N-type transistors, thereby further simplifying the manufacturing process of the display panel.

Fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 4, optionally, each of the detection terminals (S1, S2 \8230;) is connected to the first ends A1 of at least two first control units 121, and each of the data terminals (D1, D2 \8230;) is connected to the fourth ends A4 of at least two second control units 122; the first control terminal C1 of the first control unit 121 electrically connected to the same detection terminal is connected to a different control signal line, and the third control terminal C3 of the second control unit 122 electrically connected to the same data terminal is connected to a different control signal line.

Referring to fig. 4, fig. 4 exemplarily outputs a case where each of the detection terminals is connected to the first terminals A1 of the two first control units 121, and each of the data terminals is connected to the fourth terminals A4 of the two second control units 122. Among the two first control units 121 electrically connected to the same detection terminal, the first control end C1 of one of the first control units 121 may be connected to the first gate line SW11, the first control end C1 of the other first control unit 121 may be connected to the second gate line SW12, and the driving chip 130 may transmit a turn-on control signal to the first gate line SW11 and the second gate line SW12 in a time-sharing manner, so that the first end A1 and the second end A2 of the first control unit 121 connected to the same detection terminal are turned on in a time-sharing manner, and the source s potential of the driving transistor T1 of different pixel circuits 110 in the same row is detected in a time-sharing manner. Similarly, the third control terminals C3 of the two second control units 122 electrically connected to the same data terminal may also be connected to different control signal lines (not shown), so that the second control units 122 electrically connected to the same data terminal are turned on in a time-sharing manner, and data voltages are written into the pixel circuits 110 in the same row in a time-sharing manner. In the display panel, the data terminals corresponding to each detection terminal are connected to the first control unit 121 and the second control unit 122 connected to the same pixel circuit 110, for example, one detection terminal is connected to the detection line connected to the first row of pixel circuits 110 and the detection line connected to the second row of pixel circuits 110 through the first control unit 121, and the data terminal corresponding to the detection terminal is connected to the data line connected to the first row of pixel circuits 110 and the data line connected to the second row of pixel circuits 110 through the second control unit 122.

The first ends A1 of the at least two first control units 121 are connected to each detection terminal, and the fourth ends A4 of the at least two second control units 122 are connected to each data terminal, so that the number of the data terminals and the number of the detection terminals can be further reduced, the occupied areas of the data terminals and the detection terminals on the display panel are reduced, and the realization of a narrow frame is facilitated. And when the data terminal and the detection terminal are directly used as the output port of the driving chip 130, the number of the ports of the driving chip 130 is more favorably reduced, and the miniaturization of the driving chip 130 is further favored.

Fig. 5 is a schematic structural diagram of another display panel provided in an embodiment of the present invention, and referring to fig. 5, optionally, the display panel at least includes a first pixel circuit 111, a second pixel circuit 112, and a third pixel circuit 113 corresponding to sub-pixels with different light emitting colors;

one first data line and one first detection line per column of the first pixel circuits 111; each column of the second pixel circuits 112 is connected to a second data line and a second detection line; each column of the third pixel circuits 113 is connected with a third data line and a third detection line;

each detection terminal is electrically connected with at least two of the three first control units 121 corresponding to the first detection line, the second detection line and the third detection line;

each data terminal is electrically connected to at least two of the three second control units 122 corresponding to the first, second, and third data lines;

the first control end C1 of the first control unit 121 electrically connected to the first detection line is connected to the first control signal line SW1, the first control end C1 of the first control unit 121 electrically connected to the second detection line is connected to the second control signal line SW2, and the first control end C1 of the first control unit 121 electrically connected to the third detection line is connected to the third control signal line SW3.

Specifically, to implement the display of multiple colors, multiple sub-pixels with different emission colors are usually disposed in the display panel, and may include, for example, a red sub-pixel, a green sub-pixel, and a blue sub-pixel, the first pixel circuit 111, the second pixel circuit 112, and the third pixel circuit 113 may be a pixel circuit corresponding to the red sub-pixel, a pixel circuit corresponding to the blue sub-pixel, and a pixel circuit corresponding to the blue sub-pixel, respectively, the pixel circuits 110 are arranged in an array in the display panel, referring to fig. 5, the first pixel circuit 111, the second pixel circuit 112, and the third pixel circuit 113 may be arranged column by column, specifically, the sub-pixels with the same color in the display panel may be located in the same column, and optionally, the first pixel circuit 111, the second pixel circuit 112, and the third pixel circuit 113 may be arranged at intervals column by column.

Fig. 5 exemplarily shows that each of the detection terminals is electrically connected to two of the three first control units 121 corresponding to the first detection line (the first detection line one SL11, the first detection line two SL12 \8230;), the second detection line (only SL22 is shown in the drawing), and the third detection line (only SL23 is shown in the drawing); each data terminal is electrically connected to two of the three second control units 122 corresponding to the first, second, and third data lines, and the data terminals are all multiplexed as the case of the detection terminal. Referring to fig. 5, fig. 5 schematically shows a data terminal D1 (detection terminal S1) and a data terminal D2 (detection terminal S2), wherein the detection terminal S1 (data terminal D1) is connected to the first control unit 121 connected to the first pixel circuit 111 through a first detection line SL11, and is connected to the first control unit 121 connected to the second pixel circuit 112 through a second detection line SL 21; the data terminal D1 (the detection terminal S1) is connected to the second control unit 122 connected to the first pixel circuit 111 through the first data line DL11, and connected to the second control unit 122 connected to the second pixel circuit 112 through the second data line DL 21. The detection terminal S2 (data terminal D2) is connected to the first control unit 121 connected to the third pixel circuit 113 through the third detection line SL31, and connected to the first control unit 121 connected to the first pixel circuit 111 through the first detection line two SL 12; the data terminal D2 (the detection terminal S2) is connected to the second control unit 122 connected to the first pixel circuit 111 through the third data line DL31, and connected to the second control unit 122 connected to the second pixel circuit 112 through the first data line DL 12.

Fig. 6 is a driving timing diagram of a display panel according to an embodiment of the invention, where the driving timing diagram shown in fig. 6 can be used to drive the display panel shown in fig. 5, and the driving timing diagram shown in fig. 6 can correspond to the driving timing diagram of the display panel shown in fig. 5 in a display mode. Among them, the control terminal of the second switch 1212 (i.e., the second control terminal C2 of the first control unit 121) may be connected to the fourth control signal line SEN1, and the control terminal of the fourth switch 1222 (i.e., the fourth control terminal C4 of the second control unit 121) may be connected to the fifth control signal line SEN2. The first control signal line SW1, the second control signal line SW2, the third control signal line SW3, the fourth control signal line SEN1 and the fifth control signal line SEN2 may be connected to a driving chip 130 including the display panel. Referring to fig. 5 and 6, taking the transistors shown in fig. 5 as N-type transistors as an example, the operation of the display panel shown in fig. 5 in the display mode is as follows.

The operation of the first two pixel circuits 110 in the row of pixel circuits 110 shown in fig. 5, that is, the leftmost first pixel circuit 111 and the second pixel circuit 2a adjacent to the leftmost first pixel circuit 1a shown in fig. 5, will be described. Illustratively, in the display mode, the signals transmitted by the driving chip 130 to the fifth control signal line SEN2, the first control signal line SW1, the second control signal line SW2 and the third control signal line SW3 are low level signals, so that in the display mode, all the fourth switches 1222 in the second control unit 122 are turned off, the initialization terminal Vrefn is disconnected from each data line, and all the first switches 1211 in the first control unit 121 are turned off, and the detection terminal is disconnected from the detection line. Referring to fig. 5 and 6, in the display mode, when data writing is performed, two stages, i.e., a first data writing stage t1 and a second data writing stage t2, may be divided. Referring to fig. 5 and 6, for the leftmost first pixel circuit 1a and the second pixel circuit 2a adjacent to the first pixel circuit 1a, in fig. 6, MUX1 indicates a signal input to the third control terminal C31 of the second control unit 122 corresponding to the row in which the first pixel circuit 1a is located and electrically connected to the data terminal D1 (the detection terminal S1), and MUX2 indicates a signal input to the third control terminal second C32 corresponding to the row in which the second pixel circuit 2a is located and electrically connected to the data terminal D1 (the detection terminal S1).

In the first data writing phase T1, the signal inputted from the first Scan signal input terminal Scan1, the signal inputted from the second Scan signal input terminal Scan2, the signal transmitted from the fourth control signal line SEN1, and the MUX1 signal are at high level, so that the data writing transistor T3 and the detecting transistor T2 of the first pixel circuit 1a at the leftmost side are turned on, the second switch 1212 in each first control unit 121 is turned on, and the third switch 1221 connected to the first data line DL11 is turned on, so that the initialization voltage outputted from the initialization terminal Vrefn is transmitted to the source s of the driving transistor T1 through the second switch 1212, the first detecting line SL11, and the detecting transistor T2 in the pixel circuit 110, so that the potential of the source s of the driving transistor T1 is fixed; and the first Data voltage Data1 output from the Data terminal D1 is transferred to the gate g of the driving transistor T1 in the first pixel circuit 1a through the turned-on third switch 1221 connected to the first Data line DL11, and the Data writing transistor T3 in the first pixel circuit 111.

In the second data writing phase T2, the signal input from the first Scan signal input terminal Scan1, the signal input from the second Scan signal input terminal Scan2, the signal transmitted from the fourth control signal line SEN1, and the signal of the MUX2 are at high level, the data writing transistor T3 and the detecting transistor T2 in the second pixel circuit 2a are both turned on, the second switch 1212 in each first control unit 121 is turned on, and the third switch 1221 in the second control unit 122 connected to the second data line DL21 in the two second control units 122 connected to the detecting terminal S1 (data terminal D1) is turned on; the initialization voltage outputted from the initialization terminal Vrefn is transmitted to the source s of the driving transistor T1 through the second switch 1212 of each first control unit 121 and the detecting transistor T2 in the pixel circuit 110, so that the source s of the driving transistor T1 is fixed in potential; and the second Data voltage Data2 output from the Data terminal is transmitted to the gate g of the driving transistor T1 in the second pixel circuit 2a through the turned-on third switch 1221 connected to the second Data line DL21 in the second control unit 122, the second Data line DL21, and the Data writing transistor T3 in the second pixel circuit 112.

Fig. 7 is a driving timing diagram of a display panel according to an embodiment of the invention, where the driving timing diagram shown in fig. 7 can be used for driving the display panel shown in fig. 5, and the driving timing diagram shown in fig. 7 can correspond to the driving timing diagram in the detection mode of the display panel shown in fig. 5. Referring to fig. 5 and fig. 7, taking the transistors shown in fig. 5 as N-type transistors as an example, the operation of the display panel shown in fig. 5 in the detection mode is as follows.

Referring to fig. 5 and 7, in the detection mode, the operation process of the display panel can be divided into three stages, i.e., a first detection stage t3, a second detection stage t4 and a third detection stage t5. For a row of pixel circuits 110, in the first detection period T3, the second detection period T4 and the third detection period T5, the first Scan signal input terminal Scan1 and the second Scan signal input terminal Scan2 of the current row of pixel circuits 110 (the scanning row of pixel circuits 110) both input high level signals, and the data writing transistor T3 and the detection transistor T2 of the current row of pixel circuits 110 are both turned on; the signal input by the fourth control signal line SEN1 is always a low level signal, the second switch 1212 of each first control unit 121 is turned off, and the initialization terminal Vrefn is disconnected from each detection line; the signal clock inputted by the fifth control signal line SEN2 is a high level signal, the fourth switch 1222 of each second control unit 122 is turned on, and the initialization terminal Vrefn is communicated with each data line, so that in the detection mode, the initialization voltage outputted by the initialization terminal Vrefn is transmitted to the gate g of the driving transistor T1 of each pixel circuit 110, so that the potential of the gate g of the driving transistor T1 is fixed to the initialization voltage.

With continued reference to fig. 5 and fig. 7, for a row of pixel circuits 110, in the first detection phase T3, the signal transmitted by the first control signal line SW1 is a high level signal, so that the first switch 1211 in the first control unit 121 corresponding to the first pixel circuit 111 is turned on, and the detection transistor T2 is always in a conducting state, thereby achieving the connection between the detection terminal and the gate g of the driving transistor T1 in the first pixel circuit 111.

In the second detection phase T4, the signal transmitted by the second control signal line SW2 is a high level signal, so the first switch 1211 in the first control unit 121 corresponding to the second pixel circuit 112 is turned on, and the detection transistor T2 is always in a conducting state, thereby achieving the connection between the detection terminal and the gate g of the driving transistor T1 in the second pixel circuit 112.

In the third detection phase T5, the signal transmitted by the third control signal line SW3 is a high level signal, so that the first switch 1211 in the first control unit 121 corresponding to the row of the third pixel circuit 113 is turned on, and the detection transistor T2 is always in a conducting state, thereby achieving the connection between the detection terminal and the gate g of the driving transistor T1 in the third pixel circuit 113.

Fig. 8 is a driving timing diagram of the display panel in the first detection phase in fig. 7 according to an embodiment of the present invention, referring to fig. 5, fig. 7 and fig. 8, when detecting a certain pixel circuit 110, the driving timing diagram can be divided into a preset voltage phase t31, a charging phase t32 and a sampling phase t33, taking the detection of the leftmost first pixel circuit 1a as an example:

when the preset voltage enable signal SPRE is at a high level in the preset voltage phase T31, the driving chip 130 writes a source potential control signal to the source S of the driving transistor T1 in the first pixel circuit 1a through the detection terminal S1, the first switch 1211 and the detection transistor T2, and when a potential corresponding to the source potential control signal is VREF in the preset voltage phase T31, a voltage value at which the lighting voltage of the organic light emitting element is lower than VREF may be set, and the organic light emitting element does not emit light in the preset voltage phase T31.

In the charging phase T32, the level of the preset voltage enable signal SPRE is set low, since the gate g of the driving transistor T1 in each pixel circuit 110 is written with the initialization voltage provided by the initialization terminal Vrefn, the driving transistor T1 is turned on, the signal input from the first power voltage input terminal charges the source s of the driving transistor T1, the source potential of the driving transistor T1 is increased from VREF to Vsen, and at this time, the driving transistor reaches the off-threshold state.

In the sampling phase T33, when the sampling enable signal SAMP has a falling edge, the driving chip 130 does not control the potential of the detecting terminal S1, and collects the source potential signal of the driving transistor T1 through the detecting terminal S1, that is, the driving chip 130 can detect the voltage value of Vsen, the driving chip 130 can obtain the threshold voltage Vth of the driving transistor T1 in the corresponding first pixel circuit 1a according to the pre-stored initialization voltage value, the threshold voltage Vth of the driving transistor T1 is the difference between Vsen and the initialization voltage (the voltage provided by the initialization terminal Vrefn), and further, when outputting the data signal to the corresponding first pixel circuit 1a in the display phase, the threshold voltage Vth is compensated into the data signal to eliminate the influence of the drift of the threshold voltage on the display uniformity.

Fig. 9 is a driving timing diagram of a display panel according to an embodiment of the invention, where the driving timing diagram shown in fig. 9 can be used for driving the display panel shown in fig. 5, and the driving timing diagram shown in fig. 9 can correspond to the driving timing diagram in the detection mode of the display panel shown in fig. 5. Referring to fig. 5 and 9, taking the transistors shown in fig. 5 as N-type transistors as an example, the operation of the display panel shown in fig. 5 in the detection mode is as follows.

Specifically, in the detection mode, the entire display panel is scanned at least three times, and fig. 9 schematically shows a process of scanning the entire display panel three times, wherein the three times of scanning can correspond to the first detection stage h1, the second detection stage h2, and the third detection stage h3, respectively. Wherein each time the display panel is scanned, the pixels circuits 110 in the first row are scanned to the pixels circuits 110 in the last row.

When the display panel is scanned for the first time, i.e., the first detection stage h1, a turn-on control signal is input to the first control signal line SW1 when each row of pixel circuits 110 in the display panel is scanned; when the display panel is scanned for the first time, the source s potential of the driving transistor T1 in the first pixel circuit 111 in the pixel circuit 110 of each row is detected when the pixel circuit 110 of each row of the display panel is scanned.

When the display panel is scanned for the second time, i.e., the second detection stage h2, the on-control signal is input to the second control signal line SW2 when each row of the pixel circuits 110 in the display panel is scanned; when the display panel is scanned for the second time, the source s potential of the driving transistor T1 in the second pixel circuit 112 of the pixel circuit 110 of each row of the pixel circuit 110 of the display panel is detected when the pixel circuit 110 of the row is scanned.

When the display panel is scanned for the third time, i.e., the third detection stage h3, when each row of pixel circuits 110 in the display panel is scanned, the on-control signal is input to the third control signal line SW 3; when the display panel is scanned for the third time, and each row of the pixel circuits 110 of the display panel is scanned, the source s potential of the driving transistor T1 in the third pixel circuit 113 in the row of the pixel circuits 110 is detected.

Therefore, each time the display panel is scanned, only the source s potential of the driving transistor T1 in the pixel circuit 110 corresponding to one color sub-pixel in one row needs to be detected in one scanning pulse, and compared with a method of simultaneously detecting the source s potentials of the driving transistors T1 in the pixel circuits 110 corresponding to three color sub-pixels in one scanning pulse, the pulse width of the scanning signal can be reduced, and the design difficulty of the gate driving circuit generating the scanning signal is reduced.

It should be noted that, in order to more clearly illustrate the connection relationship between the data terminal and the driving chip 130, the relationship between the detection terminal and the driving chip 130, and the connection relationship between the initialization power supply 140 and the initialization terminal Vrefn in the display panel, in the structural schematic diagrams of the display panel provided in the above embodiments, the driving chip 130 and the initialization power supply 140 are all shown, but the driving chip 130 and the initialization power supply 140 may not be included in the display panel but included in the display device, and the embodiment of the present invention is not limited herein.

The embodiment of the present invention further provides a driving method of a display panel, wherein the display panel includes a plurality of pixel circuits, a plurality of data lines, a plurality of detection lines, and control circuits corresponding to the data lines and the detection lines one to one, fig. 10 is a flowchart of the driving method of the display panel according to the embodiment of the present invention, and referring to fig. 10, the driving method of the display panel includes:

step 210, in the display mode, controlling the communication between the detection lines and the initialization terminals through the control circuit, and controlling the communication between the data lines and the corresponding data terminals through the control circuit;

in the detection mode, the control circuit controls the detection line to communicate with the corresponding detection terminal, and controls the data line to communicate with the initialization terminal.

In the driving method of the display panel provided by this embodiment, the detection line is controlled to be communicated with the initialization terminal and the data line is controlled to be communicated with the corresponding data terminal by the control circuit in the display mode, so that when data is written in the display mode, the source potential of the driving transistor remains unchanged, thereby avoiding the influence on the driving current caused by unfixed source potential of the driving transistor in data writing, and further ensuring the display uniformity of the display panel; and the control circuit controls the detection line to be communicated with the corresponding detection terminal and controls the data line to be communicated with the initialization terminal in the detection mode, so that the threshold voltage of the driving transistor is compensated through the outside by detecting the threshold voltage in the detection mode, the display uniformity is improved, meanwhile, the quantity of transistors and capacitance elements contained in the pixel circuit is less, and the pixel density is improved.

in the detection mode, scanning the whole display panel at least three times;

Fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 11, a display device 10 according to an embodiment of the present invention includes the display panel 100 according to any embodiment of the present invention. The display device may be a mobile phone as shown in fig. 11, or may be a computer, a television, an intelligent wearable display device, and the like, which is not particularly limited in this embodiment of the present invention. The display panel also comprises a driving chip and an initialization power supply, wherein the driving chip is electrically connected with the display panel, and the initialization power supply is electrically connected with the display panel. Specifically, the initialization power supply may include an initialization terminal or be electrically connected to the initialization terminal, the driving chip includes a data terminal and a detection terminal, or the driving chip is electrically connected to the data terminal and the initialization terminal, where the connection relationship between the display panel and the data terminal and the detection terminal of the driving chip, and the connection relationship between the display panel and the initialization terminal of the initialization power supply may refer to the schematic structural diagram of the display panel provided in any embodiment of the present invention.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, comprising: the pixel circuit comprises a plurality of pixel circuits, a plurality of data lines, a plurality of detection lines and control circuits which correspond to the data lines and the detection lines one to one;

the pixel circuit comprises a driving transistor, a detection transistor and a data writing transistor, wherein the data writing transistor is used for writing data voltage into a grid electrode of the driving transistor, the detection transistor is electrically connected with a source electrode of the driving transistor, the data writing transistor is electrically connected with the corresponding data line, and the detection transistor is electrically connected with the corresponding detection line;

the control circuit is used for controlling the detection lines to be communicated with the initialization terminal and the data lines to be communicated with the corresponding data terminals in a display mode;

the control circuit is also used for controlling the detection lines to be communicated with the corresponding detection terminals and controlling the data lines to be communicated with the initialization terminals in a detection mode;

multiplexing at least a part of the data terminals into the detection terminals;

the control circuit comprises a first control unit and a second control unit;

the second control unit comprises a third control end, a fourth end, a fifth end and a sixth end, the fourth end is electrically connected with the data terminal, the fifth end is electrically connected with the initialization terminal, and the sixth end is electrically connected with the data line; the second control unit is used for controlling the communication between the fourth end and the sixth end according to a signal input by the third control end in a display mode and controlling the communication between the fifth end and the sixth end according to a signal input by the fourth control end in a detection mode;

the display panel at least comprises a first pixel circuit, a second pixel circuit and a third pixel circuit which correspond to sub-pixels with different light-emitting colors;

each of the data terminals is electrically connected to at least two of the three second control units corresponding to the first data line, the second data line, and the third data line;

the first control end of the first control unit electrically connected with the first detection line is connected with a first control signal line, the first control end of the first control unit electrically connected with the second detection line is connected with a second control signal line, and the first control end of the first control unit electrically connected with the third detection line is connected with a third control signal line.

2. The display panel according to claim 1, wherein the first control unit comprises a first switch and a second switch; the control end of the first switch is used as the first control end of the first control unit, the first end of the first switch is used as the first end of the first control unit, and the second end of the first switch is electrically connected with the third end of the first control unit; the control end of the second switch is used as the second control end of the first control unit, the first end of the second switch is used as the second end of the first control unit, and the second end of the second switch is electrically connected with the third end of the first control unit.

3. The display panel according to claim 1, wherein the second control unit includes a third switch and a fourth switch; a control end of the third switch is used as a third control end of the second control unit, a first end of the third switch is used as a fourth end of the second control unit, and a second end of the third switch is electrically connected with a sixth end of the second control unit; a control end of the third switch is used as a fourth control end of the second control unit, a first end of the fourth switch is used as a fifth end of the second control unit, and a second end of the fourth switch is electrically connected with a sixth end of the second control unit.

4. The display panel according to claim 1, wherein each of the detection terminals is connected to first terminals of at least two of the first control units, and each of the data terminals is connected to fourth terminals of at least two of the second control units; the first control end of the first control unit electrically connected with the same detection terminal is connected with different control signal lines, and the third control end of the second control unit electrically connected with the same data terminal is connected with different control signal lines.

5. The display panel according to claim 1,

the pixel circuit further comprises a capacitor connected between the gate and the source of the drive transistor,

in a detection mode, the detection line is controlled to be communicated with the corresponding detection terminal, and the data line is controlled to be communicated with the initialization terminal, so that the threshold voltage of the driving transistor is detected;

in the detection mode, the driving chip writes a source potential control signal into the source of the driving transistor through the multiplexed detection terminal, the gate of the driving transistor is written with an initialization voltage provided by the initialization terminal, the driving transistor is conducted, and a signal input by the first power supply voltage input terminal charges the source of the driving transistor.

6. The driving method of the display panel is characterized in that the display panel comprises a plurality of pixel circuits, a plurality of data lines, a plurality of detection lines and control circuits which are in one-to-one correspondence with the data lines and the detection lines; the driving method includes:

in a display mode, the detection lines are controlled to be communicated with the initialization terminals through the control circuit, and the data lines are controlled to be communicated with the corresponding data terminals through the control circuit;

in a detection mode, the detection line is controlled to be communicated with the corresponding detection terminal through the control circuit, and the data line is controlled to be communicated with the initialization terminal through the control circuit;

the control circuit comprises a first control unit and a second control unit; the first control unit comprises a first control end, a second control end, a first end, a second end and a third end, wherein the first end is electrically connected with the detection terminal, the second end is electrically connected with the initialization terminal, and the third end is electrically connected with the detection line; the second control unit comprises a third control end, a fourth end, a fifth end and a sixth end, the fourth end is electrically connected with the data terminal, the fifth end is electrically connected with the initialization terminal, and the sixth end is electrically connected with the data line;

the pixel circuit at least comprises a first pixel circuit, a second pixel circuit and a third pixel circuit which correspond to sub-pixels with different light-emitting colors;

7. The method for driving a display panel according to claim 6,

under the detection mode, through control circuit control detect the line with the detection terminal intercommunication that corresponds, include:

in the detection mode, when each row of pixel circuits in the display panel is scanned, the conducting control signals are sequentially input to the first control signal line, the second control signal line and the third control signal line.

8. The method according to claim 6, wherein the control circuit includes a first control unit and a second control unit; the first control unit comprises a first control end, a second control end, a first end, a second end and a third end, wherein the first end is electrically connected with the detection terminal, the second end is electrically connected with the initialization terminal, and the third end is electrically connected with the detection line; the second control unit comprises a third control end, a fourth end, a fifth end and a sixth end, the fourth end is electrically connected with the data terminal, the fifth end is electrically connected with the initialization terminal, and the sixth end is electrically connected with the data line;

the pixel circuit at least comprises a first pixel circuit, a second pixel circuit and a third pixel circuit which correspond to different luminous color sub-pixels;

under the mode of listening, through control circuit control the detection line communicates with the detection terminal that corresponds, includes:

in the detection mode, scanning the whole display panel at least three times;

when the display panel is scanned for the first time, inputting a conducting control signal to the first control signal line when each row of pixel circuits in the display panel is scanned;

when the display panel is scanned for the second time, inputting a conducting control signal to the second control signal line when each row of pixel circuits in the display panel is scanned;

and when the display panel is scanned for the third time, inputting a conducting control signal to the third control signal line when each row of pixel circuits in the display panel is scanned.

9. A display device characterized by comprising the display panel according to any one of claims 1 to 5; the display panel is characterized by further comprising a driving chip and an initialization power supply, wherein the driving chip is electrically connected with the display panel, and the initialization power supply is electrically connected with the display panel.