CN111026571A - Processor frequency reduction processing method and device and electronic equipment - Google Patents
Processor frequency reduction processing method and device and electronic equipment Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0709—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a distributed system consisting of a plurality of standalone computer nodes, e.g. clusters, client-server systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The embodiment of the disclosure provides a processor frequency reduction processing method, a processor frequency reduction processing device and electronic equipment, and belongs to the technical field of data processing, wherein the method comprises the following steps: determining the actual operating frequency of the target processor based on the obtained TSC frequency, the actual frequency variable and the reference frequency variable; determining a frequency deviation value for the target processor based on the actual operating frequency and an expected operating frequency of the target processor; when the frequency deviation value is larger than a first threshold value, further acquiring an actual power consumption value of the target processor; and when the actual power consumption value is smaller than a second threshold value, executing filtering processing on the target processor. Through the scheme disclosed by the invention, the fault processor can be quickly and accurately identified and processed.
Description
Technical Field
The present disclosure relates to the field of data processing technologies, and in particular, to a processor frequency reduction processing method and apparatus, and an electronic device.
Background
A data center is a globally collaborative network of devices that is used to communicate, accelerate, present, compute, store data information over an internet network infrastructure. Most of the electronic components of the data center are driven by low direct current power supplies to operate. The generation of data centers has led to the introduction of people's awareness from the quantitative, structured world to the uncertain and unstructured world, which, like traffic and network communications, will gradually become part of the infrastructure of modern society, thus positively affecting many industries.
Data centers are made up of numerous pieces of computer hardware, which can cause problems with the hardware, resulting in partial functionality not being properly performed or functioning. The data center often has some complex reasons to cause the running frequency of the CPU to dynamically change, which causes the performance difference between a single machine and a cluster and configured machine, thereby affecting the processing efficiency of the whole data center.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a processor frequency reduction processing method, an apparatus, and an electronic device, which at least partially solve the problems in the prior art.
In a first aspect, an embodiment of the present disclosure provides a processor frequency reduction processing method, including:
determining the actual operating frequency of the target processor based on the obtained TSC frequency, the actual frequency variable and the reference frequency variable;
determining a frequency deviation value for the target processor based on the actual operating frequency and an expected operating frequency of the target processor;
when the frequency deviation value is larger than a first threshold value, further acquiring an actual power consumption value of the target processor;
and when the actual power consumption value is smaller than a second threshold value, executing filtering processing on the target processor.
According to a specific implementation manner of the embodiment of the present disclosure, the determining an actual operating frequency of a target processor based on the acquired TSC frequency, an actual frequency variable, and a reference frequency variable includes:
dividing the actual frequency variable and the reference frequency variable to obtain a frequency ratio;
and determining the product of the frequency ratio and the TSC frequency as the actual operating frequency of the target processor.
According to a specific implementation manner of the embodiment of the present disclosure, the determining an actual operating frequency of a target processor based on the acquired TSC frequency, an actual frequency variable, and a reference frequency variable includes:
and acquiring the TSC frequency, the actual frequency variable and the reference frequency variable of the target processor in real time every preset time period.
According to a specific implementation manner of the embodiment of the present disclosure, the determining a frequency deviation value of the target processor based on the actual operating frequency and the expected operating frequency of the target processor includes:
calculating a frequency difference between the actual operating frequency and the desired operating frequency;
and determining the frequency deviation value of the target processor according to the absolute value of the frequency difference value.
According to a specific implementation manner of the embodiment of the present disclosure, before determining the frequency deviation value of the target processor based on the actual operating frequency and the expected operating frequency of the target processor, the method further includes:
sending an expected operation frequency acquisition request to a target server;
analyzing a response request sent by the target server aiming at the expected operation frequency acquisition request to obtain an analysis result;
determining the desired operating frequency of the target processor based on the parsed result.
According to a specific implementation manner of the embodiment of the present disclosure, before further acquiring the actual power consumption value of the target processor when the frequency deviation value is greater than the first threshold, the method further includes:
acquiring a first threshold corresponding to the target processor;
and judging whether the frequency deviation value is larger than the first threshold value.
According to a specific implementation manner of the embodiment of the present disclosure, the obtaining the actual power consumption value of the target processor includes:
acquiring an ID (identity) of a target processor;
sending the ID identification and the power query request to a target server;
determining an actual power consumption value for the target processor based on the power response of the target server.
According to a specific implementation manner of the embodiment of the present disclosure, when the actual power consumption value is smaller than a second threshold, performing a filtering process on the target processor includes:
deleting the identification of the target processor in the cluster of data center processors;
stopping the execution of the target processor after the identification of the target processor is deleted.
In a second aspect, an embodiment of the present disclosure provides a processor frequency reduction processing apparatus, including:
the first determining module is used for determining the actual operating frequency of the target processor based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable;
a second determination module to determine a frequency deviation value for the target processor based on the actual operating frequency and a desired operating frequency of the target processor;
the obtaining module is used for further obtaining the actual power consumption value of the target processor when the frequency deviation value is larger than a first threshold value;
and the execution module is used for executing filtering processing on the target processor when the actual power consumption value is smaller than a second threshold value.
In a third aspect, an embodiment of the present disclosure further provides an electronic device, where the electronic device includes:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the processor frequency reduction processing method of any one of the preceding first aspect or any implementation manner of the first aspect.
In a fourth aspect, the disclosed embodiments also provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the processor frequency reduction processing method in the first aspect or any implementation manner of the first aspect.
In a fifth aspect, the disclosed embodiments also provide a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions that, when executed by a computer, cause the computer to perform the processor frequency reduction processing method in the foregoing first aspect or any implementation manner of the first aspect.
The frequency reduction processing scheme of the processor in the embodiment of the disclosure comprises the steps of determining the actual operating frequency of a target processor based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable; determining a frequency deviation value for the target processor based on the actual operating frequency and an expected operating frequency of the target processor; when the frequency deviation value is larger than a first threshold value, further acquiring an actual power consumption value of the target processor; and when the actual power consumption value is smaller than a second threshold value, executing filtering processing on the target processor. Through the scheme of the disclosure, the fault processor can be automatically identified and processed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram illustrating a frequency reduction processing flow of a processor according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram illustrating another processor frequency reduction processing flow provided by the embodiment of the disclosure;
fig. 3 is a schematic diagram illustrating another processor frequency reduction processing flow provided by the embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating another processor frequency reduction processing flow provided by the embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a processor frequency reduction processing apparatus according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of an electronic device provided in an embodiment of the present disclosure.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
The embodiment of the disclosure provides a frequency reduction processing method for a processor. The processor frequency reduction processing method provided by the embodiment may be executed by a computing device, which may be implemented as software or implemented as a combination of software and hardware, and may be integrally provided in a server, a terminal device, or the like.
Referring to fig. 1, a processor frequency reduction processing method provided in the embodiment of the present disclosure includes the following steps:
s101, determining the actual operation frequency of the target processor based on the obtained TSC frequency, the actual frequency variable and the reference frequency variable.
Data centers often contain a large number of processors, and there are situations where some of the processors fail during long-term operation. Since these processors are distributed in an array, it is difficult to find out a processor in time after a failure occurs.
For this purpose, real-time operation data of each processor (e.g., a target processor) in the data center may be periodically obtained, and whether the processor fails or not may be further determined by whether the operation data of each processor is abnormal or not.
As an embodiment, the TSC frequency, the actual frequency variable and the reference frequency variable of the target processor may be obtained, and the actual operating frequency of the target processor may be determined by the TSC frequency, the actual frequency variable and the reference frequency variable.
Specifically, the actual frequency variable may be first divided by the reference frequency variable to obtain a frequency ratio, and then the frequency ratio may be multiplied by the TSC frequency to obtain the actual operating frequency of the target processor.
S102, determining a frequency deviation value of the target processor based on the actual operating frequency and the expected operating frequency of the target processor.
The target processor develops an expected operating frequency over extended periods of operation, the expected operating frequency indicating the frequency at which the target processor operates normally. For this purpose, the expected operating frequency of the target processor may be obtained by sending a request to the target server. The target server is a server for managing all processors in the data center, and the target server records frequency values of all processors in a period of time, and the expected operating frequency of the target processor can be calculated through the frequency values.
After the expected operating frequency of the target processor is obtained, the actual operating frequency and the expected operating frequency may be subjected to a difference operation, and an absolute value of a difference operation result may be used as a frequency deviation value of the target processor. By means of the frequency deviation value, the difference between the actual working condition and the expected working condition of the target processor can be characterized.
S103, when the frequency deviation value is larger than a first threshold value, further acquiring an actual power consumption value of the target processor.
In the actual operation process of the target processor, the frequency of the processor fluctuates due to different working contents. At the same time, however, the data center does not perform load balancing of tasks for a large number of processors, so that the offset value of each processor is not too large.
Based on this, a first threshold value may be set for the deviation value, and by comparing whether the frequency deviation value of the target processor is greater than the first threshold value, it may be determined whether there is an abnormality in the target processor.
When the frequency deviation value is larger than the first threshold value, in order to further assist in judging whether the target processor has an abnormality, the actual power consumption value of the target processor may be further obtained. The actual power consumption value of the target processor can characterize the operating state of the target processor from the other side. Generally speaking, the smaller the frequency deviation value of the target processor, the larger the actual power consumption value of the target processor.
And S104, when the actual power consumption value is smaller than a second threshold value, executing filtering processing on the target processor.
Different processors have different power consumption values, and for this purpose, the model of the target processor may be acquired based on the ID of the target processor, thereby further acquiring the second threshold corresponding to the power consumption value of the target processor. The second threshold may be set according to actual conditions to indicate whether the processor is in a normal power consumption operation state.
When the actual power consumption value of the target processor is found to be smaller than the second threshold value through comparison, the target processor can be determined to have an exception, and filtering processing can be performed on the target processor. For example, a target processor with an exception may be culled directly in the data center.
Through the scheme in the embodiment, whether the target processor is abnormal or not can be judged based on the frequency deviation value and the actual power consumption value of the target processor, so that the processor with the abnormality can be timely eliminated.
Referring to fig. 2, according to a specific implementation manner of the embodiment of the present disclosure, the determining an actual operating frequency of a target processor based on the acquired TSC frequency, an actual frequency variable, and a reference frequency variable includes:
s201, dividing the actual frequency variable and the reference frequency variable to obtain a frequency ratio;
s202, determining the product of the frequency ratio and the TSC frequency as the actual operating frequency of the target processor.
In this way, the actual operating frequency of the target processor can be quickly calculated.
According to a specific implementation manner of the embodiment of the present disclosure, the determining an actual operating frequency of a target processor based on the acquired TSC frequency, an actual frequency variable, and a reference frequency variable includes: and acquiring the TSC frequency, the actual frequency variable and the reference frequency variable of the target processor in real time every preset time period. The state of the target processor can be monitored in real time by periodically acquiring relevant parameters of the target processor.
According to a specific implementation manner of the embodiment of the present disclosure, the determining a frequency deviation value of the target processor based on the actual operating frequency and the expected operating frequency of the target processor includes: calculating a frequency difference between the actual operating frequency and the desired operating frequency; and determining the frequency deviation value of the target processor according to the absolute value of the frequency difference value. By calculating the frequency deviation value of the target processor, whether the target processor is abnormal or not can be further judged.
Referring to fig. 3, according to a specific implementation manner of the embodiment of the present disclosure, before determining the frequency deviation value of the target processor based on the actual operating frequency and the expected operating frequency of the target processor, the method further includes:
s301, a request for obtaining the expected operation frequency is sent to the target server.
The target processor develops an expected operating frequency over extended periods of operation, the expected operating frequency indicating the frequency at which the target processor operates normally. For this purpose, the expected operating frequency of the target processor may be obtained by sending a request to the target server.
S302, analyzing the response request sent by the target server aiming at the expected operation frequency acquisition request to obtain an analysis result.
S303, determining the expected operating frequency of the target processor based on the analysis result.
By the method in the embodiment, the expected operating frequency of the target processor can be rapidly acquired.
According to a specific implementation manner of the embodiment of the present disclosure, before further acquiring the actual power consumption value of the target processor when the frequency deviation value is greater than the first threshold, the method further includes: acquiring a first threshold corresponding to the target processor; and judging whether the frequency deviation value is larger than the first threshold value. Whether the frequency deviation value is larger than the first threshold value or not can be further judged, and whether the target processor is abnormal or not can be further judged.
Referring to fig. 4, according to a specific implementation manner of the embodiment of the present disclosure, the obtaining an actual power consumption value of the target processor includes:
s401, obtaining the ID identification of the target processor.
Different processors have different power consumption values, and for this purpose, the model of the target processor can be obtained based on the ID of the target processor, and for this purpose, the model of the target processor can be identified by reading the ID identification of the target processor.
S402, the ID identification and the power inquiry request are sent to a target server.
By sending the ID identification and the power inquiry request to the target server, the actual power consumption value corresponding to the target processor can be inquired in the target server.
S403, determining an actual power consumption value of the target processor based on the power response of the target server.
By the scheme of the embodiment, the actual power consumption value of the target processor can be rapidly inquired.
According to a specific implementation manner of the embodiment of the present disclosure, when the actual power consumption value is smaller than a second threshold, performing a filtering process on the target processor includes: deleting the identification of the target processor in the cluster of data center processors; stopping the execution of the target processor after the identification of the target processor is deleted. By the method, the processors in the abnormal state can be timely eliminated.
Corresponding to the above method embodiment, referring to fig. 5, an embodiment of the present disclosure further provides a processor frequency reduction processing apparatus 50, including:
a first determining module 501, configured to determine an actual operating frequency of the target processor based on the obtained TSC frequency, the actual frequency variable, and the reference frequency variable.
Data centers often contain a large number of processors, and there are situations where some of the processors fail during long-term operation. Since these processors are distributed in an array, it is difficult to find out a processor in time after a failure occurs.
For this purpose, real-time operation data of each processor (e.g., a target processor) in the data center may be periodically obtained, and whether the processor fails or not may be further determined by whether the operation data of each processor is abnormal or not.
As an embodiment, the TSC frequency, the actual frequency variable and the reference frequency variable of the target processor may be obtained, and the actual operating frequency of the target processor may be determined by the TSC frequency, the actual frequency variable and the reference frequency variable.
Specifically, the actual frequency variable may be first divided by the reference frequency variable to obtain a frequency ratio, and then the frequency ratio may be multiplied by the TSC frequency to obtain the actual operating frequency of the target processor.
A second determining module 502 for determining a frequency deviation value of the target processor based on the actual operating frequency and the desired operating frequency of the target processor.
The target processor develops an expected operating frequency over extended periods of operation, the expected operating frequency indicating the frequency at which the target processor operates normally. For this purpose, the expected operating frequency of the target processor may be obtained by sending a request to the target server. The target server is a server for managing all processors in the data center, and the target server records frequency values of all processors in a period of time, and the expected operating frequency of the target processor can be calculated through the frequency values.
After the expected operating frequency of the target processor is obtained, the actual operating frequency and the expected operating frequency may be subjected to a difference operation, and an absolute value of a difference operation result may be used as a frequency deviation value of the target processor. By means of the frequency deviation value, the difference between the actual working condition and the expected working condition of the target processor can be characterized.
An obtaining module 503, configured to further obtain an actual power consumption value of the target processor when the frequency deviation value is greater than a first threshold.
In the actual operation process of the target processor, the frequency of the processor fluctuates due to different working contents. At the same time, however, the data center does not perform load balancing of tasks for a large number of processors, so that the offset value of each processor is not too large.
Based on this, a first threshold value may be set for the deviation value, and by comparing whether the frequency deviation value of the target processor is greater than the first threshold value, it may be determined whether there is an abnormality in the target processor.
When the frequency deviation value is larger than the first threshold value, in order to further assist in judging whether the target processor has an abnormality, the actual power consumption value of the target processor may be further obtained. The actual power consumption value of the target processor can characterize the operating state of the target processor from the other side. Generally speaking, the smaller the frequency deviation value of the target processor, the larger the actual power consumption value of the target processor.
An executing module 504, configured to execute a filtering process on the target processor when the actual power consumption value is smaller than a second threshold.
Different processors have different power consumption values, and for this purpose, the model of the target processor may be acquired based on the ID of the target processor, thereby further acquiring the second threshold corresponding to the power consumption value of the target processor. The second threshold may be set according to actual conditions to indicate whether the processor is in a normal power consumption operation state.
When the actual power consumption value of the target processor is found to be smaller than the second threshold value through comparison, the target processor can be determined to have an exception, and filtering processing can be performed on the target processor. For example, a target processor with an exception may be culled directly in the data center.
Through the scheme in the embodiment, whether the target processor is abnormal or not can be judged based on the frequency deviation value and the actual power consumption value of the target processor, so that the processor with the abnormality can be timely eliminated.
The apparatus shown in fig. 5 may correspondingly execute the content in the above method embodiment, and details of the part not described in detail in this embodiment refer to the content described in the above method embodiment, which is not described again here.
Referring to fig. 6, an embodiment of the present disclosure also provides an electronic device 60, including:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the processor frequency reduction processing method of the foregoing method embodiments.
The disclosed embodiments also provide a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the foregoing method embodiments.
The disclosed embodiments also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the processor frequency reduction processing method in the aforementioned method embodiments.
Referring now to FIG. 6, a schematic diagram of an electronic device 60 suitable for use in implementing embodiments of the present disclosure is shown. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., car navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, and the like. The electronic device shown in fig. 6 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.
As shown in fig. 6, the electronic device 60 may include a processing means (e.g., a central processing unit, a graphics processor, etc.) 601 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)602 or a program loaded from a storage means 608 into a Random Access Memory (RAM) 603. In the RAM 603, various programs and data necessary for the operation of the electronic apparatus 60 are also stored. The processing device 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
Generally, the following devices may be connected to the I/O interface 605: input devices 606 including, for example, a touch screen, touch pad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 607 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 608 including, for example, tape, hard disk, etc.; and a communication device 609. The communication means 609 may allow the electronic device 60 to communicate with other devices wirelessly or by wire to exchange data. While the figures illustrate an electronic device 60 having various means, it is to be understood that not all illustrated means are required to be implemented or provided. More or fewer devices may alternatively be implemented or provided.
In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means 609, or may be installed from the storage means 608, or may be installed from the ROM 602. The computer program, when executed by the processing device 601, performs the above-described functions defined in the methods of the embodiments of the present disclosure.
It should be noted that the computer readable medium in the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present disclosure, a computer readable signal medium may comprise a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.
The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.
The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to: acquiring at least two internet protocol addresses; sending a node evaluation request comprising the at least two internet protocol addresses to node evaluation equipment, wherein the node evaluation equipment selects the internet protocol addresses from the at least two internet protocol addresses and returns the internet protocol addresses; receiving an internet protocol address returned by the node evaluation equipment; wherein the obtained internet protocol address indicates an edge node in the content distribution network.
Alternatively, the computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to: receiving a node evaluation request comprising at least two internet protocol addresses; selecting an internet protocol address from the at least two internet protocol addresses; returning the selected internet protocol address; wherein the received internet protocol address indicates an edge node in the content distribution network.
Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units described in the embodiments of the present disclosure may be implemented by software or hardware. Where the name of a unit does not in some cases constitute a limitation of the unit itself, for example, the first retrieving unit may also be described as a "unit for retrieving at least two internet protocol addresses".
It should be understood that portions of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (11)
1. A frequency reduction processing method for a processor is characterized by comprising the following steps:
determining the actual operating frequency of the target processor based on the obtained TSC frequency, the actual frequency variable and the reference frequency variable;
determining a frequency deviation value for the target processor based on the actual operating frequency and an expected operating frequency of the target processor;
when the frequency deviation value is larger than a first threshold value, further acquiring an actual power consumption value of the target processor;
and when the actual power consumption value is smaller than a second threshold value, executing filtering processing on the target processor.
2. The method of claim 1, wherein determining an actual operating frequency of a target processor based on the obtained TSC frequency, the actual frequency variable, and the reference frequency variable comprises:
dividing the actual frequency variable and the reference frequency variable to obtain a frequency ratio;
and determining the product of the frequency ratio and the TSC frequency as the actual operating frequency of the target processor.
3. The method of claim 1, wherein determining an actual operating frequency of a target processor based on the obtained TSC frequency, the actual frequency variable, and the reference frequency variable comprises:
and acquiring the TSC frequency, the actual frequency variable and the reference frequency variable of the target processor in real time every preset time period.
4. The method of claim 1, wherein determining the frequency deviation value for the target processor based on the actual operating frequency and the desired operating frequency for the target processor comprises:
calculating a frequency difference between the actual operating frequency and the desired operating frequency;
and determining the frequency deviation value of the target processor according to the absolute value of the frequency difference value.
5. The method of claim 1, wherein prior to determining the frequency deviation value for the target processor based on the actual operating frequency and the desired operating frequency for the target processor, the method further comprises:
sending an expected operation frequency acquisition request to a target server;
analyzing a response request sent by the target server aiming at the expected operation frequency acquisition request to obtain an analysis result;
determining the desired operating frequency of the target processor based on the parsed result.
6. The method of claim 1, wherein before further obtaining the actual power consumption value of the target processor when the frequency deviation value is greater than the first threshold, the method further comprises:
acquiring a first threshold corresponding to the target processor;
and judging whether the frequency deviation value is larger than the first threshold value.
7. The method of claim 1, wherein obtaining the actual power consumption value of the target processor comprises:
acquiring an ID (identity) of a target processor;
sending the ID identification and the power query request to a target server;
determining an actual power consumption value for the target processor based on the power response of the target server.
8. The method of claim 1, wherein performing a filtering process on the target processor when the actual power consumption value is less than a second threshold value comprises:
deleting the identification of the target processor in the cluster of data center processors;
stopping the execution of the target processor after the identification of the target processor is deleted.
9. A processor frequency reduction processing apparatus, comprising:
the first determining module is used for determining the actual operating frequency of the target processor based on the acquired TSC frequency, the actual frequency variable and the reference frequency variable;
a second determination module to determine a frequency deviation value for the target processor based on the actual operating frequency and a desired operating frequency of the target processor;
the obtaining module is used for further obtaining the actual power consumption value of the target processor when the frequency deviation value is larger than a first threshold value;
and the execution module is used for executing filtering processing on the target processor when the actual power consumption value is smaller than a second threshold value.
10. An electronic device, characterized in that the electronic device comprises:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the processor frequency reduction processing method of any one of claims 1-8.
11. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the processor frequency reduction processing method of any of the preceding claims 1-8.
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