CN111026236A - Memory device - Google Patents

Memory device Download PDF

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Publication number
CN111026236A
CN111026236A CN201911345781.7A CN201911345781A CN111026236A CN 111026236 A CN111026236 A CN 111026236A CN 201911345781 A CN201911345781 A CN 201911345781A CN 111026236 A CN111026236 A CN 111026236A
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China
Prior art keywords
memory
heating
chip
closed cavity
heating element
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Pending
Application number
CN201911345781.7A
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Chinese (zh)
Inventor
邓玉良
唐越
殷中云
方晓伟
杨彬
苏通
李昂阳
朱晓锐
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Shenzhen State Micro Electronics Co Ltd
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Shenzhen State Micro Electronics Co Ltd
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Priority to CN201911345781.7A priority Critical patent/CN111026236A/en
Publication of CN111026236A publication Critical patent/CN111026236A/en
Pending legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16Constructional details or arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention relates to the technical field of electronic devices, and provides a memory, which comprises a closed cavity, a plurality of memory chips arranged in the closed cavity, and a plurality of heating elements arranged in the closed cavity and used for providing annealing heat sources for the memory chips. The memory of the invention encapsulates the memory chip and the heating element in a closed cavity, thereby ensuring the heat insulation requirement during annealing, and simultaneously, the heating element provides a heat source for the memory chip to meet the annealing requirement. Therefore, under an extreme environment or a condition that the memory chip is not suitable for being disassembled to be annealed, the memory can be autonomously annealed, and the memory is prevented from being disassembled to be annealed and maintained.

Description

Memory device
Technical Field
The invention relates to the technical field of electronic devices, and particularly provides a memory.
Background
The memory is an important component of an electronic system as a data storage carrier. In recent years, the memory is developed to have low power consumption and high density, and the process size is also getting smaller and smaller. The mainstream memories used at present are Flash and DRAM, and due to the structure of the memory unit, the process size is reduced, so that the device is easily influenced by external radiation particles, and the storage information retention time is reduced and the device fails due to the structural degradation of transistor leakage, insulation characteristic reduction and the like. Failures caused by these oxide layer defects can be recovered by annealing. Therefore, annealing is required to eliminate the above problem. However, the conventional annealing method is to take the memory out and place it in an annealing furnace for annealing. However, under extreme conditions or when it is not appropriate to remove the memory, the memory cannot be recovered by annealing.
Disclosure of Invention
The invention aims to provide a memory, aiming at solving the problem that the existing memory cannot realize autonomous annealing.
In order to achieve the purpose, the invention adopts the technical scheme that: a memory comprises a closed cavity, a plurality of memory chips arranged in the closed cavity and a plurality of heating elements arranged in the closed cavity and used for providing annealing heat sources for the memory chips.
In one embodiment, the number of the memory chips and the number of the heating elements are both one, and the memory chips and the heating elements are stacked in the closed cavity from top to bottom.
In one embodiment, the number of the memory chips is at least two, the number of the heating elements is at least one, and the memory chips and the heating elements are alternately stacked in the closed cavity from bottom to top.
In one embodiment, the memory chip is arranged on the inner side of the bottom of the closed cavity, and the heating element is arranged on the inner side of the top of the closed cavity.
In one embodiment, the memory chip is arranged on the inner side of the bottom of the closed cavity, and the heating element is arranged around the outer side of the memory chip.
In one embodiment, the reservoir further comprises a first auxiliary heating element provided inside the top of the closed cavity.
In one embodiment, the memory further includes a second auxiliary heating member which is provided around an outer side of the memory chip.
In one embodiment, the memory further includes a second auxiliary heating member which is provided around an outer side of the memory chip.
In one embodiment, the heating element is one or more of a heating chip, a resistance wire and a carbon rod.
In one embodiment, the heating chip comprises a chip body, a plurality of heating units which are arranged on the chip body and work independently, and a plurality of temperature sensors arranged on the chip body.
The invention has the beneficial effects that: according to the memory provided by the invention, the memory chip and the heating element are packaged in a closed cavity, so that the thermal insulation requirement during annealing is ensured, and meanwhile, the heating element provides a heat source for the memory chip so as to meet the annealing requirement of the memory chip. Therefore, under an extreme environment or a condition that the memory chip is not suitable for being disassembled to be annealed, the memory can be autonomously annealed, and the memory is prevented from being disassembled to be annealed and maintained.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a cross-sectional view of a memory according to an embodiment of the invention;
FIG. 2 is another cross-sectional view of a memory according to an embodiment of the invention;
FIG. 3 is a cross-sectional view of a memory according to an embodiment of the invention;
FIG. 4 is a cross-sectional view of a memory according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a heating element of a memory according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of a memory according to a second embodiment of the present invention;
FIG. 7 is a cross-sectional view of a memory according to a third embodiment of the present invention;
fig. 8 is a cross-sectional view of a memory according to a fourth embodiment of the invention.
Wherein, in the figures, the respective reference numerals:
the heating device comprises a closed cavity 10, a memory chip 20, a heating member 30, a first auxiliary heating member 40, a second auxiliary heating member 50, a cover body 11, a substrate 12, a chip body 31, a heating unit 32 and a temperature sensor 33.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the description of the present invention, it is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1, a memory according to an embodiment of the present invention includes a closed cavity 10, a plurality of memory chips 20 disposed in the closed cavity 10, and a plurality of heating elements 30 disposed in the closed cavity 10 and used for providing an annealing heat source to the memory chips 20. Here, the closed cavity 10 may be a package for isolating an internal temperature and preventing components outside the closed cavity from being affected by a high temperature, and the heating member 30 provides an annealing heat source for the memory chip 20.
According to the memory provided by the embodiment of the invention, the memory chip 20 and the heating element 30 are packaged in the closed cavity 10, so that the heat insulation requirement during annealing is ensured, and meanwhile, the heating element 30 provides a heat source for the memory chip 20 to meet the annealing requirement. Thus, under extreme environments or conditions that the memory chip 20 is not suitable to be disassembled for annealing, the memory can be autonomously annealed, and the memory is prevented from being disassembled to achieve annealing maintenance.
Referring to fig. 1, in the present embodiment, the closed cavity 10 includes a cover 11 and a substrate 12 sealed at an opening end of the cover 11, and the substrate 12 is directly electrically connected to an external control circuit. Namely, the cover body 11 and the substrate 12 enclose to form a closed space, so that the efficiency of internal heat outward diffusion is reduced. Preferably, the substrate 12 is a low thermal resistance substrate.
Example one
Referring to fig. 1, in the present embodiment, the number of the memory chips 20 and the number of the heating members 30 are one, and the memory chips 20 and the heating members 30 are stacked in the closed cavity 10 from top to bottom. Specifically, the memory chip 20 is placed on the heating member 30 in the form of a pyramid structure in a 3D stacking manner. I.e., the heating member 30 operates, to transfer heat directly to the memory chip 20 to effect the annealing process. Preferably, the heating element 30 is a heating chip, the memory chip 20 is stacked on the heating chip, and the leads of the memory chip 20 are directly connected to the substrate 12, so that the length of the leads of the memory chip 20 is reduced, which is beneficial to the signal integrity of the memory chip 20. Meanwhile, the pins of the heating chip are directly connected to the substrate 12 of the enclosed cavity 10, and the substrate 12 is directly electrically connected to the external control circuit, so that the on/off and the heating rate of the heating chip can be controlled by the external control circuit.
Preferably, referring to fig. 2, in order to further increase the temperature rise rate during the annealing process, a first auxiliary heating member 40 is disposed inside the top of the closed chamber 10. Here, the first auxiliary heating member 40 may be a resistance wire, or a heating element such as a carbon rod. That is, the heating member 30 and the first auxiliary heating member 40 can transfer heat from both the upper and lower directions of the memory chip 20, thereby achieving rapid temperature rise.
Preferably, referring to fig. 3, in order to further increase the temperature rising rate during the annealing process, a second auxiliary heating member 50 is disposed around the outside of the closed cavity 10, where the second auxiliary heating member 50 may be a heating element such as a resistance wire or a carbon rod. Similarly, the second auxiliary heating member 50 can also rapidly increase the temperature inside the closed chamber 10.
Preferably, referring to fig. 4, in addition to the heating member 30, a first auxiliary heating member 40 disposed inside the top of the closed cavity 10 and a second auxiliary heating member 50 surrounding the memory chip 20 are further added. Similarly, the memory chip 20 is heated in a surrounding manner from three directions by the first auxiliary heating member 40, the second auxiliary heating member 50, and the heating member 30, and the temperature rise rate is further increased.
The heating member 30 may be one or more of a heating chip, a resistance wire, and a carbon rod. Alternatively, other heating elements can be used to meet the annealing requirements of the memory chip. Referring to fig. 5, in the present embodiment, the heating member 30 is a heating chip, and the heating chip includes a chip body 31, a plurality of heating units 32 disposed on the chip body 31 and working independently, and a plurality of temperature sensors 33 disposed on the chip body 31. It can be understood that the chip body 31 is electrically connected to the substrate 12 enclosing the cavity, wherein each heating unit 32 can be directly controlled and heated by an external control circuit, and each temperature sensor 33 feeds back the temperature signal of the control area to the external control circuit, so that the external control circuit adjusts the temperature of each heating unit 32. Preferably, since each heating unit 32 can work independently, the memory chip can be annealed by regions, that is, the overall annealing and the local region annealing can be realized. Preferably, the heating units 32 are disposed on the chip body 31 in parallel and spaced apart. Of course, the heating units 32 are distributed in an array on the chip body 31. And, preferably, the temperature sensors 33 are arranged in an array on the chip body 31. Of course, the arrangement of the temperature sensors 33 may be different according to actual requirements, and is not described here.
Example two
The difference from the first embodiment is that the number of the memory chips 20 is at least two, and the number of the heating members 30 is at least one. Preferably, referring to fig. 6, the number of the memory chips 20 is two, and the number of the heating members 30 is one, in which case, the first memory chip 20 is placed inside the bottom of the closed cavity 10, the heating members 30 are further disposed on the memory chips 20, and finally, the second memory chip 20 is placed on the heating members 30 to form an alternate stacked structure. Or, when the number of the memory chips 20 is greater than two, the number of the heating members 30 is the same as that of the memory chips 20, or is one less than that of the memory chips 20, so that the memory chips 20 and the heating members 30 are alternately stacked in the closed cavity 10 from bottom to top.
EXAMPLE III
Referring to fig. 7, the difference from the first embodiment is that the memory chip 20 is disposed inside the bottom of the enclosed cavity 10, and the heating element 30 is disposed inside the top of the enclosed cavity 10. Similarly, the heating member 30 disposed inside the top of the closed cavity 10 can also heat-anneal the memory chip 20.
Example four
Referring to fig. 8, the difference from the first embodiment is that the memory chip 20 is disposed inside the bottom of the enclosed cavity 10, and the heating member 30 is disposed around the outside of the memory chip 20. Similarly, the heating member 30 disposed around the memory chip 20 can also heat and anneal the memory chip 20.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A memory, characterized by: the device comprises a closed cavity, a plurality of memory chips arranged in the closed cavity and a plurality of heating elements arranged in the closed cavity and used for providing annealing heat sources for the memory chips.
2. The memory of claim 1, wherein: the storage chip with the quantity of heating member is one, the storage chip with the heating member top-down stacks to be located in the closed cavity.
3. The memory of claim 2, wherein: the number of the memory chips is at least two, the number of the heating elements is at least one, and the memory chips and the heating elements are sequentially and alternately stacked in the closed cavity from bottom to top.
4. The memory of claim 1, wherein: the storage chip is arranged on the inner side of the bottom of the closed cavity, and the heating element is arranged on the inner side of the top of the closed cavity.
5. The memory of claim 1, wherein: the storage chip is arranged on the inner side of the bottom of the closed cavity, and the heating element is arranged on the outer side of the storage chip in a surrounding mode.
6. A memory according to claim 2 or 3, wherein: the memory still includes first auxiliary heating spare, first auxiliary heating spare is located the top inboard of closed cavity.
7. The memory of claim 6, wherein: the memory further comprises a second auxiliary heating element which is arranged around the outer side of the memory chip.
8. A memory according to claim 2 or 3, wherein: the memory further comprises a second auxiliary heating element which is arranged around the outer side of the memory chip.
9. The memory of claim 1, wherein: the heating element is one or more of a heating chip, a resistance wire and a carbon rod.
10. The memory of claim 9, wherein: the heating chip comprises a chip body, a plurality of heating units which are arranged on the chip body and work independently, and a plurality of temperature sensors arranged on the chip body.
CN201911345781.7A 2019-12-24 2019-12-24 Memory device Pending CN111026236A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911345781.7A CN111026236A (en) 2019-12-24 2019-12-24 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911345781.7A CN111026236A (en) 2019-12-24 2019-12-24 Memory device

Publications (1)

Publication Number Publication Date
CN111026236A true CN111026236A (en) 2020-04-17

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009037670A (en) * 2007-07-31 2009-02-19 Toshiba Corp Flash memory
CN101924069A (en) * 2010-05-13 2010-12-22 中国科学院上海微系统与信息技术研究所 Preparation method of high-peed and high-density three-dimensional resistance conversion storage structure
US9275744B1 (en) * 2015-01-29 2016-03-01 International Business Machines Corporation Method of restoring a flash memory in an integrated circuit chip package by addition of heat and an electric field
US9761290B1 (en) * 2016-08-25 2017-09-12 Sandisk Technologies Llc Overheat prevention for annealing non-volatile memory
CN210983152U (en) * 2019-12-24 2020-07-10 深圳市国微电子有限公司 Memory device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009037670A (en) * 2007-07-31 2009-02-19 Toshiba Corp Flash memory
CN101924069A (en) * 2010-05-13 2010-12-22 中国科学院上海微系统与信息技术研究所 Preparation method of high-peed and high-density three-dimensional resistance conversion storage structure
US9275744B1 (en) * 2015-01-29 2016-03-01 International Business Machines Corporation Method of restoring a flash memory in an integrated circuit chip package by addition of heat and an electric field
US9761290B1 (en) * 2016-08-25 2017-09-12 Sandisk Technologies Llc Overheat prevention for annealing non-volatile memory
CN210983152U (en) * 2019-12-24 2020-07-10 深圳市国微电子有限公司 Memory device

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