CN111010237A

CN111010237A - Geometric constellation shaping for optical data transmission

Info

Publication number: CN111010237A
Application number: CN201910950023.1A
Authority: CN
Inventors: L·施马伦
Original assignee: Nokia Solutions and Networks Oy
Current assignee: Nokia Solutions and Networks Oy
Priority date: 2018-10-08
Filing date: 2019-10-08
Publication date: 2020-04-14
Anticipated expiration: 2039-10-08
Also published as: EP3637324A1; CN111010237B; US20200112777A1; US10834485B2

Abstract

The present application relates to geometric constellation shaping for optical data transmission. An optical transfer system is configured to use one or more Artificial Neural Networks (ANNs) for geometric constellation shaping, determining constellation symbols to be transmitted, and/or determining transmitted bit words or codewords. In some embodiments, such geometric constellation shaping may be directed to finding a constellation that can provide desired performance for a given optical channel between a transmitter and a receiver of the optical transport system. In an example embodiment, an ANN used in the optical transmission system has a plurality of bit-level processing portions connected to a symbol-level processing portion in a manner that enables bit-wise processing (e.g., allocation or recovery) of constellation point labels. Adjusting configuration parameters of the ANN during training mode can be used to find better geometrical arrangements (and/or better labels) of the constellation points that can then be used during payload mode.

Description

Geometric constellation shaping for optical data transmission

Technical Field

Various example embodiments relate to an optical communication apparatus and, more particularly, but not exclusively, to methods and apparatus that may be used for geometric constellation shaping in optical data transfer systems.

Background

This section introduces aspects that may help to better understand the present disclosure. Accordingly, the statements in this section are to be read in this light and are not to be construed as admissions of what is in the prior art or what is not in the prior art.

An Artificial Neural Network (ANN) may implement an information processing paradigm developed based on certain characteristics of the biological nervous system, such as the brain. An example processing circuit, device, or system for this information processing paradigm may be constructed using multiple interconnected processing elements (PEs; sometimes also referred to as ANN nodes or artificial neurons) designed and configured to function together to solve a specific problem. In some ANN's, the number of such PEs may be relatively large. Because some such ANN's may learn by example, such ANN's may be trained for specific applications such as pattern recognition, data classification, parameter field optimization, and the like. The corresponding learning process typically involves iterative adjustment of synaptic connections between different artificial neurons and/or decisions in the neuron core.

In some data transmission systems, end-to-end (e.g., data source to data sink) signaling may be difficult to describe with tractable mathematical models. In such systems, conventional system designs in which the signal processing chain has multiple independent processing blocks, each performing well-defined and isolated functions (e.g., coding, modulation, equalization, etc.), may result in sub-optimal and/or undesirable performance. For this reason, ANN-based data transfer system design is considered an alternative.

Disclosure of Invention

Various embodiments of an optical data transfer system configured to use one or more Artificial Neural Networks (ANN) for geometric constellation shaping, determining constellation symbols to be transmitted, and/or determining transmitted bit words or codewords are disclosed herein. In some embodiments, such geometric constellation shaping may be directed to finding a constellation that may provide desired performance for a given optical channel between a transmitter and a receiver of an optical data transfer system. In an example embodiment, an ANN for use in an optical data transmission system has a plurality of bit-level processing portions connected to a symbol-level processing portion in a manner that enables bit-wise processing (e.g., allocation or recovery) of constellation point labels. Adjusting configuration parameters of the ANN during the training mode of operation may be used to find a better geometric arrangement of constellation points and/or better label constellation points that may then be used during the payload mode of operation.

In some embodiments, the ANN configuration parameters may be used to implement bypassing of the ANN during the payload mode of operation. For example, the look-up table may be loaded with constellation data derived from the ANN configuration parameters and used to replicate the output of the transmitter ANN. The demapping circuitry may be loaded with a decision graph derived from the ANN configuration parameters and used to replicate the output of the receiver ANN.

Various embodiments may be advantageously used, for example, to handle optical data transfers for optical channels that cannot be satisfactorily handled by conventional signal processing chains employing multiple independent processing blocks, each performing well-defined and isolated functions.

According to one embodiment, there is provided an apparatus comprising: an optical data transmitter, the optical data transmitter comprising: an optical modulator; one or more electrical drivers connected to operate the optical modulator to modulate an optical carrier to carry a stream of digital symbols; and a digital signal processor connected to control one or more electrical drivers in response to input data; and wherein the digital signal processor is configured to use the artificial neural network to determine values of digital symbols corresponding to values of input bit words applied to a plurality of inputs of the artificial neural network, each of the inputs being configured to carry a respective bit of the input bit word to a different respective portion of the artificial neural network, each of the portions being configured to be responsive to a respective one of the inputs.

According to another embodiment, there is provided an apparatus comprising: a correlated optical data receiver including an opto-electric converter for a modulated optical carrier, a plurality of analog-to-digital converters, and a digital signal processor, the analog-to-digital converters configured to output a digitized stream of measurements of the modulated optical carrier performed by the opto-electric converter; and wherein the digital signal processor is electrically connected to process the digitized stream using an artificial neural network configured to generate, in response to the digitized stream, a stream of output bit words for a plurality of outputs, each of the outputs configured to carry a respective bit of an output bit word generated by a different respective portion of the artificial neural network, each of the different respective portions connected to control a respective one of the outputs.

Drawings

Other aspects, features, and benefits of the various disclosed embodiments will become more fully apparent from the following detailed description and the accompanying drawings, by way of example, in which:

FIG. 1 shows a block diagram of an optical communication system according to an embodiment;

FIG. 2 shows a block diagram of a Processing Element (PE) that may be used in the optical communication system of FIG. 1, in accordance with an embodiment;

FIG. 3 shows a block diagram of another PE that may be used in the optical communication system of FIG. 1, in accordance with an embodiment;

FIG. 4 shows a block diagram of a set of PEs that may be used in the optical communication system of FIG. 1, in accordance with an embodiment;

FIG. 5 shows a block diagram of digital circuitry that may be used in a transmitter of the optical communication system of FIG. 1, in accordance with an embodiment;

FIG. 6 shows a block diagram of an Artificial Neural Network (ANN) that may be used in the digital circuit of FIG. 5, in accordance with an embodiment;

FIG. 7 shows a block diagram of a digital circuit that may be used in a receiver of the optical communication system of FIG. 1, in accordance with an embodiment;

FIG. 8 shows a block diagram of an ANN that may be used in the digital circuit of FIG. 7, in accordance with an embodiment;

fig. 9A-9B illustrate circuit modifications that may be used to implement any or all of the ANN used in the optical communication system of fig. 1, according to an embodiment;

FIG. 10 shows a flow diagram of a communication method that may be used in the optical communication system of FIG. 1 during a training mode, according to an embodiment;

FIG. 11 shows a schematic representation of a mathematical model of an optical link that may be used in the communication method of FIG. 10, in accordance with an embodiment;

fig. 12 graphically shows an example constellation that may be generated using the communication method of fig. 10, in accordance with an embodiment; and is

Fig. 13A-13D graphically show an example set of decision diagrams that may be generated using the communication method of fig. 10, according to an embodiment.

Detailed Description

Some embodiments may benefit from some of the features disclosed in the following international patent applications: PCT/EP2018/065422, PCT/EP2018/062479, PCT/EP2018/059994, PCT/EP2017/076964, and PCT/EP 2017/076965. All of these international patent applications are incorporated herein by reference in their entirety.

Fig. 1 shows a block diagram of a related optical communication system 100, according to an embodiment. The system 100 has an optical transmitter 110 and an associated optical receiver 190 coupled to each other by an optical communication link 140. The transmitter 110 and the receiver 190 may also be connected to each other by means of a control link 180, which may be used by the receiver and/or the transmitter, for example, to send service messages and/or control signals. In an example embodiment, the control link 180 may be implemented using the control plane of the system 100 and/or via an internet connection. The control link 180 may be used, for example, for ANN training purposes and/or to enable the transmitter 110 and receiver 190 to operate in a cooperative manner.

In an example embodiment, the system 100 may operate in a payload mode and a training mode.

In the training mode, the system 100 performs, in particular geometric constellation shaping, using pilot data sequences that are "known" to both the transmitter 110 and the receiver 190, e.g., as described below with reference to fig. 10-13. In an example embodiment, such constellation shaping may include, but is not limited to, the following steps: (i) selecting and/or changing the size of the constellation; (ii) changing the position of one or more constellation points on the IQ plane; (iii) changing a respective binary label (e.g., bit word) of one or more constellation points; and (iv) using a set of predetermined criteria to drive the changes made at steps (ii) and (iii). An example result after completion of the training mode operation may be a fixed constellation, where each constellation point has a respective fixed position on the IQ plane and a respective fixed binary label (e.g., a bit word of a selected length) assigned to each constellation point (see, e.g., fig. 12). The fixed binary label is a bit word encoded by a constellation point. This fixed constellation may then be used for data transmission during the payload mode.

In payload mode, transmittingThe processor 110 receives the digital electrical input stream 102 of payload data and applies it to a Digital Signal Processor (DSP) 112. DSP 112 processes input data stream 102 to generate digital signal 114₁To 114₄. In an example embodiment, the DSP 112 may perform, among other things, one or more of the following: (i) demultiplexing the input stream 102 into two sub-streams, each intended for optical transmission using a respective one of orthogonal (e.g., X and Y) polarizations of the optical output signal 130; (ii) encoding each of the sub-streams using a suitable Forward Error Correction (FEC) code, e.g., to achieve error correction at receiver 190; and (iii) converting each of the two resulting substreams into a corresponding sequence of constellation symbols of a fixed constellation determined during the training mode. In each signaling interval (also referred to as a symbol period or time slot), the signal 114₁And 114₂Carry digital values representing the (I) and quadrature (Q) components, respectively, of the corresponding constellation symbols intended for emission using the first (e.g., X) polarization of the light. Signal 114₃And 114₄Similarly carrying digital values representing the I and Q components, respectively, of the corresponding constellation symbol intended for emission using the second (e.g., Y) polarization of the light.

An E/O converter 116 (also sometimes referred to as a front-end or front-end circuit) of the transmitter 110 is used to convert the digital signal 114₁To 114₄Into a corresponding modulated optical output signal 130. More specifically, as is known in the art, the drive circuit 118₁And 118₂Will digital signal 114₁And 114₂Conversion into electrical analog drive signals I for corresponding signalling intervals respectively_XAnd Q_X. The drive signal I is then used in a conventional manner_XAnd Q_XTo drive the I-Q modulator 124_X. In response to a drive signal I_XAnd Q_XI-Q modulator 124_XX-polarized light beam 122 to modulate light supplied by laser source 120 indicated in FIG. 1_XThereby producing a modulated optical signal 126_X。

Drive circuit 118₃And 118₄Similarly, the digital signal 114₃And 114₄Transformation of componentsElectric analog drive signal I for corresponding signaling intervals_YAnd Q_Y. In response to a drive signal I_YAnd Q_YI-Q modulator 124_YY-polarized light beam 122 to modulate light supplied by laser source 120 indicated in FIG. 1_YThereby producing a modulated optical signal 126_Y. The polarization beam combiner 128 is used to combine the modulated optical signals 126_XAnd 126_YThereby generating an optical output signal 130. The optical output signal 130 is then applied to an optical communication link 140.

In an example embodiment, the drive circuit 118 may include a digital-to-analog converter (DAC, not explicitly shown in fig. 1).

The optical communication link 140 is illustratively shown as an amplified optical link having a plurality of optical amplifiers 144 configured to amplify optical signals conveyed through the optical fibers of the link, e.g., to cancel signal attenuation in the fiber spans thereof. It should be noted that an optical communication link 140 having only one optical amplifier 144, or even no optical amplifier, may similarly be used in alternative embodiments. After propagating through optical communication link 140, optical signal 130 becomes optical signal 130', which is applied to receiver 190. Optical signal 130' may differ from optical signal 130 in that optical communication link 140 typically adds noise and applies various signal distortions, e.g., due to optical amplifiers and/or due to, e.g., chromatic dispersion, polarization rotation, polarization mode dispersion, and/or nonlinear optical effects in the optical fiber.

The receiver 190 has a front end circuit 172 that includes an optical-to-electrical (O/E) converter 160, an analog-to-digital converter (ADC)166₁To 166₄And an Optical Local Oscillator (OLO) source 156. The O/E converter 160 has (i) two input ports labeled S and R and (ii) four output ports labeled 1 through 4. The input port S receives the optical signal 130' from the optical communication link 140. Input port R receives an OLO signal 158 generated by OLO source 156. The OLO signal 158 has an optical carrier frequency (wavelength) sufficiently close to the optical carrier frequency of the signal 130' to enable correlated (e.g., intra-differenced) detection of the latter signal. The OLO signal 158 may be generated, for example, using a relatively stable tunable laser that may be tunedThe output wavelength (frequency) of the optical device is substantially the same as the carrier wavelength (frequency) of the optical signal 130'.

In an example embodiment, O/E converter 160 is used to mix input signal 130' and OLO signal 158 to generate eight different mixed (e.g., by interference) optical signals (not explicitly shown in fig. 1), such as eight such mixed signals for differential I/Q detection of two polarizations. The O/E converter 160 then uses one or more photodetectors (e.g., one or more photodiodes, not explicitly shown in fig. 1) to convert the set of mixed optical signals into four electrical signals 162₁To 162₄Indicating the complex values corresponding to the two orthogonal polarization components of signal 130'. For example, electrical signal 162₁And 162₂May be an approximately analog I signal and an approximately analog Q signal, respectively, that correspond to a first (e.g., horizontal, h) polarization component of signal 130'. Electrical signal 162₃And 162₄May similarly be an approximately analog I signal and an approximately analog Q signal, respectively, corresponding to a second (e.g., vertical, v) polarization component of signal 130'. It should be noted that the orientation of the h and v polarization axes at the receiver 190 may or may not coincide with the orientation of the X and Y polarization axes at the transmitter 110.

In example embodiments, the signal mixing functionality of the O/E converter 160 may be implemented using one or more optical mixtures.

The electrical signal 162 generated by the O/E converter 160₁To 162₄At ADC166₁To 166₄Is converted into digital form. Optionally, electrical signal 162₁To 162₄Each of which may be amplified in a corresponding electrical amplifier (e.g., a transimpedance amplifier, TIA; not explicitly shown in fig. 1) before the resulting signals are converted to digital form. By ADC166₁To 166₄Generated digital signal 168₁To 168₄And then processed by the DSP 170 to recover the data applied to the original input data stream 102 of the transmitter 110. In an example embodiment, DSP 170 may perform, among other things, one or more of the following: (i) electronic polarization demultiplexing; (ii) signal equalization and/or dispersion compensation; (iii) mapping signal samples to trainingOn a fixed constellation determined during training mode; and (iv) error correction based on the FEC coding applied at DSP 112.

In an example embodiment, each of DSP 112 and DSP 170 includes a respective ANN. Example embodiments of the DSP 112 and DSP 170 and coherent signal processing methods that may be implemented therein are described in more detail below with reference to FIGS. 2-13.

As used herein, the term "ANN" refers to a distributed and typically nonlinear trainable circuit or machine that is constructed using multiple Processing Elements (PEs). Also, the ANN may be dynamically adaptive. Each PE has connections to one or more other PEs. The plurality of connections between the PEs define the topology of the ANN. In some topologies, the PE may polymerize into the layer. Different layers may have different types of PEs configured to perform different kinds of respective transforms on their inputs. A signal may travel from a first PE layer (often referred to as an input layer) to a last PE layer (often referred to as an output layer). In some topologies, the ANN may have one or more intermediate PE layers (commonly referred to as hidden layers) positioned between the input PE layer and the output PE layer. An example PE may scale, sum, and bias incoming signals, and use an activation function to generate an output signal that is a static non-linear function of the biased sum. The resulting PE output may become any of the outputs of the ANN, or be sent to one or more other PEs over corresponding connections. The respective weights and/or biases applied by the individual PEs may change during the training mode and are typically fixed (constant) during the payload mode.

For example, some additional features and characteristics that may be relevant to the Definition of the term "ANN" are reviewed in e.grurson (e.guresen), g.kayakutlu, "Definition of Artificial Neural Networks and comparison with Other Networks (Definition of Artificial Neural Networks with Computer to Other Networks)" Procedia Computer Science,3(2011), page 426-433, which is incorporated herein by reference in its entirety.

In an example embodiment, the ANN may be implemented using one or more of the following: (i) a software program executed by a general-purpose or special-purpose electronic processor; (ii) a Field Programmable Gate Array (FPGA) device; and (iii) an Application Specific Integrated Circuit (ASIC). Some ANN's may be implemented using an optical processor, for example, as described in U.S. patent No. 7,512,573, which is incorporated herein by reference in its entirety.

In an example embodiment, the PE may be implemented using one or more of the following circuits: (i) a multiplier circuit; (ii) an adder; (iii) a comparator; and (iv) a non-volatile memory cell.

FIG. 2 schematically illustrates a block diagram of a PE200 that may be used in DSP 112 and/or DSP 170, according to an embodiment. PE200 is a multiple-input/single-output (MISO) device having N inputs (labeled x)₁,x₂,…,x_N) And a single output (labeled y), where N is a positive integer greater than one. Input x₁,x₂,…,x_NEach applied to a respective input port of the PE200 and may deliver real or integer numbers. Collectively, input x₁,x₂,…,x_NCan be expressed as a column vector x ═ x₁,x₂,…,x_N)^TWhere superscript T denotes transpose.

The configuration of the PE200 is determined by a weight vector w, a bias b, and a scalar function f (-). Weight vector w ═ w₁,w₂,…,w_N)^TWith N scalar components. In operation, an instance of PE200 may calculate output y according to equation (1):

y＝f(w^Tx+b) (1)

wherein w^Tx represents a vector w^TAnd the dot product of x. The scalar function f (-) depends on the embodiment and may be, for example, one of:

f(z)＝max(0,z) (2a)

f(z)＝max(γz,z) (2b)

f(z)＝1/(1+exp(-z)) (2c)

f(z)＝tanh(z) (2d)

wherein 0< γ < 1. The functions defined by equations (2a) through (2e) are sometimes also referred to as rectification linear unit (ReLU) functions, leakage rectification linear unit (lreol) functions, sigmoid functions, hyperbolic tangent functions, and goodman functions, respectively.

In a typical configuration of the PE200, multiple copies of the output y may be generated and applied to respective input ports of corresponding different PEs connected to the PE 200.

FIG. 3 schematically illustrates a block diagram of a PE 300, which may be used in the DSP 112, according to an embodiment. PE 300 is substantially similar to PE200, except that PE 300 calculates output y according to equation (3):

y＝α(w^Tx+b) (3)

where α is a scaling variable selected such that the average power of the output y is limited to some fixed value PE 300 may sometimes be referred to as a "normalization node".

In some embodiments, the scaling variable α may not be used as a separate PE configuration parameter, but instead may be incorporated into the weight vector w and the bias b by redefining those quantities as α w and α b, respectively.

FIG. 4 schematically illustrates a block diagram of a group 400 of PEs 410 that may be used in DSP 170, according to an embodiment. In general, a group 400 may have G PEs 410, where G is a positive integer greater than one. For purposes of illustration and without any implied limitation, fig. 4 shows group 400, where G ═ 2. The corresponding two PEs 410 are labeled 410 in FIG. 4, respectively₁And 410₂. The individual PEs 410 may sometimes be referred to as "softmax nodes".

Each PE410_i(where i ═ 1,2, …, G) has N inputs and one output. To PE410_iCan be represented as a column vector x_i＝(x_i,1,x_i,2,…,x_i,N)^T。PE 410_iBy a weight vector w_i＝(w_i,1,w_i,2,…,w_i,N)^TAnd deviation b_iTo be determined.

In operation, PE410_iThe output y may be calculated in two steps_i. For example, in the first stepDuring the procedure, PE410_iThe intermediate result Y can be calculated according to equation (4)_i：

Y_i＝w_i ^Tx_i+b_i(4)

This intermediate result Y_iWhich may then be shared with other PEs 410 of the same group 400, such as by way of connections 420. During the second step, the PE410_iShared intermediate result Y that may use the group 400_iTo calculate the output y according to equation (5)_i：

Fig. 5 shows a block diagram of digital circuitry 500 that may be used in DSP 112 of transmitter 110 (fig. 1), according to an embodiment. More specifically, the DSP 112 may use two instances (nominal copies) of the circuit 500, e.g., one instance per polarization. In operation, the circuit 500 converts an input bit stream 502 into a digital signal 114_aAnd 114_b. For a first example of the circuit 500 in the DSP 112, a is 1 and b is 2. For a second example of the circuit 500 in the DSP 112, a is 3 and b is 4. During the training mode, the input bit stream 502 carries a pilot data sequence. During the payload mode, the input bitstream 502 carries payload data and may be generated, for example, by demultiplexing the input stream 102 (fig. 1).

As is known in the pertinent art, the circuit 500 includes an FEC encoder 510 that uses an appropriate FEC code to add redundancy to the input bitstream 502 to convert the input bitstream into an FEC encoded bitstream 512. A serial-to-parallel (S/P) converter 520 then converts the bit stream 512 into a plurality of bit streams 522₁To 522_mWherein m is a positive integer greater than one. In an example embodiment, the number m relates to the constellation size and represents the length of the binary label assigned to the constellation point. For example, the number M and the number M of constellation points in the used constellation may be associated as M-2^m。

In some embodiments, the S/P converter 520 may be a demultiplexer. In some other embodiments, S/P converter 520 may be configured to implement bitstream 502 to bitstream 522₁To 522_mMore complex linear transformations. Such more complex transformations may include, for example, data interleaving, suitable linear matrix operations, and so forth.

The circuit 500 further includes an ANN 530 and a look-up table (LUT)560, each of which is coupled to receive the bit stream 522₁To 522_mThe corresponding copy of (c). The state of switch 540 determines whether the output of ANN 530 or the output of LUT560 is used to generate digital signal 114_aAnd 114_b. In an example embodiment, the electronic controller 560 is configured to use the control signal 554 to cause the switch 540 to: (i) the output of the ANN 530 is used during the training mode and (ii) the output of the LUT560 is used during the payload mode.

In some embodiments, the LUT560 may not be used, and as such, the LUT560 may be disabled, disconnected, or removed from the circuit 500. In such embodiments, the output of the ANN 530 is used to generate the digital signal 114 in the training and payload modes_aAnd 114_b. It should be noted, however, that controller 550 may use control signal 552 to change PE configuration parameters of ANN 530 during the training mode, e.g., as described with reference to fig. 10. In contrast, the PE configuration parameters of the ANN 530 remain constant during payload mode.

In each time slot, the ANN 530 uses the bitstream 522₁To 522_mTo generate an output symbol having an I component derived from the digital output signal 532₁Is carried, and the Q component of the output symbol is represented by the digital output signal 532₂Is carried. When the PE configuration parameters of ANN 530 are constant, the conversion of the input bit words into I and Q values performed by the ANN is deterministic. Namely: through bit stream 522₁To 522_mReceiving the same input bit word to generate for digital output signal 532₁And 532₂The same (I, Q) pair. The latter property of the ANN 530 may be advantageously used to reduce the computational load of the DSP 112 using the LUT560 instead of the ANN 530.

For example, upon completion of the training mode, controller 550 may use

control signals

534 and 556 to pass through the respective (I, Q) pair saved therein for each different input bit wordThe LUT560 is loaded. Then, during payload mode, the saved (I, Q) pairs may be read out of LUT560 and applied to output 562₁And 562₂To reproduce the response of the ANN 530 to the same input bit words. Using LUT560 instead of ANN 530 may reduce the computational load in circuit 500, for example, because LUTs are generally simpler circuits than ANNs.

FIG. 6 shows a block diagram of an ANN 530, according to an embodiment. Also shown in FIG. 6 is a digital signal 522₁To 522_mAnd 532₁To 532₂To better illustrate the relationship between the circuits of fig. 5 and 6.

ANN 530 includes a one-hot vector encoder 610₁To 610_mEach configured to receive a digital signal 522₁To 522_mA respective one of the. In operation, encoder 610_i(where i-1, 2, …, m) produces a digital output signal 612_aiAnd 612_bi. More specifically, encoder 610 responds to a binary "one" applied to the output signal via a corresponding input 522_iOutput for signal 612_aiAnd for signal 612_biA binary "one". Encoder 610 responds to binary "zeros" applied to the output signal via corresponding input 522_iOutput for signal 612_aiAnd for signal 612_biIs binary "zero".

The ANN 530 further includes an input layer 616, a bit-level section 640, a symbol-level section 650, and an output layer 660.

Input layer 616 includes multiple PEs 620, each pair of PEs coupled to encoder 610₁To 610_mA respective one of the. The output of each PE 620 is replicated an appropriate number of times and the resulting replicas are applied to the PEs 200 of the corresponding portion 630 of the segment 640. In an example embodiment, each PE 620 may be implemented using a suitable embodiment of PE200 (fig. 2) or PE 300 (fig. 3). In some embodiments, each PE 620 may be configured to only generate multiple copies of its inputs and apply each copy to a respective one of its outputs.

Each portion 630 may have two or more layers that fully connect the PEs 200. As used herein, the term "fully connected" should be interpreted to mean that the output of a PE200 of one PE layer of the portion 630 is received by each PE200 of the next PE layer of the portion 630. For purposes of illustration and without any implied limitation, fig. 6 shows only two PE layers in each portion 630. However, one of ordinary skill in the art will readily understand how to connect additional PE layers therein.

The different portions 630 of the segment 640 are not directly connected to each other. For example, portion 630₁Does not apply any of its outputs to portion 630₂Or 630_mAny of the PEs 200. Portion 630₂Does not apply any of its outputs to portion 630₁Or 630_mAny of the PEs 200, etc. Thus, portion 630₁To 630_mIs only responsive to the digital signal 522₁To 522_mAnd not in response to any other of those digital signals.

The segment 650 may include two or more layers of the fully-connected PE 200. The PEs 200 of the first PE layer of the segment 650 are connected to slave portion 630₁To 630_mEach PE200 of the last PE layer receives the output. For purposes of illustration and without any implied limitation, fig. 6 shows only two PE layers in each section 650. However, one of ordinary skill in the art will readily understand how to connect additional PE layers therein.

In some embodiments, the segment 650 may have a single layer of the PE 200.

Output layer 660 includes two PEs 300, each connected to receive output from each PE200 of the last PE layer of section 650. The output of one PE 300 of output layer 660 is digital signal 532₁(see also fig. 5). The output of another PE 300 of output layer 660 is digital signal 532₂(see also fig. 5).

One of ordinary skill in the art will appreciate that the embodiment of the ANN 530 shown in fig. 6 is designed to process two-dimensional constellation symbols (corresponding to two dimensions on a complex plane), such as represented by I and Q components. However, possible embodiments of the ANN that may be used in the system 100 are not limited thereto. Given the description provided, one of ordinary skill in the art will be able to make and use other embodiments in which a corresponding ANN is configured to handle constellation symbols having dimensions other than two dimensions.

As used herein, the term "constellation symbol" should be understood to encompass constellation symbols of one-dimensional constellations and multidimensional constellations. An example one-dimensional constellation enables a single constellation symbol to be transmitted in a single signaling interval (time slot) via a single dimension of the carrier. In contrast, a multi-dimensional constellation enables a single constellation symbol to be transmitted using multiple signaling intervals and/or multiple dimensions of carriers and/or links. For example, a d-dimensional constellation may be constructed using d different one-dimensional constellations or d copies of the same one-dimensional constellation. Examples of possible dimensions that may be used for these purposes include, but are not limited to, time, quadrature, polarization, spatial mode, and carrier frequency.

For example, the embodiments of fig. 5-6 may be modified to be able to process four-dimensional constellation symbols, which may then be transmitted using two orthogonal (e.g., X and Y) polarizations of the carrier. These modifications may include, for example, the following.

The S/P converter 520 may be modified to convert the bitstream 512 into 2m bitstreams 522₁To 5222_m。

The ANN 530 may be modified to generate four digital output signals, of which digital output signal 532₁To 532₂The values for the I and Q components, respectively, for the X polarization are provided, and the two additional digital output signals provide the values for the I and Q components, respectively, for the Y polarization.

LUT560 may be modified to have 2m inputs and four outputs.

Switch 540 may be modified to generate digital signal 114 by selecting either the four outputs of modified ANN 530 or the four outputs of modified LUT560₁To 114₄(see also FIG. 1).

FIG. 7 shows a block diagram of digital circuitry 700 that may be used in DSP 170 of receiver 190 (FIG. 1) according to an embodiment. In operation, the circuit 700 converts the digital signal 168₁To 168₄(fig. 1) into an output bitstream 502 (see also fig.)5)。

The circuit 700 includes a receiver processing circuit 710 configured to convert the digital signal 168₁To 168₄Conversion to digital signal 712₁To 712₄. The signal processing implemented in circuit 710 may include some of the signal processing operations performed in the DSP chain of a conventional correlated optical receiver prior to constellation demapping. Such signal processing operations may include, for example, one or more of the following: (i) reduction of signal distortion caused by the front-end circuitry 172 (fig. 1); (ii) electronic polarization rotation and/or demultiplexing; (iii) recovering a clock; (iv) OLO phase and/or frequency offset correction, and the like.

The circuit 700 further comprises an ANN 720 and a demapping circuit 770, each of which is coupled to receive the digital signal 712₁To 712₄The corresponding copy of (c). The state of switch 730 determines whether to apply the output of ANN 720 or the output of demapping circuit 770 to parallel-to-serial (P/S) converter 740. In an example embodiment, the electronic controller 760 is configured to use the control signal 764 to cause the switch 730 to pass: (i) the output of the ANN 720 during the training mode, and (ii) the output of the demapping circuitry 770 during the payload mode.

In some embodiments, demapping circuit 770 may not be used, and as such, demapping circuit may be disabled, disconnected, or removed from circuit 700. In such embodiments, the output of the ANN 720 is applied to the P/S converter 740 in training and payload modes. It should be noted, however, that the controller 760 may use the control signal 762 to change PE configuration parameters of the ANN 720 during the training mode, e.g., as described with reference to fig. 10. In contrast, the PE configuration parameters of the ANN 720 remain constant during payload mode.

In each time slot, the ANN 720 uses the incoming digital signals (712) separately₁，712₂) And (712)₃，712₄) Two corresponding (I, Q) pairs are provided to produce two corresponding bit words, each having m bits. M bits of the first of the two bit words are output by digital output signal 722₁To 722_mIs carried. M bits of the second of the two bit words are provided by digital output signal 722_m+1To 722_2mIs carried.

When the PE configuration parameters of ANN 720 are constant, the conversion of each of the input (I, Q) pairs performed by the ANN may alternatively be represented as a mapping operation configured to use a respective plurality of decision graphs, each decision graph corresponding to a respective bit of the output bit word. Each of the decision graphs divides the I-Q plane into two portions, the first portion representing a binary "one" and the second portion representing a binary "zero". From an input digital signal (712)₁，712₂) Or (712)₃，712₄) The provided input (I, Q) pairs are then available as coordinates of the corresponding sample point on each of the decision graphs to convert the (I, Q) pairs into output bit words as follows. If the sample point belongs within the first portion of the graph, the corresponding bit of the output bit word is set to a binary "one". If the sample point belongs within the second portion of the graph, the corresponding bit of the output bit word is set to a binary "zero". An example plurality of decision diagrams that may be used for this purpose are shown in fig. 13A-13D.

In some embodiments, the graph-based representation of the conversion performed by the ANN 720 may be advantageously used to reduce the computational load of the DSP 170 using the demapping circuitry 770 instead of the ANN 720. For example, upon completion of the training mode, controller 760 may use

control signals

724 and 766 to: (i) generating the decision graph described above using the PE configuration parameters of the ANN 720; and (ii) loading the generated decision graph into the demapping circuitry 770. Then, during payload mode, the loaded decision graph can be used by the demapping circuit 770 to perform the processing performed by the input digital signal (712)₁，712₂) And (712)₃，712₄) The above-described conversion to input (I, Q) pairs of the loaded decision graph is provided to reproduce the response of the ANN 720 to the same input (I, Q) pairs. The resulting bit words are then used to generate a digital output signal 772₁To 772_2m. In each time slot, m bits of a first one of two bit words are output by digital output signal 772₁To 772_mIs carried, and m bits of the second of the two bit words are provided by digital output signal 772_m+1To 772_2mIs carried.

In some embodiments, using the demapping circuitry 770 instead of the ANN 720 may reduce the computational load in the circuitry 700, for example, because the complexity of at least some of the mapping circuitry may be lower than the complexity of the ANN 720.

Parallel-to-serial (P/S) converter 740 to serialize bit stream 732 output by switch 730₁To 732_2mThereby generating a bitstream 742. In an example embodiment, the serialization operation performed by P/S converter 740 is configured as the inverse of the deserialization operation performed by corresponding S/P converter 520 (fig. 5) located at transmitter 110 (fig. 1). Therefore, in the case where there is no error, the bit stream 742 is the same as the bit stream 512.

FEC decoder 750 is configured to apply an operational FEC code to correct errors and remove redundancy from bit stream 742, as is known in the art of coherence, to recover bit stream 502 (see also fig. 5).

Fig. 8 shows a block diagram of an ANN 800, which may be used to implement ANN 720, according to an embodiment. For purposes of illustration and without any implied limitation, the ANN 800 is shown as processing a digital signal 712₁And 712₂And generates a digital signal 722₁To 722₂. Thus, the ANN 800 may be used to process signals in a manner that is compatible with the processing implemented in the ANN 530 (see fig. 5-6). The ANN 800 may be modified in a straightforward manner, for example, as described further below, to process the digital signal 712₁To 712₄And generates a digital signal 722₁To 722_2mFor processing signals corresponding to both polarizations.

ANN 800 includes a symbol-level section 810, a bit-level section 820, and an output layer 840.

The segment 810 may include two or more layers of the fully-connected PE 200. PE200 of the first PE layer of section 810 is coupled to input digital signal 712₁And 712₂The corresponding copy of (c). The PE200 of the last PE layer of the segment 810 is coupled to apply a copy of its output to each PE200 of the first PE layer of the segment 820. For purposes of illustration and without any implied limitation, FIG. 8 shows three PE layers in section 810. However, one of ordinary skill in the art will readily understand how to in sectionsAdditional PE layers are attached or one PE layer is removed.

In some embodiments, the segment 810 may comprise a single layer of the PE 200.

Segment 820 includes portion 830₁To 830_m. The different portions 830 of the segment 820 are not directly connected to each other. For example, portion 830₁PE200 of (a) does not apply any of its outputs to portion 830₂Or 830_mAny of the PEs 200. Portion 830₂PE200 of (a) does not apply any of its outputs to portion 830₁Or 830_mAny of the PEs 200, etc.

Output layer 840 includes group 400₁To 400_mEach having two corresponding PEs 410 (i.e., G ═ 2; see also fig. 4). Group 400_jEach PE410 (where j ═ 1,2, …, m) is connected to: (i) from portion 830 of section 820_jThe PE200 of the last PE layer of (2) receives the output copy; and (ii) applying its output to arg-max circuit 850_j. In each time slot, an arg-max circuit 850_jFor: (i) comparison group 400_jThe outputs of the two PEs 410; and (ii) generated for output bitstream 722 based on the comparison_jThe binary value of (c). More specifically, if group 400_jPE410 of₁Is greater than the group of PEs 410₂(see also fig. 4), then arg-max circuit 850_jProducing a bitstream 722 for output_jIs binary "zero". Otherwise, arg-max circuit 850_jProducing a bitstream 722 for output_jA binary "one".

To be able to handle four-dimensional constellation symbols transmitted using two orthogonal (e.g., X and Y) polarizations of the carrier, the ANN 800 may be modified, for example, as follows.

The segment 810 may be modified to receive four digital signals 712₁To 712₄。

The segment 820 may be modified to have 2m portions 830.

The output layer 840 may be modified to have 2m groups 400, and the number of arg-max circuits 850 may thus be increased to 2 m.

Fig. 9A-9B illustrate circuit modifications that may be used to implement any or all of

ANNs

530, 720, and 800 according to an embodiment. More specifically, fig. 9A shows a block diagram of an ANN portion 910 that may be used in some of the above-described embodiments of the

ANN

530, 720, and 800. Fig. 9B shows a block diagram of an ANN portion 940 that may be used to replace the ANN portion 910 in some embodiments of the

ANN

530, 720, and 800.

Referring to FIG. 9A, the ANN portion 910 has two layers of PEs 200, respectively designated 920₁And 920₂. In operation, ANN portion 910 inputs vector X according to equations (6) through (7)₁Conversion to output vector X₃：

X_3,i＝f_a(W_2,i ^TX₂+b_2,i) (6)

X_2,i＝f_a(W_1,i ^TX₁+b_1,i) (7)

Wherein X_3,iIs an output vector X₃The ith component of (a); f. of_aIs the ReLU function (see also equation (2 a)); w_2,iIs for the PE layer 920₂The weight vector in the ith PE200 in (a); x₂Is composed of a PE layer 920₁A generated output vector; b_2,iIs for the PE layer 920₂The deviation in the ith PE200 in (1); x_2,iIs an output vector X₂The ith component of (a); w_1,iIs for the PE layer 920₁The weight vector in the ith PE200 in (a); b_1,iIs for the PE layer 920₁The deviation in the ith PE200 in (1); superscript T denotes transpose; 1,2, …, N; and N is a PE layer 920₁And 920₂The number of PEs 200 in each of them.

Referring to FIG. 9B, the ANN portion 940 uses the PE layer 950 instead of the PE layer 920₂. The PE layer 950 has N PEs 900, each of which is configured to operate according to equation (8):

X′_3,i＝f_a(W_2,i ^TX₂+b_2,i+X_1,i) (8)

wherein X'_3,iIs an output vector X 'produced by PE layer 950'₃The ith component of (a); and X_1,iIs an input directionQuantity X₁The ith component of (a). Therefore, the signal conversion performed by the ANN section 940 is described by equations (6) and (8). As indicated by equation (8) and the circuit structure shown in FIG. 9B, each PE900 is connected to receive except the full vector X₂Outer input vector X₁Corresponding scalar component.

In some embodiments, it may be advantageous to use one or more ANN portions 940 in the system 100, as such use may help to improve the training process of the system and/or increase the speed of convergence of the optimization algorithms used for the training process.

Fig. 10 shows a flow diagram of a communication method 1000 that may be used in system 100 during a training mode, according to an embodiment. For purposes of illustration and without any implied limitation, the description of some steps of method 1000 may also refer to the specific examples shown in fig. 11-13.

At step 1002 of the method 1000, the system 100 is operated to transmit the calibration signal 130 from the transmitter 110 to the receiver 190 (see also fig. 1). In an example embodiment, the calibration signal 130 may carry a pilot data sequence specifically designed for ANN training purposes, e.g., as known in the pertinent art, where the transmitted form of the pilot data sequence is known to both the transmitter 110 and the receiver 190. Such common sense may be obtained, for example, using control link 180 (fig. 1).

At step 1004, a system controller (e.g., including

controllers

550 and 760 and/or other coherent entities corresponding to the control plane of system 100) calculates a cost function L (·) based on at least some of the above-indicated signals generated by transmitter 110 and receiver 190 during step 1002 (see, e.g., fig. 5-8).

In an example embodiment, the cost function L (-) may be constructed to achieve an approximate minimization of average cross entropy between m parallel autoencoders, each coupled by signal 522_i(FIG. 6) input and output signals 722_i(fig. 8), where i is 1,2, …, m. An example cost function L (-) suitable for this purpose is given by the following equation (9):

wherein B is_i＝{x_i,1,…,x_i,MBIs a one-hot vector encoder 610 containing a pilot data sequence used in response to step 1002_i(e.g., as described above with reference to FIG. 6) generated MB unique heat vector x_i,jThe mini batch of (1); and Z is_i＝{z_i,1,…,z_i,MBIs responsive to mini batch B_iAnd an output z produced by output layer 840 (FIG. 8)_i,jA collection of (a). In other embodiments, other suitable cost functions L (-) may be used instead.

In some embodiments, the cost function L (-) and/or PE parameter update algorithm used at step 1008 may rely on an approximate mathematical model of the link 140 (FIG. 1).

Fig. 11 shows a schematic representation of an example mathematical model 1100 of an optical link 140 that may be used in the method 1000, according to an embodiment. Model 1100 corresponds to an optical link, and is characterized by zero dispersion and nonlinearity. As an example, the value of nonlinearity, can be 1.27W/km. Model 1100 represents optical link 140 as K series-connected stages S₁,S₂,…,S_K. Each of these stages represents a section of optical fiber having a length L/K, where L is the total length of optical fiber in link 140. Of course, other possible optical links 140 may have chromatic dispersion and/or nonlinear optical effects, and thus may be modeled in different ways.

Each stage S_kThe effects on the optical signal applied to it are: (i) applying a phase flip, the magnitude of which is proportional to the intensity of the optical signal (the squared magnitude of the electric field); and (ii) adding gaussian noise. In FIG. 11, the slave stage S_k(where K ═ 1,2, …, K) the applied phase flip is determined by a complex exponent exp (j γ | · |)²L/K), wherein | · non-woven²Indicating the light intensity. From stage S_kThe applied Gaussian noise is denoted therein as n_k. Example values of K may be between 10 and 100.

One of ordinary skill in the art will appreciate that other mathematical models of the link 140 may also be used and will be able to select or construct an appropriate mathematical model based on the specific technical characteristics of the link 140.

At step 1006 of method 1000, the system controller uses a predefined set of one or more criteria to evaluate the cost function L (-) calculated at step 1004. If the criteria are not met, then processing of method 1000 proceeds to step 1008. If the criteria are met, then processing of method 1000 proceeds to step 1010.

Depending on the embodiment, step 1006 may include one or more of: (i) comparing the value of the cost function L (-) to one or more predetermined thresholds; (ii) comparing the change in value of the cost function L (-) corresponding to two different executions of the processing loops 1002-1008 with one or more other predetermined thresholds; and the like.

At step 1008, the system controller may use a suitable algorithm to change one or more PE configuration parameters (see, e.g., equations (1), (3), (4), and (6) through (8)). As already indicated above, this algorithm may be directed to minimizing the cost function L (·) and may rely in particular on a mathematical model of the optical link 140 (see e.g. fig. 11). After performing step 1008, processing of method 1000 returns to step 1002.

At step 1010, the system controller makes the current values of the PE configuration parameters fixed, for example, by disabling further configuration updates. These parameter values may also be saved in non-volatile memory for future use, for example, during payload mode.

Steps

1012 and 1014 may be optional and are performed in embodiments that use LUT560 during payload mode.

At step 1012, the controller 550 uses the PE configuration parameters of step 1010 to generate a fixed constellation. For example, controller 550 may use digital signal 522₁To 522_mApplying a different set of bit words to ANN 530 and then using digital signal 532₁To 532₂To determine the I and Q values corresponding to each such bit word (see also fig. 5). The (I, Q) pairs determined in this way provide the coordinates of the different constellation points of the constellation defined by the fixed PE configuration parameters. For theEach of such constellation points is passed through a digital signal 522₁To 522_mThe corresponding input bit words applied to ANN 530 provide the corresponding binary labels.

Fig. 12 graphically shows an example constellation 1200 that can be defined at step 1012, in accordance with an embodiment. More specifically, constellation 1200 corresponds to optical link 140, where m-4 and is well described by model 1100. Also shown in fig. 12 are constellation labels for each of the sixteen constellation points of constellation 1200.

It may be noted that the relative arrangement of constellation points in constellation 1200 may be irregular, in the sense that the constellation points do not lie in a regular square or rectangular grid, as is the case for example with conventional 16-QAM constellations. Two groups of constellation points may be noted. The first group (labeled 1210) has ten constellation points, each having a relatively small amplitude. A second group, labeled 1220, has six constellation points, each having a relatively large amplitude, where the points are in a substantially linear form. The binary labels in each group are substantially quasi-gray.

These geometric properties of constellation 1200 can be qualitatively understood, for example, as follows. For relatively small signal amplitudes, the signal distortion in channel 1100 is dominated by gaussian noise. In this case, the best performance may be achieved by appropriately expanding the constellation around the origin, e.g., as in group 1210. For relatively large signal amplitudes, signal distortion in channel 1100 is dominated by nonlinear phase noise. In this case, for example as in group 1220, optimal performance may be achieved by appropriately limiting the possible phase values.

One of ordinary skill in the art will appreciate that optical channels other than channel 1100 may cause system 100 to converge on a different set of constellations having geometric properties than constellation 1200 during training.

At step 1014 of the method 1000, the results of step 1012 may be loaded into the LUT 560.

Steps

1016 and 1018 may be optional and may be performed in embodiments that use demapping circuitry 770 (fig. 7) during payload mode.

At step 1016, the controller 760 uses the PE configuration parameters of step 1010 to generate a set of decision maps corresponding to the constellation of step 1012. For example, controller 760 may generate a set of (I, Q) pairs corresponding to nodes of a relatively tight square or rectangular grid that encompasses the I-Q plane. In this case, the distance between adjacent grid lines typically determines the resolution of the resulting decision map.

For example, controller 760 may use digital signal 712₁To 712₂Applying different (I, Q) pairs corresponding to nodes of a grid to ANN 800₁And then use the digital signal 722₁To 722_mThe bit words corresponding to each such (I, Q) pair are determined (see also fig. 8). In this way, a bit value for each of the m bit positions may be determined for each (I, Q) pair. Suitable extrapolation and/or interpolation techniques may optionally be used to obtain bit values for points located between nodes of the used grid. The resulting body of data can then be converted into a decision graph in a relatively straightforward manner.

Fig. 13A-13D graphically show an example set of decision graphs 1310-1340 that can be generated at step 1016, according to an embodiment. More specifically, decision diagrams 1310 through 1340 correspond to constellation 1200 (fig. 12) and channel 1100 (fig. 11). As already indicated above, the binary label in constellation 1200 has four bits (i.e., m-4). Decision graph 1310 (FIG. 13A) corresponds to the most significant bits of the tags. Decision diagram 1320 (fig. 13B) corresponds to the next most significant bit of the tag. Decision map 1330 (FIG. 13C) corresponds to the third bit of the tag. Decision graph 1340 (FIG. 13D) corresponds to the least significant bits of the tag.

At step 1018 of the method 1000, the decision graph generated at step 1016 may be loaded into the demapping circuitry 770.

According to an example embodiment disclosed above, for example in the summary and/or with reference to any one or any combination of some or all of figures 1 to 13, there is provided an apparatus comprising: an optical data transmitter (e.g., 110, fig. 1), the optical data transmitter comprising: an optical modulator (e.g. 124, FIG. 1) connected to operate the optical modulator to modulate an optical carrier to carry a numberOne or more electrical drivers (e.g., 118, fig. 1) of a stream of word symbols (e.g., I and Q values, fig. 5) and a digital signal processor (e.g., 112, fig. 1) connected to control the one or more electrical drivers in response to input data; and wherein the digital signal processor is configured to use the artificial neural network (e.g., 530, FIG. 5) to determine a plurality of inputs (e.g., 522) corresponding to the plurality of inputs applied to the artificial neural network₁To 522_mFig. 5), each of the inputs being configured to carry a respective bit of the input bit word to a different respective portion (e.g., 630) of the artificial neural network₁To 630_mOne of the portions, fig. 6), each of the portions being configured to respond to a respective one of the inputs.

In some embodiments of the above apparatus, different ones of the respective portions are separate.

In some embodiments of any of the above apparatus, the artificial neural network further comprises a plurality of processing elements (e.g., a first layer of 650, fig. 6), wherein each of the processing elements is connected to receive a digital input from each of the respective portions (e.g., as indicated in fig. 6).

In some embodiments of any of the above apparatus, the apparatus further comprises an electronic controller (e.g., 550, fig. 5) configured to change a configuration parameter of the artificial neural network based on a training mode in which the optical data transmitter transmits the pilot data sequence over the optical fiber (e.g., 140, fig. 1).

In some embodiments of any of the above apparatus, the electronic controller is further configured to fix the configuration parameters of the artificial neural network for a payload mode in which the transmitter transmits a modulated optical carrier carrying the input data to the optical fiber.

In some embodiments of any of the above apparatus, the apparatus further comprises a look-up table (e.g., 560, fig. 5) that stores therein values of the digital symbols (e.g., I and Q values, fig. 5) for different values of the input bit word; and wherein the electronic controller is further configured to load (e.g., at 1014, figure 10) values of the digital symbols for different values of the input bit word into a lookup table based on the training pattern.

In some embodiments of any of the above apparatus, the apparatus further comprises a look-up table (e.g., 560, fig. 5) connected to the plurality of inputs and configured to output a value of the digital symbol in response to a value of the input bit word.

In some embodiments of any of the above apparatus, the apparatus further comprises a switch (e.g., 540, fig. 5) configured to select a value of the digital symbol generated by the artificial neural network or a value of the digital symbol generated by the look-up table.

In some embodiments of any of the above apparatus, the apparatus further comprises a forward error correction encoder (e.g., 510, fig. 5) configured to generate a stream of input bit words for the plurality of electrical inputs by applying a forward error correction code to the input data stream (e.g., 502, fig. 5).

In some embodiments of any of the above apparatus, the apparatus further comprises an optical data receiver (e.g., 190, fig. 1) including an optical-to-electrical converter (e.g., 160, fig. 1), a plurality of analog-to-digital converters (e.g., 166, fig. 1), and a second digital signal processor (e.g., 170, fig. 1), the analog-to-digital converters configured to output a digitized stream of measurements of the modulated optical carrier, the measurements performed by the optical-to-electrical converter; and wherein the second digital signal processor is electrically connected to process the digitized stream using a second artificial neural network (e.g., 800, fig. 8).

In some embodiments of any of the above apparatus, the digital signal processor is configured to determine the value of the digital symbol using a d-dimensional constellation, where d is an integer greater than two.

In some embodiments of any of the above apparatus, the digital signal processor is electrically connected to control one or more associated electrical drivers and includes an artificial neural network (e.g., 530, fig. 5) configured to: receiving information about multiple electrical inputs (e.g., 522)₁To 522_mFIG. 5), each of the electrical inputs being configured to input a bitDifferent respective bits of the word are carried to different respective portions of the artificial neural network (e.g., 630)₁To 630_mOne of fig. 6), each of the different respective portions being configured to respond to a respective single one of the electrical inputs; and generating output digital symbols (e.g., I and Q values, fig. 5) for the stream of digital symbols in response to the input bit words.

In some embodiments of any of the above apparatus, the artificial neural network comprises a plurality of interconnected processing elements (e.g., 200, 300, 620, fig. 6); and wherein any two of the different respective portions do not have a common processing element.

In some embodiments of any of the above apparatus, the electronic controller is further configured to load (e.g., at 1014, fig. 10) the constellation data into a lookup table; and wherein the lookup table is configured to use the constellation data to replicate output digital symbols generated by the artificial neural network in response to the input bit words.

In some embodiments of any of the above apparatus, the apparatus further comprises an optical data receiver (e.g., 190, fig. 1) including an optical-to-electrical converter (e.g., 160, fig. 1), a plurality of analog-to-digital converters (e.g., 166, fig. 1), and a second digital signal processor (e.g., 170, fig. 1), the analog-to-digital converters configured to output a digitized stream of measurements of the modulated optical carrier, the measurements performed by the optical-to-electrical converter; and wherein the second digital signal processor is electrically connected to process the digitized stream and comprises a second artificial neural network (e.g., 800, fig. 8) configured to: converting the digitized stream into a stream of output bit words; and generating a plurality of electrical outputs (e.g., 722)₁To 722_mFig. 8), each of the electrical outputs configured to carry a different respective portion (e.g., 400) of the second artificial neural network₁To 400_mOne of fig. 6), each of the different respective portions of the second artificial neural network being connected to control a respective single one of the electrical outputs.

According to another example embodiment disclosed aboveFor example, in the summary and/or with reference to any one or any combination of some or all of fig. 1 to 13, there is provided an apparatus comprising: a related optical data receiver (e.g., 190, fig. 1) including an opto-electric converter (e.g., 160, fig. 1) for a modulated optical carrier, a plurality of analog-to-digital converters (e.g., 166, fig. 1) configured to output a digitized stream of measurements of the modulated optical carrier performed by the opto-electric converter, and a digital signal processor (e.g., 170, fig. 1); and wherein the digital signal processor is electrically connected to process the digitized stream using an artificial neural network (e.g., 800, FIG. 8) configured to generate a plurality of outputs (e.g., 722) relating to the digitized stream in response to the digitized stream₁To 722_mFig. 8), each of the outputs configured to carry a different respective portion of an artificial neural network (e.g., 400)₁To 400_mOne of fig. 8), each of the different respective portions being connected to control a respective one of the outputs.

In some embodiments of any of the above apparatus, the artificial neural network further comprises a plurality of processing elements (e.g., the last layer of 810, fig. 8); and wherein each of the processing elements is connected to apply a digital input to each of the different respective portions (e.g., as indicated in fig. 8).

In some embodiments of any of the above apparatus, the apparatus further comprises an electronic controller (e.g., 760, fig. 6) configured to change a configuration parameter of the artificial neural network based on a training mode in which an associated optical data receiver receives the pilot data sequence over the optical fiber (e.g., 140, fig. 1).

In some embodiments of any of the above apparatus, the apparatus further comprises a demapping circuit (e.g., 770, fig. 7) configured to use a plurality of decision graphs (e.g., at 1018, fig. 10) in response to the digitized stream to generate a stream of output bit words; and wherein the electronic controller is further configured to load a plurality of decision graphs into a demapping circuit based on a training pattern.

In some embodiments of any of the above apparatus, the apparatus further comprises a demapping circuit (e.g., 770, fig. 7) configured to generate the stream of output bit words in response to the digitized stream.

In some embodiments of any of the above apparatus, the apparatus further comprises a switch (e.g., 730, fig. 7) configured to select the stream of output bit words generated by the artificial neural network or the stream of output bit words generated by the demapping circuit.

In some embodiments of any of the above apparatus, the apparatus further comprises a forward error correction decoder (e.g., 750, fig. 7) configured to generate an output data stream (e.g., 502, fig. 7) by applying a forward error correction code to the stream of output bit words.

In some embodiments of any of the above apparatus, the digital signal processor is configured to generate the stream of output bit words using a d-dimensional constellation, where d is an integer greater than two.

In some embodiments of any of the above apparatus, the digital signal processor is electrically connected to process the digitized stream and includes an artificial neural network (e.g., 800, fig. 8) configured to: converting the digitized stream into a stream of output bit words; and generating a plurality of electrical outputs (e.g., 722)₁To 722_mFig. 8), each of the electrical outputs is configured to carry a different respective portion (e.g., 400) of the artificial neural network₁To 400_mOne of fig. 6), each of the different respective portions being connected to control a respective single one of the electrical outputs.

In some embodiments of any of the above apparatus, the artificial neural network comprises a plurality of interconnected processing elements (e.g., 200, 300, 410, fig. 8); and wherein any two of the different respective portions do not have a common processing element.

In some embodiments of any of the above apparatus, the apparatus further comprises a demapping circuit (e.g., 770, fig. 7) configured to generate output bit words for the stream of output bit words in response to the digitized stream; wherein the electronic controller is further configured to load (e.g., at 1018, FIG. 10) a plurality of decision graphs into the demapping circuit; and wherein the demapping circuit is configured to use the decision graph to replicate the output bit words produced by the artificial neural network in response to the digitized stream.

While this disclosure includes references to illustrative embodiments, this description is not intended to be construed in a limiting sense.

For example, some embodiments may be adapted to use uncorrelated transmitters and receivers.

Various modifications of the described embodiments, as well as other embodiments within the scope of the disclosure, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the principle and scope of the disclosure, e.g. as expressed in the following claims.

Some embodiments may be implemented as circuit-based processes, including possible implementations with respect to a single integrated circuit

Some embodiments may be embodied in the form of methods and apparatuses for practicing those methods. Some embodiments may also be embodied in the form of program code recorded in tangible media, such as magnetic recording media, optical recording media, solid state memory, floppy diskettes, CD-ROMs, hard drives, or any other non-transitory machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the patent invention. Some embodiments may also be embodied in the form of program code, for example, whether stored in a non-transitory machine-readable storage medium, including loaded into and/or executed by a machine, wherein, when the program code is loaded into and executed by a machine, such as a computer or processor, the machine becomes an apparatus for practicing the patented invention. When implemented on a general-purpose processor, the program code segments combine with the processor to provide a unique device that operates analogously to specific logic circuits.

Unless expressly stated otherwise, each numerical value and range should be construed as an approximation as if the word "about" or "approximately" preceded the stated value or range.

It is to be further understood that the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this disclosure may be varied by those skilled in the art without departing from the scope of this disclosure, e.g., as expressed in the following claims.

The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use should not be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures.

Although elements in the following method claims (if any) are recited in a particular order with corresponding labeling, unless the claim recitations otherwise imply a particular order for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular order.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. The same applies to the term "embodiment".

Unless otherwise specified herein, the use of the ordinal adjectives "first," "second," "third," etc., to refer to objects in a plurality of identical objects, merely indicate that different instances of such identical objects are being referred to, and are not intended to imply that the identical objects so referred to must be in a corresponding order or sequence, either temporally, spatially, in ranking, or in any other manner.

Also for purposes of this description, the terms "couple", "connecting", connected "refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the insertion of one or more additional elements is contemplated, although not required. Conversely, the terms "directly coupled," "directly connected," etc., imply the absence of such additional elements.

The described embodiments are to be considered in all respects only as illustrative and not restrictive. In particular, the scope of the disclosure is indicated by the appended claims rather than by the description and drawings herein. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

The functions of the various elements shown in the figures, including any functional blocks labeled as "processors" and/or "controllers", may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term "processor" or "controller" should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, Digital Signal Processor (DSP) hardware, network processor, Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), Read Only Memory (ROM) for storing software, Random Access Memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included. Similarly, any switches shown in the figures are conceptual only. The functions of the switches may be performed through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.

As used in this application, the term "circuitry" may refer to one or more of the following: (a) hardware-only circuit implementations (e.g., implementations in only analog and/or digital circuitry); (b) a combination of hardware circuitry and software, for example (where appropriate): (i) a combination of analog and/or digital hardware circuitry and software/firmware and (ii) any portion of a hardware processor and software (including a digital signal processor, software, and memory that function together to cause a device, such as a mobile telephone or server, to perform various functions); and (c) hardware circuitry and/or a processor, such as a microprocessor or a portion of a microprocessor, that requires software (e.g., firmware) for operation, but software may not be present when it is not required for operation. This definition of circuitry applies to all uses of this term in this application (including in any claims). As another example, the term circuit, as used in this application, also encompasses implementations of merely a hardware circuit or processor (or multiple processors) or portion of a hardware circuit or processor and its accompanying software and/or firmware. The term circuitry also encompasses (e.g., and where applicable to a particular claim element) a baseband integrated circuit or processor integrated circuit for a mobile device, or a similar integrated circuit in a server, a cellular network device, or other computing or network device.

It should be appreciated by those of ordinary skill in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudocode, and the like represent various processes which may be substantially represented in computer readable media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

Claims

1. An apparatus, comprising:

an optical data transmitter (110) comprising:

an optical modulator (124),

one or more electrical drivers (118) connected to operate the optical modulator to modulate an optical carrier to carry a stream of digital symbols, an

A digital signal processor (112) connected to control the one or more electrical drivers in response to input data; and is

Wherein the digital signal processor is configured to use manual workA neural network (530) to determine a plurality of inputs (522) corresponding to the artificial neural network₁To 522_m) Each of the inputs being configured to carry a respective bit of the input bit word to a different respective portion of the artificial neural network (630)₁To 630_m) Each of the portions is configured to respond to a respective one of the inputs.

2. The apparatus of claim 1, wherein different ones of the respective portions are separate.

3. The apparatus as set forth in claim 1, wherein,

wherein the artificial neural network further comprises a plurality of processing elements; and is

Wherein each of the processing elements is connected to receive a digital input from each of the respective portions.

4. The apparatus of claim 1, further comprising an electronic controller configured to change configuration parameters of the artificial neural network based on a training mode in which the optical data transmitter transmits a pilot data sequence over an optical fiber.

5. The apparatus of claim 4, wherein the electronic controller is further configured to fix the configuration parameters of the artificial neural network for a payload mode in which the transmitter transmits a modulated optical carrier that carries the input data to the optical fiber.

6. The apparatus of claim 5, further comprising a lookup table storing therein values of the digital symbols for different values of the input bit word; and is

Wherein the electronic controller is further configured to load the values of the digital symbols for the different values of the input bit word into the lookup table based on the training pattern.

7. The apparatus of claim 1, further comprising a lookup table connected to the plurality of inputs and configured to output the value of the digital symbol in response to the value of the input bit word.

8. The apparatus of claim 7, further comprising a switch configured to select the value of the digital symbol generated by the artificial neural network or the value of the digital symbol generated by the lookup table.

9. The apparatus of claim 1, further comprising a forward error correction encoder configured to generate a stream of input bit words for a plurality of electrical inputs by applying a forward error correction code to an input data stream.

10. The apparatus of claim 1, further comprising:

an optical data receiver including an opto-electric converter, a plurality of analog-to-digital converters, and a second digital signal processor, the analog-to-digital converters configured to output a digitized stream of measurements of the modulated optical carrier, the measurements performed by the opto-electric converter; and is

Wherein the second digital signal processor is electrically connected to process the digitized stream using a second artificial neural network.

11. The apparatus of claim 1, wherein the digital signal processor is configured to determine the value of the digital symbol using a d-dimensional constellation, wherein d is an integer greater than two.

12. An apparatus, comprising:

a related optical data receiver (190) including an optical-to-electrical converter (160) for a modulated optical carrier, a plurality of analog-to-digital converters (166), and a digital signal processor (170), the analog-to-digital converters configured to output a digitized stream of measurements of the modulated optical carrier performed by the optical-to-electrical converter; and is

Wherein the digital signal processor is electrically connected to process the digitized stream using an artificial neural network (800) configured to generate information about a plurality of outputs (722) in response to the digitized stream₁To 722_m) Each of the outputs is configured to carry a respective bit of the output bit word produced by a different respective portion (400) of the artificial neural network, each of the different respective portions being connected to control a respective one of the outputs.

13. The apparatus of claim 12, wherein different ones of the respective portions are separate.

14. The apparatus as set forth in claim 12, wherein,

Wherein each of the processing elements is connected to apply a digital input to each of the different respective portions.

15. The apparatus of claim 12, further comprising an electronic controller configured to change configuration parameters of the artificial neural network based on a training mode in which the correlated optical data receiver receives a pilot data sequence over an optical fiber.

16. The apparatus of claim 15, further comprising a demapping circuit configured to use a plurality of decision graphs to generate a stream of output bit words in response to the digitized stream; and is

Wherein the electronic controller is further configured to load the plurality of decision graphs into the demapping circuit based on the training pattern.

17. The apparatus of claim 12, further comprising a demapping circuit configured to generate a stream of output bit words in response to the digitized stream.

18. The apparatus of claim 17, further comprising a switch configured to select the stream of output bit words generated by the artificial neural network or the stream of output bit words generated by the demapping circuit.

19. The apparatus of claim 12, further comprising a forward error correction decoder configured to generate an output data stream by applying a forward error correction code to the stream of output bit words.

20. The apparatus of claim 12, wherein the digital signal processor is configured to generate the stream of output bit words using a d-dimensional constellation, wherein d is an integer greater than two.