CN111010023B

CN111010023B - Switch mode power converter

Info

Publication number: CN111010023B
Application number: CN201910919021.6A
Authority: CN
Inventors: D·切斯诺; H·埃施; F·阿米德
Original assignee: STMicroelectronics Grenoble 2 SAS
Current assignee: STMicroelectronics Grenoble 2 SAS
Priority date: 2018-10-05
Filing date: 2019-09-26
Publication date: 2024-01-09
Anticipated expiration: 2039-09-26
Also published as: US11171565B2; EP3633487A1; CN211481150U; US20200112252A1; CN111010023A

Abstract

The present disclosure relates to a switch mode power converter. In one embodiment, an apparatus includes an operational amplifier and a feedback loop. A feedback loop is coupled between the first input of the operational amplifier and the output of the operational amplifier. The feedback loop is controllable in accordance with the saturation of the operational amplifier. In one example, the device is incorporated into a microcontroller.

Description

Switch mode power converter

Cross Reference to Related Applications

The present application claims the benefit of U.S. provisional application No.1859261 filed on 5/10/2018, which is hereby incorporated by reference.

Technical Field

The present disclosure relates generally to electronic circuits and, in particular embodiments, to switch-mode power converters.

Background

In a switched mode power converter, the DC voltage delivered to the input of the converter is chopped by switching of one or more cut-off switches to achieve a phase of power storage in the inductive element and a phase of power stored in the inductive element discharging towards the load, the load being connected to the converter output.

The known switch-mode power converter has various disadvantages.

Disclosure of Invention

Some embodiments relate to a switch mode power supply type DC/DC power converter that converts a DC voltage to another DC voltage.

One embodiment provides a switch-mode power converter that overcomes all or part of the disadvantages of common switch-mode power converters.

More specifically, one embodiment overcomes all or part of the disadvantages associated with saturation of error amplifiers of devices such as switch-mode converters.

One embodiment provides an apparatus comprising: an operational amplifier; and a feedback loop connected between the first input of the amplifier and the output of the amplifier, the feedback loop being controllable in dependence on saturation of the amplifier.

According to one embodiment, the feedback loop comprises a switch connected between the first input and the output of the amplifier, or a controllable variable resistor connected between the first input and the output of the amplifier.

According to one embodiment, the device further comprises an amplifier saturation detection circuit configured to control the feedback loop when the amplifier is saturated, to preferably reduce the impedance of the feedback loop or to reduce the impedance of the feedback loop to zero.

According to one embodiment, the circuit is configured to detect saturation of the amplifier and to control the feedback loop in dependence of an internal signal of the amplifier.

According to one embodiment, the amplifier includes a first transistor having a conductive terminal forming an output of the amplifier, the internal signal being received by a control terminal of the first transistor.

According to one embodiment, the circuit is configured to control the switch to conduct when saturation is detected, or to control the value of the variable resistor to decrease when saturation is detected.

According to one embodiment, the circuit is a direct connection between the control terminal of the first transistor and the control terminal of the switch.

According to one embodiment, the circuit comprises a first resistor and a second transistor connected in series between the power supply terminals of the amplifier, the control terminal of the second transistor being connected to the control terminal of the first transistor, and the connection node between the first resistor and the second transistor being connected to the control terminal of the variable resistor.

According to one embodiment, the switch or variable resistor corresponds to a third transistor having a first conductive terminal connected to the first input of the amplifier and having a second conductive terminal connected to the output of the amplifier.

According to one embodiment, saturation is saturation of the amplifier at a high supply potential in absolute value.

According to one embodiment, the first input is an inverting input of the amplifier.

According to one embodiment, the apparatus further comprises: an inductive element having a first terminal coupled, preferably connected, to an output terminal of the device; a switching element coupled to the second terminal of the inductive element; and a control circuit configured to control the switching circuit, preferably in Pulse Width Modulation (PWM), based in part on the output signal of the amplifier.

According to one embodiment, the device is a switch mode voltage converter, preferably a buck, buck-boost or inverting converter.

Another embodiment provides a microcontroller comprising a switch mode voltage converter such as previously defined.

Another embodiment provides a method of controlling a device comprising an operational amplifier and a controllable feedback loop connected between an output of the amplifier and a first input (preferably an inverting input) of the amplifier, the method comprising the step of reducing the impedance of the feedback loop or reducing the impedance of the feedback loop to zero when saturation of the amplifier is detected.

The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.

Drawings

FIG. 1 schematically illustrates one embodiment of a buck switch-mode converter, for example;

FIG. 2 illustrates a portion of the converter of FIG. 1 in more detail, according to one embodiment;

FIG. 3 illustrates a portion of the converter of FIG. 1 in more detail according to another embodiment; and

fig. 4 shows simulation results.

Detailed Description

In the different drawings, the same elements are denoted by the same reference numerals. In particular, structural and/or functional elements common to different embodiments may be identified by the same reference numerals and may have the same structural, dimensional, and/or material characteristics.

For clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, various switching circuits including one or more off switches of a switch-mode converter, and circuits and/or methods for controlling such off switches, particularly in Pulse Width Modulation (PWM), have not been described in detail, and the described embodiments are compatible with common switch-mode converters.

Throughout this disclosure, the term "connected" is used to denote a direct electrical connection between circuit elements without intermediate elements other than conductors, while the term "coupled" is used to denote an electrical connection between circuit elements, which may be direct or may be via one or more intermediate elements.

In the following description, unless otherwise indicated, when referring to terms defining an absolute position (such as the terms "front", "rear", "top", "bottom", "left", "right", etc.) or terms defining a relative position (such as the terms "above", "below", "upper", "lower", etc.) or terms defining a direction (such as the terms "horizontal", "vertical", etc.), reference is made to the orientation of the drawings.

The terms "about", "substantially" and "approximately" are used herein to denote tolerances of plus or minus 10%, preferably plus or minus 5%, of the values in question.

Fig. 1 schematically shows one embodiment of a switch-mode converter, and more particularly one embodiment of a DC/DC switch-mode converter, i.e. a switch-mode converter converting a DC supply voltage to another DC voltage. In this example, the converter is of the buck type, i.e. the DC voltage Vout it supplies to the load has a smaller value (absolute value) than the DC supply voltage Vin it receives.

The converter 1 comprises two terminals or nodes 3 and 4 intended to receive a DC supply voltage Vin, and two output terminals or nodes 5 and 6 intended to supply a DC output voltage Vout. For example, the voltage Vin is positive and is referenced to node 4, where node 4 is typically ground GND. For example, the voltage Vout is positive and reference is made to node 6, nodes 4 and 6 being mixed here. In this example, the converter 1 further comprises an input terminal 7. The input terminals 7 and 4 are intended to receive a DC reference voltage Vref, e.g. the DC reference voltage Vref is positive and the reference terminal 4. In this example, the converter 1 further comprises an input terminal 8, the input terminal 8 being intended to receive a periodic binary signal or clock signal clk.

The converter 1 comprises an operational amplifier 10. The amplifier 10 has two power supply terminals connected to the respective terminals 3 and 4 to be supplied with the voltage Vin. The amplifier 10 is an error amplifier. In other words, the amplifier 10 is configured to supply an output signal Verr, which represents the difference between the voltage Vout and the reference voltage Vref, at the level of its output terminal 101. For example, signal Verr is the voltage available between terminals 101 and 4, for example, the voltage is referenced to ground 4. The amplifier 10 receives a reference voltage Vref on an input terminal 102, preferably its non-inverting input (+). In other words, the terminal 102 of the amplifier is coupled, preferably connected, to the terminal 7. The amplifier 10 receives the voltage Vout or a voltage representative of the voltage Vout on a second input terminal 103, preferably its inverting input (-). In this example, terminal 103 of amplifier 10 is coupled to terminal 5 of converter 1 through complex impedance Z1, where complex impedance Z1 may include, for example, one or more resistive and capacitive components having impedance Z1 as an equivalent impedance. Preferably, the impedance Z1 is connected to the respective terminals 5 and 103, or in other words, only the impedance Z1 is present between the terminals 5 and 103.

Feedback loop 11 (preferably a negative feedback loop) couples the output terminal 101 of amplifier 10 to its input terminal 103. In this embodiment, a feedback loop 11 is provided which is controllable in dependence of the saturation of the amplifier 10. More specifically, it is provided to reduce the impedance of the feedback loop 11 or even to reduce the impedance to zero when saturation of the amplifier 10 is detected. In other words, when the amplifier 10 is saturated, the output 101 of the amplifier 10 and the input 103 of the amplifier 10 tend to be short-circuited. Preferably, when the amplifier 10 is no longer saturated, the feedback loop 11 is controlled such that its impedance resumes its nominal value, i.e. its value without saturation of the amplifier. Preferably, the nominal value of the impedance of the feedback loop 11 is chosen to ensure the stability of the amplifier and, more specifically, of the loop comprising the amplifier.

In this example, feedback loop 11 includes a complex impedance Z2 connected between respective terminals 101 and 103, i.e., one or more resistive and capacitive components having impedance Z2 as an equivalent impedance. The feedback loop 11 further comprises a controllable component 111, the controllable component 111 being connected between the respective terminals 101 and 103, in this example in parallel with the impedance Z2, the controllable component 111 corresponding to a switch or controllable variable resistor. In this example, component 111 is a transistor, preferably a Metal Oxide Semiconductor (MOS) transistor, preferably having a P-channel, whose conductive terminals (source/drain) are coupled, preferably connected, to respective terminals 101 and 103.

Although the feedback loop 11 corresponds in this example to a parallel connection of the complex impedance Z2 and the controllable component 111, as a variant the feedback loop may comprise only a controllable complex impedance connected between the terminals 101 and 103. In this variant, when the amplifier 10 is saturated, the complex impedance can be controlled to reduce the impedance of the feedback loop 11 between the terminals 101 and 103 or even to reduce this impedance to zero.

In this embodiment, the converter 1 comprises a circuit 12 for controlling the feedback loop 11 (i.e. the controllable component 111 in this example). More specifically, the circuit 12 is configured to detect saturation of the amplifier 10 and to control the feedback loop 11 accordingly. As an example, the circuit 12 detects saturation of the amplifier 10 and controls the feedback loop 11 by using the internal signal of the amplifier, to which the circuit 12 is not shown in fig. 1 in order to obtain the internal signal. Further, although not shown in the example of fig. 1, the circuit 12 may be connected between the terminals 3 and 4 to be supplied with the voltage Vin.

The converter 1 further comprises a switching control circuit or cut-off control circuit 20, for example, the switching control circuit or cut-off control circuit 20 being connected between the terminals 3 and 4 so that it can be supplied with the voltage Vin. Circuit 20 is configured to determine at least one off control signal or switch control signal based at least in part on output signal Verr of amplifier 10. The off control signal is preferably a Pulse Width Modulation (PWM) signal, for example a signal having a duty cycle that depends on the value of the voltage Verr. For example, the off control signal is also determined from the signal clk.

In the example shown, the circuit 20 supplies a single cut-off control signal cmd at the level of its output terminal 201. Further, the circuit 20 comprises an input terminal 202 and an input terminal 203, the input terminal 202 being coupled, preferably connected, to the terminal 8 for receiving the signal clk, the input terminal 203 being coupled, preferably connected, to the output terminal 101 of the amplifier 10 for receiving the voltage Verr.

In this example, more specifically, circuit 20 includes a ramp generator 205 (Gen-R) and a comparator 206, generator 205 and/or comparator 206 being connected, for example, between terminals 3 and 4 to be supplied with voltage Vin.

The generator 205 is configured to deliver the ramp signal VR at the level of its output terminal 2051. Preferably, the signal VR is periodic with the same period as the signal clk, and the input terminal 2052 of the generator 205 receives the signal clk from the input 202. For example, signal VR is the voltage available between terminals 2051 and 4 and is referenced to ground terminal 4. As an example, the value of the voltage VR is zero at the beginning of each cycle of the signal clk and increases to a maximum value, preferably the value of the supply voltage Vin, at the end of each cycle of the signal clk.

The comparator 206 is here configured to deliver the signal cmd at the level of its output terminal 2061, the output terminal 2061 being coupled, preferably connected to the terminal 201. Comparator 206 determines signal cmd from the signals or voltages VR and Verr it receives on its respective input terminals 2062 and 2063, terminal 2062 being coupled, preferably connected, to terminal 2051, and terminal 2061 being coupled, preferably connected, to terminal 203.

The converter 1 further comprises a switching circuit 30 (in dashed lines in fig. 1). The circuit 30 is connected between the terminals 3 and 4 to receive the supply voltage Vin. The circuit 30 includes an output terminal 301. Depending on the cut-off control signal it receives from circuit 20, circuit 30 is configured to selectively couple terminal 102 to terminal 3, terminal 4, or possibly not to both terminals 3 and 4, in this example the signal cmd that circuit 30 receives on its input terminal 302. The selective coupling of terminal 301 to terminal 3, terminal 4, or less than both terminals 3 and 4 is achieved by means of one or more cut-off switches of circuit 30 controlled by a cut-off control signal.

In the example shown, the circuit 30 comprises two cut-off switches 303 and 304, which cut-off switches 303 and 304 are connected in series between the terminals 3 and 4 and are controlled by a signal cmd. Here, the connection nodes of the switches 303 and 304 correspond to the output terminal 301. In this example, switch 303 is a MOS transistor, e.g., having a P-channel, with its source and drain connected to terminals 301 and 3, respectively, and switch 304 is a MOS transistor, e.g., having an N-channel, with its drain and source connected to terminals 301 and 4, respectively, with the gates of transistors 303 and 304 coupled, preferably connected, to terminal 302.

The converter 1 further comprises an inductive element 40, e.g. an inductance, the inductive element 40 coupling the terminal 301 of the circuit 30 to the terminal 5 of the converter 1, the inductive element 40 preferably being connected to the respective terminals 301 and 5. As a variant, the inductive element 40 may be external to the converter 1. Further, in this example, a capacitive element 50 (e.g., a capacitor) couples terminals 5 and 6, the capacitive element 50 preferably being connected to the respective terminals 5 and 6. The capacitive element may form part of the converter 1 or be external to the converter.

In operation, the signal clk and the voltages Vref and Vin are supplied to the converter 1. A load 60 (the converter 1 supplies a voltage Vout to the load 60) is connected between the terminals 5 and 6. From the signal clk and the voltages Vref, vin and Vout, and more specifically from the voltages VR and Verr, the circuit 20 generates a signal cmd to hold the voltage Vout across the combination of the load 60 and the capacitive element 50, the value of the voltage Vout being dependent on the reference voltage Vref, preferably the value of the voltage Vout being substantially equal to, preferably equal to, the value of the voltage Vref. More specifically, in the depicted example, when switches 303 and 304 are turned on and off, respectively, for example, when signal cmd is in a low logic state (e.g., equal to ground) and voltage Vout is less than voltage Vin, power is stored in inductive element 40 and current IL in the inductive element increases. Conversely, when switches 303 and 304 are turned off and on, respectively, for example, when signal cmd is in a high logic state (e.g., equal to Vin), inductive element 40 returns power to the combination of load 60 and capacitive element 50, and current IL in the inductive element decreases.

Preferably, when the voltage Vout is equal to the voltage Vref, the converter 1 (and more particularly the amplifier 10) is configured such that the voltage Verr is equal to the voltage Vref.

As the current drawn by load 60 increases, this typically results in a corresponding decrease in voltage Vout relative to reference voltage Vref. This results in an increase in voltage Verr and thus in an increase in the duration of its low logic state for each cycle of signal cmd, which tends to return voltage Vout to voltage Vref.

When the reduction of the voltage Vout with respect to the voltage Vref causes the amplifier 10 to saturate, i.e. when the voltage Verr it supplies reaches a maximum value (i.e. the value of the supply voltage Vin of the amplifier), the circuit 12 controls the feedback loop 11 to reduce its impedance or even to reduce its impedance to zero. As a result, the voltage Verr tends to be the voltage present on the input 103 of the amplifier, in particular, since the capacitance 50 between terminals 5 and 6 is, for example, at least 5 times, preferably at least 10 times, the capacitance present between terminals 101 and 4 (i.e. the capacitance of node 101). Since the voltage Vout is smaller than the voltage Vin, the voltage between the terminals 103 and 4 is smaller than the saturation voltage Vin of the amplifier 10, and the feedback loop 11 tends to apply a voltage value Verr smaller than the value of the saturation voltage Vin of the amplifier 10. This allows to reduce the time required for the amplifier 10 to leave saturation with respect to the case where the converter 1 does not comprise the controllable feedback loop 11 and does not comprise the circuit 12.

In fact, without controllable feedback loop 11 and circuit 12, although after the decrease in voltage Vout causes amplifier 10 to saturate, voltage Vout increases to a value such that voltage Verr should be less than the saturation voltage of amplifier 10, the amplifier may still remain saturated for a while, which may result in oscillations of voltage Vout and/or significant current peaks IL.

To avoid this, the power amplifier 10 may be designed with a sufficiently high voltage Vin so that the amplifier 10 never saturates. However, this results in an increase in power consumption of the converter, which is undesirable. This will further result in limiting the minimum operating supply voltage of the converter 1, which may be particularly disturbing when the voltage Vin is supplied by a battery cell or battery.

Fig. 2 shows a part of a converter 1 according to an embodiment in a more detailed manner. More specifically, fig. 2 shows circuit 12, controllable component 111, terminals 3 and 4, and only a portion of amplifier 10, i.e. input terminal 103 of amplifier 10 and its output stage for supply voltage Verr.

In this embodiment, the output stage or gain stage of the amplifier 10 includes, for example, a MOS transistor 104 having a P channel, and a current source 105 biasing the transistor 104. A transistor 104 and a current source 105 are connected in series between terminals 3 and 4, where transistor 104 is connected to terminal 3. The output terminal 101 of the amplifier 10 corresponds to a connection node between the transistor 104 and the current source 105, i.e. here, corresponds to the source of the transistor 104. A control terminal (gate) 106 of transistor 104 receives an internal signal Vint of amplifier 10, which represents the differential voltage of amplifier 10, i.e., the voltage difference between inputs 102 and 103 of amplifier 10. As one example, the signal Vint is an output signal of a differential pair. In the example shown, miller compensation is provided in the output stage of the amplifier 10, with a resistor R and a capacitor C connected in series between the gate 106 and the source 101 of the transistor 104.

In this embodiment, circuit 12 is a direct connection between control terminal (gate) 106 of transistor 104 and the control terminal of component 111 (i.e., in this example, the gate of transistor 111). In this embodiment, the transistor 111 is controlled in a discrete manner (all or none). In other words, the component 111 corresponds to a switch.

The saturated or unsaturated state of the amplifier 10 depends on the signal Vint of the control transistor 104. Thus, the signal Vint allows saturation of the sense amplifier 10. More specifically, in the example shown, during saturation of the amplifier 10, the voltage Vint between the gate of the transistor 104 and the terminal 4 is zero or near zero. Thus, when the amplifier is saturated, the signal Vint applied to the control terminal of the switch 111 causes it to conduct. In other words, the voltage Vint between the control terminal of the transistor 111 and the terminal 4 causes the transistor 111 to be turned on.

Fig. 3 shows a part of a converter 1 according to another embodiment in a more detailed manner. The embodiment of fig. 3 differs from the embodiment of fig. 2 only in that: its circuit 12 and assembly 111 correspond to a controllable variable resistor.

In this embodiment, circuit 12 is connected to terminals 3 and 4 to be powered by voltage Vin. The circuit 12 includes a resistor 107 and a MOS transistor 108 connected in series between the terminals 3 and 4, for example, the MOS transistor 108 has a P channel. In this example the conductive terminal (here the source) of the transistor 108 is connected to terminal 4, the terminal of the resistor 107 is connected to terminal 3, and the connection node 109 between the transistor 108 and the resistor 107 forms the output of the circuit 12, the node 109 being connected to the control terminal of the controllable variable resistor 111, i.e. in this example the node 109 is connected to the control terminal (gate) of the transistor 111. Further, a control terminal of the transistor 108 is connected to a control terminal of the transistor 104 of the amplifier 10 to receive the internal signal Vint.

The operation is similar to that described with respect to fig. 2, except that: instead of controlling the component 111 in a discrete manner (switch 111 off or on), the component 111 (in this example, transistor 111) is here controlled linearly, the value of the variable resistor 111 decreasing as the amplifier 10 approaches its saturated state, the value of the variable resistor 111 decreasing to a minimum value when the amplifier is saturated. This results in a less abrupt decrease in the impedance of the feedback loop 11 as in the embodiment described in relation to fig. 2, which results in a less abrupt response of the converter 1 after saturation of the amplifier 10.

The circuit 12 and the component 111 described in relation to fig. 2 and 3 (especially when the component 111 is a transistor) are particularly easy to implement, with low volume and low power consumption.

Fig. 4 shows simulation results.

Fig. 4 includes timing charts 401, 402, and 403 obtained for a converter 1 according to the embodiment of fig. 3, and timing charts 404, 405, and 406 obtained for converters different from the converters of the timing charts 401, 402, and 403, except that the converters of the timing charts 404, 405, and 406 do not include the component 111 and the circuit 12. The timing diagrams 401, 402, 403, 404, 405 and 406 share the same time scale t in abscissa and in microseconds (μs) and illustrate the operation of the converter during current draw of the load 60 causing saturation of the amplifier 10. In the example of fig. 4, the difference between two consecutive abscissa steps corresponds to 2 μs. In this example, the voltage Vin is equal to 1.6V and the voltage Vref is equal to 1.2V.

More specifically, timing diagrams 401 and 404 show changes in current IL in inductive element 40 (fig. 1) in milliamperes (mA), timing diagrams 402 and 405 show changes in voltage Vout in volts (V), and timing diagrams 403 and 406 show changes in voltage Verr in volts (V).

At time t0, voltage Vout decreases after the current draw, which causes voltage Verr to increase to its saturation value (1.6V in this example), with voltage Verr reaching its saturation value at the next time t 1. As long as voltage Verr remains equal to its maximum value, circuit 20 (fig. 1) controls circuit 30 (fig. 1) such that terminal 102 of inductive element 40 is coupled to terminal 3 and current IL increases.

At time t2 after time t1 (equal to t0 plus 50 μs in this example), voltage Vout reaches a minimum, amplifier 10 is still saturated, and voltage Verr is equal to 1.6V.

At time t3 after time t2, while the voltage Vout increases, in the converters corresponding to the timing charts 401, 402, and 403, the voltage Verr starts to decrease because the impedance of the feedback loop 11 decreases or even is zero due to the saturation of the amplifier 10 (time t 1). In contrast, in the converters corresponding to the timing charts 404, 405, and 406, the voltage Verr decreases only from time t4 after time t 3.

Thus, from time t3, circuits 20 and 30 of the converters of timing diagrams 401, 402, and 403 operate such that the increasing phase of current IL alternates with the decreasing phase of current IL, while in the converters of timing diagrams 404, 405, and 406 this occurs only from time t 4.

It can then be observed that the voltage Vout of the converters of the timing diagrams 401, 402 and 403 gradually increases to a value of 1.2V without oscillation, contrary to what happens in the converters of the timing diagrams 404, 405 and 406. Since voltage Verr depends on voltage Vout, voltage Verr exhibits little or no oscillation in the converters of timing diagrams 401, 402, and 403, as opposed to voltage Verr of the converters of timing diagrams 404, 405, and 406. Furthermore, the voltage Verr of the converters of the timing charts 401, 402, and 403 recovers a stable value equal to the voltage Vref faster than the voltage Verr of the converters of the timing charts 404, 405, and 406.

It can then also be observed that the current IL of the converters of the timing diagrams 401, 402 and 403 more or less exhibits regular alternation of increasing and decreasing phases of its value and further exhibits a current IL with a smaller maximum value than the current IL of the converters of the timing diagrams 404, 405 and 406.

Various embodiments of a switch-mode converter have been described above. For example, such embodiments are suitable for use in microcontrollers, such as in Power Management Units (PMUs) that form various elements of microcontrollers (e.g., volatile memory such as RAM, non-volatile memory such as flash memory, data, address and/or control buses, processing units, input/output interfaces, etc.). In this case, the converter belongs to the microcontroller.

Furthermore, while the case of a buck-type voltage converter has been described above, it is within the ability of those skilled in the art, based on structural and/or functional indications of the present disclosure, to: the described embodiments are adapted to any power converter using an error amplifier to achieve a switching operation of a pulse width modulation control, e.g. a boost converter, a buck-boost converter, which may be inverting (positive voltage Vin and negative voltage Vout) or non-inverting. Such other converters may further have one or more outputs, such as, for example, a buck converter having multiple outputs, a buck/boost converter having a positive output and a negative output, and the like.

Furthermore, although the saturation of the amplifier 10 at its high value of the supply voltage Vin is more specifically described, it is within the ability of a person skilled in the art to: the described embodiments are adapted to the case where the amplifier is saturated at its low value with an absolute value. In this case, the transistor 104 (fig. 2 and 3) of the output stage of the amplifier 10 may be, for example, an N-channel transistor, and then the current source 105 is connected between the transistor 104 and the terminal 3. The controllable element 111 and the transistor 108 in the embodiment of fig. 3 may then be formed with an N-channel transistor.

More generally, although embodiments have been described in which the transistor is a MOS transistor, it is within the ability of those skilled in the art to: these embodiments are adapted to the case where at least some of the transistors used are bipolar transistors.

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, the embodiments described above are not limited to the circuits 20 and 30 shown in fig. 1. For example, control circuit 20 may include a state machine, and/or supply a plurality of off control signals (one for each off switch of circuit 30). For example, the control circuit may be adapted to implement the control method described in applicant's french application No. 1855400.

More generally, an operational amplifier 10, a controllable component 111 (variable switch or resistor) coupling an input (preferably an inverting input) to an amplifier output, and a control circuit 12 of the controllable component may be provided in other circuits than a voltage converter. For example, such an assembly may be provided in the following circuit: wherein the amplifier is an error amplifier between the reference voltage and the output voltage of the circuit, the output signal of the amplifier determining the control signal inside the circuit.

Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the competence of a person skilled in the art. In particular, it is within the ability of one skilled in the art to provide other implementations with respect to component 111 and/or circuit 12.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The invention is limited only as defined in the following claims and equivalents thereto.

Claims

1. An electronic device, comprising:

an operational amplifier; and

a feedback loop coupled between a first input of the operational amplifier and an output of the operational amplifier, the feedback loop being controllable in accordance with saturation of the operational amplifier;

wherein the feedback loop comprises a first circuit coupled between the first input and the output of the operational amplifier;

wherein the first circuit comprises a first transistor having a first conductive terminal coupled to the first input of the operational amplifier and a second conductive terminal coupled to the output of the operational amplifier;

the electronic device further includes an amplifier saturation detection circuit configured to control the feedback loop to linearly reduce an impedance of the feedback loop when the operational amplifier is saturated.

2. The electronic device of claim 1, wherein the amplifier saturation detection circuit is configured to detect saturation of the operational amplifier and to control the feedback loop based on an internal signal of the operational amplifier.

3. The electronic device defined in claim 2 wherein the operational amplifier comprises a first transistor comprising:

a conductive terminal forming the output of the operational amplifier; and

and a control terminal configured to receive the internal signal.

4. An electronic device, comprising:

an operational amplifier;

a feedback loop coupled between a first input of the operational amplifier and an output of the operational amplifier, the feedback loop being controllable in accordance with saturation of the operational amplifier; wherein the feedback loop comprises a first circuit coupled between the first input and the output of the operational amplifier;

an amplifier saturation detection circuit configured to control the feedback loop to reduce an impedance of the feedback loop when the operational amplifier is saturated; wherein the amplifier saturation detection circuit is configured to detect saturation of the operational amplifier and control the feedback loop based on an internal signal of the operational amplifier; wherein the operational amplifier comprises a first transistor comprising: a conductive terminal forming the output of the operational amplifier; and a control terminal configured to receive the internal signal; and is also provided with

Wherein the first circuit is a switch, and wherein the amplifier saturation detection circuit is configured to control the switch to conduct linearly when saturation is detected.

5. The electronic device of claim 4, wherein the amplifier saturation detection circuit is directly connected between a control terminal of the first transistor (104) and a control terminal of the switch.

6. An electronic device, comprising:

an operational amplifier;

Wherein the first circuit comprises a controllable variable resistor, and wherein the amplifier saturation detection circuit is configured to control a value reduction of the controllable variable resistor linearly when saturation is detected.

7. The electronic device defined in claim 6 wherein the controllable variable resistor comprises a transistor.

8. The electronic device according to claim 6,

wherein the amplifier saturation detection circuit comprises a first resistor coupled between a first power supply terminal of the operational amplifier and an intermediate node, and a second transistor coupled between the intermediate node and a second power supply terminal of the operational amplifier, wherein the second transistor comprises a control terminal coupled to a control terminal of the first transistor, and wherein the intermediate node is coupled to a control terminal of the controllable variable resistor.

9. The electronic device of claim 1, wherein the saturation is saturation of the operational amplifier at a high supply potential in absolute value.

10. The electronic device of claim 1, wherein the first input is an inverting input of the operational amplifier.

11. The electronic device of claim 1, further comprising:

an inductive element having a first terminal coupled to an output terminal of the electronic device;

a switching circuit coupled to a second terminal of the inductive element; and

a control circuit configured to control the switching circuit based at least in part on an output signal of the operational amplifier.

12. The electronic device of claim 1, wherein the electronic device is a buck-type, buck-boost type, or an inverting type switch-mode voltage converter.

13. A microcontroller comprising a switch mode voltage converter according to claim 12.

14. A method of operating a switch-mode voltage converter, the method comprising:

receiving an input voltage with a switching circuit;

generating an output voltage;

receiving a reference voltage with a first input of an amplifier;

receiving a feedback signal with a second input of the amplifier, the feedback signal being based on the output voltage;

generating an error signal at an output of the amplifier, wherein the switching circuit switches based on the error signal;

detecting saturation of the amplifier; and

upon detecting saturation of the amplifier, an impedance between the output of the amplifier and the second input of the amplifier is linearly reduced.

15. The method of claim 14, wherein reducing the impedance comprises reducing the impedance to zero.

16. The method of claim 14, wherein reducing the impedance comprises turning on a transistor directly connected between the output of the amplifier and the second input of the amplifier.

17. A buck converter, comprising:

an output stage having an output terminal configured to be coupled to an inductor;

a comparator having an output coupled to the output stage;

an amplifier, comprising:

a first input configured to receive a reference voltage;

a second input coupled to the output terminal of the output stage; and

an output coupled to an input of the comparator;

a feedback loop circuit coupled between the second input of the amplifier and the output of the amplifier; and

a first circuit configured to detect saturation of the amplifier and to linearly reduce an impedance of the feedback loop circuit when the amplifier is saturated.

18. The buck converter of claim 17, wherein the amplifier further comprises a first transistor having a first conductive terminal coupled to the output of the amplifier, wherein the first circuit comprises a second transistor having a control terminal coupled to a control terminal of the first transistor, and wherein the feedback loop circuit comprises a third transistor having a control terminal coupled to the second transistor and a first conductive terminal coupled to the first conductive terminal of the first transistor.