CN111008168A - Control method, system and storage medium for connection of CPU and chip - Google Patents
Control method, system and storage medium for connection of CPU and chip Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Abstract
The invention discloses a control method, a system and a storage medium for connection of a CPU and a chip, wherein the method comprises the following steps: the data line and the address line of the CPU are all accessed into the CPLD, and the data line and the address line of the chip are all accessed into the CPLD; the CPU sets chip selection bit width and informs the CPLD through a register, and the CPLD connects a CPU data line with a chip data line according to the chip selection bit width; the CPU allocates a base address to the chip selection where the CPLD is located, the CPLD detects the large end mode and the small end mode of the CPU, and the CPLD adjusts the connection sequence of the data line and the address line to the chip according to the large end mode and the small end mode of the CPU; and confirming whether the chip is consistent with the CPU in byte order or not, and informing the CPLD of the result of consistent byte order release by the CPU. The invention realizes the automatic matching of the CPU, the chip address wire and the chip data wire, and does not need to define the size end again after the CPU is replaced.
Description
Technical Field
The invention relates to the technical field of computer embedded driving, in particular to a control method and a control system for connection of a CPU (Central processing Unit) and a chip and a storage medium.
Background
In a computer system, each address unit corresponds to one byte in units of bytes, and each byte is 8 bits. However, in addition to the char of 8 bits (used for defining character type variables in C or C + +, which only occupies one byte), there are short types of 16 bits (which define one type of integer variable family in C language), long types of 32 bits (which represent a long integer data, which is a basic data type in programming language, and which need to look at a specific compiler), and in addition, for processors with more bits than 8 bits, such as 16-bit or 32-bit processors, since the register width is greater than one byte, there is a problem of how to arrange a plurality of bytes. Thus resulting in a big-end storage mode and a little-end storage mode. For example, a 16-bit short type a, has an address of 0x0010 in memory, and a has a value of 0x1122, then 0x11 is the high byte and 0x22 is the low byte. For big-end mode, 0x11 is placed in the low address, 0x0010, and 0x22 is placed in the high address, 0x 0011. Small end mode, exactly the opposite. The conventional X86 structure is in the small end mode, while KEIL C51 is in the large end mode. Many ARM and DSP are in small-end mode. Some ARM processors can also switch size sides at any time in the program (using REV, REV16, REVSH instruction [1] in the ARM Cortex family).
The Big-endian (Big-endian) mode is a storage mode in which a high byte of data is stored in a low address of a memory and a low byte of data is stored in a high address of the memory, and is somewhat similar to a mode in which data is sequentially processed as a character string: the address increases from small to large, and the data is put from high to low; for example:
0000430:e684 6c4e 0100 1800 53ef 0100 0100 0000
0000440:b484 6c4e 004e ed00 0000 0000 0100 0000
in big-end mode, the first 32 bits should be read as e 6846 c 4e (assuming int takes 4 bytes);
the memory method is that the growth sequence of the address is opposite to that of the value.
The small-end mode (Little-endian) means that the high byte of data is stored in the high address of the memory, and the low byte of data is stored in the low address of the memory, the storage mode effectively combines the high and low of the address and the data bit weight, the weight of the high address part is high, the weight of the low address part is low, and the logic method is consistent. For example:
0000430:e684 6c4e 0100 1800 53ef 0100 0100 0000
0000440:b484 6c4e 004e ed00 0000 0000 0100 0000
in small-end mode, the first 32 bits should be read 4e 6c 84e6 (assuming int takes 4 bytes);
the memory method is characterized in that the growth sequence of addresses is the same as that of values.
Common big end CPU: POWERPC, MIPS;
common small-end CPU: x86, ARM;
the CPU with different size ends, the definition of the highest bit of the data line or the address line is different. The Most Significant Bit (MSB) of the big end CPU is bit0, and the Least Significant Bit (LSB) is bit 31. As shown in fig. 1: the register is 32 bits, the binary expression is 0b 0000-0001-0000-0101, the corresponding hexadecimal expression is 0x0011-0105, it can be seen that the highest bit is bit0, and the lowest bit is bit 31.
For the CPU of the small-end mode, of the 32-bit data, the Most Significant Bit (MSB) is bit31, and the Least Significant Bit (LSB) is bit0, as shown in fig. 2.
In hardware design, the mastering of the size end by a hardware engineer is a basic requirement. The big end CPU accesses the chip of the parallel bus, such as FLASH, CPLD and other 8/16/32 bit width chips, the lowest bit of the address and data line must be bit 31. As shown in fig. 3, power pc accesses a piece of NOR FLASH with a data bit width of 16bit, the lowest bit LA31 of CPU must float for byte addressed system, bit30 is connected to the lowest bit of FLASH, so that CPU accesses FLASH only with even addresses of 0/2/4 · · · · and so on. 16bit of data line, the highest bit LAD0, and the lowest bit LAD 15. The address line is connected with LA5 at the highest position and LA30 at the lowest position.
For the small-end CPU, the highest data line is connected with LAD15, and the lowest data line is connected with LAD 0. The address line is connected with LA26 at the highest position and LA1 at the lowest position.
That is to say, in the prior art, the CPU cannot be automatically matched with the address line and the data line of the peripheral chip, and after the CPU is replaced, the size end needs to be defined again.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
The present invention mainly aims to provide a method, a system and a storage medium for controlling the connection between a CPU and a chip, and aims to solve the above-mentioned defects in the prior art.
In order to achieve the above object, the present invention provides a method for controlling connection between a CPU and a chip, wherein the method for controlling connection between the CPU and the chip comprises:
the data line and the address line of the CPU are all accessed into the CPLD, and the data line and the address line of the chip are all accessed into the CPLD;
the CPU sets chip selection bit width and informs the CPLD through a register, and the CPLD connects a CPU data line with a chip data line according to the chip selection bit width;
the CPU allocates a base address to the chip selection where the CPLD is located, the CPLD detects the large end mode and the small end mode of the CPU, and the CPLD adjusts the connection sequence of the data line and the address line to the chip according to the large end mode and the small end mode of the CPU;
and confirming whether the chip is consistent with the CPU in byte order or not, and informing the CPLD of the result of consistent byte order release by the CPU.
Optionally, the method for controlling connection between the CPU and the chip, where the data line and the address line of the CPU are all accessed into the CPLD, and the data line and the address line of the chip are all accessed into the CPLD specifically includes:
data lines LA 0-LA 31 and address lines LD 0-LD 31 of the CPU are all connected into the CPLD, and data lines D0-D15 and address lines A0-A26 of the chip are all connected into the CPLD.
Optionally, the method for controlling connection between the CPU and the chip, where the CPU sets a chip select bit width and informs the CPLD through a register, and the CPLD connects the CPU data line and the chip data line according to the chip select bit width specifically includes:
the CPU sets the chip selection bit width 16 bits and informs the CPLD through the register;
according to the chip selection bit width, the CPLD connects a CPU data line LD0 with a chip data line D0 by default, a CPU address line LA0 is not connected with the chip, and LA1 is connected with a chip A0.
Optionally, the method for controlling connection between the CPU and the chip, where the CPU allocates a base address to a chip select where the CPLD is located, the CPLD detects a large-small end mode of the CPU, and the CPLD adjusts a connection sequence of the data line and the address line to the chip according to the large-small end mode of the CPU, specifically includes:
the CPU allocates a base address CPLD _ base _ adrs to the chip selection where the CPLD is located;
the CPLD detects the mode of the big end and the small end of the CPU;
and the CPLD adjusts the connection sequence of the data line and the address line to the chip according to the large end mode and the small end mode of the CPU.
Optionally, the method for controlling connection between the CPU and the chip, where the CPLD detects a size mode of the CPU specifically includes:
the CPU reads the address of CPLD _ base _ adrs +1, only one address line provided by the CPU to the CPLD is 1, and the other address lines are 0;
if LA30 is equal to 1, the CPU is the big end CPU, otherwise it is the small end CPU.
Optionally, the method for controlling connection between the CPU and the chip, wherein the adjusting, by the CPLD, a connection order of the data line and the address line to the chip according to a size end mode of the CPU specifically includes:
if the mode is the small-end mode, no adjustment is made;
if the mode is large-end mode, the data line switching sequence LD 15-LD 0 of the CPU is connected with the D0-D15 of the chip, and the address lines are adjusted to LA 30-LA 4 connected with the A0-A26 of the chip.
Optionally, the method for controlling connection between a CPU and a chip, wherein the determining whether the chip and the CPU have a consistent endian, and the CPU informs the CPLD of a result of consistent endian release, specifically includes:
reading two bytes of an address cpld _ base _ adrs +2 to A and reading 2 bytes of an address cpld _ base _ adrs +1 to B by the CPU;
if A is B, the CPU has the same byte order as the chip, otherwise, the byte order is opposite;
if the byte order of the chip is consistent with that of the CPU, the CPLD does not need to adjust the connection relation between the data line and the address line;
if the chip and the CPU have inconsistent byte order, the data line exchange sequence LD 15-LD 0 of the CPU is connected with the D0-D15 of the chip, and the address lines are adjusted to LA 30-LA 4 connected with the A0-A26 of the chip.
Optionally, the method for controlling connection between the CPU and the chip, wherein the determining whether the chip and the CPU have the same byte order, includes
If the CPU is consistent with the sequence of the chip size end, the lowest order signal of the 16-bit address is not sent to the chip, and the 0 and 1 address access is the 0 address of the chip;
if the CPU is in reverse order from the chip size side, then the 0 address accesses the 0 address of the chip, and 1 accesses the offset address of 0x8000-0000 of the chip.
In addition, in order to achieve the above object, the present invention further provides a control system for connecting a CPU and a chip, wherein the control system for connecting the CPU and the chip comprises: a CPU and a chip; the data line and the address line of the CPU are all accessed into the CPLD, and the data line and the address line of the chip are all accessed into the CPLD; the CPU sets chip selection bit width and informs the CPLD through a register, and the CPLD connects a CPU data line with a chip data line according to the chip selection bit width; the CPU allocates a base address to the chip selection where the CPLD is located, the CPLD detects the large end mode and the small end mode of the CPU, and the CPLD adjusts the connection sequence of the data line and the address line to the chip according to the large end mode and the small end mode of the CPU; and confirming whether the chip is consistent with the CPU in byte order or not, and informing the CPLD of the result of consistent byte order release by the CPU.
In the invention, the data line and the address line of the CPU are all accessed into the CPLD, and the data line and the address line of the chip are all accessed into the CPLD; the CPU sets chip selection bit width and informs the CPLD through a register, and the CPLD connects a CPU data line with a chip data line according to the chip selection bit width; the CPU allocates a base address to the chip selection where the CPLD is located, the CPLD detects the large end mode and the small end mode of the CPU, and the CPLD adjusts the connection sequence of the data line and the address line to the chip according to the large end mode and the small end mode of the CPU; and confirming whether the chip is consistent with the CPU in byte order or not, and informing the CPLD of the result of consistent byte order release by the CPU. The invention realizes the automatic matching of the CPU and the address line and the data line of the peripheral chip, and after the CPU is replaced, the size end does not need to be defined again, and the invention only needs to be according to the commonly used connection method of the CPU which is actually used.
Drawings
FIG. 1 is a diagram of a prior art register represented in binary;
FIG. 2 is a diagram of prior art, for a small-end mode CPU, where the Most Significant Bit (MSB) of 32 bits of data is bit31 and the Least Significant Bit (LSB) is bit 0;
FIG. 3 is a diagram of prior art POWEPC accessing a piece of NOR FLASH;
FIG. 4 is a schematic diagram of the connection of a large-end CPU to a chip;
FIG. 5 is a schematic diagram of the connection of a small-end CPU to a chip;
FIG. 6 is a flow chart of a control method for CPU and chip connection according to a preferred embodiment of the present invention;
FIG. 7 is a diagram illustrating a first state of communication between a CPU and a slave device in the preferred embodiment of the control method for connecting the CPU and the chip of the present invention;
FIG. 8 is a diagram illustrating a first connection state of a CPU and a chip according to a preferred embodiment of the method for controlling the connection of the CPU and the chip of the present invention;
FIG. 9 is a diagram showing a second connection state of the CPU and the chip in the preferred embodiment of the control method for connecting the CPU and the chip according to the present invention;
FIG. 10 is a diagram illustrating a second state of communication between the CPU and the slave device in the preferred embodiment of the control method for connecting the CPU and the chip of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in FIG. 4, the highest bit of the data line of the large-end CPU is LD0 chip data highest bit D15, LD15 chip D0. Because the chip is a 16-bit data line, the addresses that the CPU gives to the chip to access can only be even addresses. The lowest bit LA31 of the address line of the large-end CPU is suspended, and the second lowest bit LA30 is connected with the lowest bit A0 of the chip, so that the address coming out of the CPU is always even to the chip.
As shown in FIG. 5, the highest bit of the data line of the small-end CPU is LD15 chip data highest bit D15, LD0 chip D0. Because the chip is a 16-bit data line, the addresses that the CPU gives to the chip to access can only be even addresses. The lowest bit LA0 of the address line of the small-end CPU is suspended, and the second lowest bit LA1 is connected with the lowest bit A0 of the chip, so that the address from the CPU is always even to the chip.
As shown in fig. 6 to 10, the method for controlling connection between a CPU and a chip according to a preferred embodiment of the present invention includes:
step S10, all the data lines and address lines of the CPU are accessed into the CPLD, and all the data lines and address lines of the chip are accessed into the CPLD;
step S20, the CPU sets chip selection bit width and informs the CPLD through the register, and the CPLD connects the CPU data line and the chip data line according to the chip selection bit width;
step S30, the CPU allocates a base address to the chip selection where the CPLD is located, the CPLD detects the big end mode and the small end mode of the CPU, and the CPLD adjusts the connection sequence of the data line and the address line to the chip according to the big end mode and the small end mode of the CPU;
and step S40, confirming whether the chip is consistent with the CPU in the byte order, and informing the CPLD of the result of consistent byte order release by the CPU.
Specifically, as shown in fig. 8, the data lines LA0 to LA31 and the address lines LD0 to LD31 of the CPU are all connected to the CPLD, and the data lines D0 to D15 and the address lines a0 to a26 of the external chip are also all connected to the CPLD.
The CPU sets the chip select bit width to be 16 bits and informs the CPLD through the register.
According to the chip selection bit width, the CPLD connects the CPU data line LD0 with the chip data line D0 by default, and so on. CPU address line LA0 is not connected to chip, LA1 is connected to chip A0, and so on, as shown in FIGS. 7 and 8.
And the CPU allocates a base address CPLD _ base _ adrs to the chip selection where the CPLD is located.
The CPLD detects the big-end mode and the small-end mode of the CPU. And (CPLD _ base _ adrs +1) addresses are read by the CPU, only one address line given to the CPLD by the CPU is 1, and the other addresses are 0. If LA30 is equal to 1, then the CPU is a big end CPU, otherwise the CPU is a small end CPU;
and the CPLD adjusts the connection sequence of the data line and the address line of the CPLD to the chip according to the size end mode of the CPU. If the mode is the small-end mode, the adjustment is not needed, and if the mode is the large-end mode, the data line exchange sequence LD 15-LD 0 of the CPU is connected with D0-D15 of the chip. The address lines are adjusted to be LA 30-LA 4 connected with A0-A26 of the chip.
And then confirming whether the chip is consistent with the CPU in byte order. The CPU reads the address (cpld _ base _ adrs +2) two bytes to A and the read address (cpld _ base _ adrs +1)2 bytes to B. If A is B, the CPU has the same byte order as the chip, otherwise, the byte order is opposite. The principle is as follows: if the CPU is consistent with the chip size end sequence, the lowest order signal of the 16-bit address is not sent to the chip, and 0 and 1 address access are both 0 addresses of the chip. If the CPU and the chip size end are in reverse order, 0 address accesses 0 address of the chip, 1 is offset address of 0x8000-0000 accessing the chip, and the contents of reading the two are not consistent.
The CPU informs the CPLD of the result of the consistent byte order release, and if the result is consistent, the CPLD does not need to adjust the connection relation between the data line and the address line. If not, the data line exchange sequence LD 15-LD 0 of the CPU is connected with the D0-D15 of the chip. The address lines are adjusted to LA 30-LA 4 to A0-A26 of the chip as shown in FIGS. 9 and 10.
Further, based on the above control method for connecting the CPU and the chip, the present invention further provides a control system for connecting the CPU and the chip, as shown in fig. 8 and 9, the control system for connecting the CPU and the chip includes: a CPU and a chip; the data line and the address line of the CPU are all accessed into the CPLD, and the data line and the address line of the chip are all accessed into the CPLD; the CPU sets chip selection bit width and informs the CPLD through a register, and the CPLD connects a CPU data line with a chip data line according to the chip selection bit width; the CPU allocates a base address to the chip selection where the CPLD is located, the CPLD detects the large end mode and the small end mode of the CPU, and the CPLD adjusts the connection sequence of the data line and the address line to the chip according to the large end mode and the small end mode of the CPU; and confirming whether the chip is consistent with the CPU in byte order or not, and informing the CPLD of the result of consistent byte order release by the CPU.
The invention also provides a storage medium, wherein the storage medium stores a control program for connecting the CPU and the chip, and the control program for connecting the CPU and the chip realizes the steps of the control method for connecting the CPU and the chip when being executed by a processor.
In summary, the present invention provides a method, a system and a storage medium for controlling connection between a CPU and a chip, wherein the method includes: the data line and the address line of the CPU are all accessed into the CPLD, and the data line and the address line of the chip are all accessed into the CPLD; the CPU sets chip selection bit width and informs the CPLD through a register, and the CPLD connects a CPU data line with a chip data line according to the chip selection bit width; the CPU allocates a base address to the chip selection where the CPLD is located, the CPLD detects the large end mode and the small end mode of the CPU, and the CPLD adjusts the connection sequence of the data line and the address line to the chip according to the large end mode and the small end mode of the CPU; and confirming whether the chip is consistent with the CPU in byte order or not, and informing the CPLD of the result of consistent byte order release by the CPU. The invention realizes the automatic matching of the CPU and the address line and the data line of the peripheral chip, and after the CPU is replaced, the size end does not need to be defined again, and the invention only needs to be according to the commonly used connection method of the CPU which is actually used.
Of course, it will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer readable storage medium, and may include the processes of the above method embodiments when executed. The storage medium may be a memory, a magnetic disk, an optical disk, etc.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. A method for controlling connection between a CPU and a chip is characterized in that the method for controlling connection between the CPU and the chip comprises the following steps:
the data line and the address line of the CPU are all accessed into the CPLD, and the data line and the address line of the chip are all accessed into the CPLD;
the CPU sets chip selection bit width and informs the CPLD through a register, and the CPLD connects a CPU data line with a chip data line according to the chip selection bit width;
the CPU allocates a base address to the chip selection where the CPLD is located, the CPLD detects the large end mode and the small end mode of the CPU, and the CPLD adjusts the connection sequence of the data line and the address line to the chip according to the large end mode and the small end mode of the CPU;
and confirming whether the chip is consistent with the CPU in byte order or not, and informing the CPLD of the result of consistent byte order release by the CPU.
2. The CPU and chip connection control device of claim 1, wherein the data line and the address line of the CPU are all connected to the CPLD, and the data line and the address line of the chip are all connected to the CPLD, specifically comprising:
data lines LA 0-LA 31 and address lines LD 0-LD 31 of the CPU are all connected into the CPLD, and data lines D0-D15 and address lines A0-A26 of the chip are all connected into the CPLD.
3. The CPU and chip connection control device according to claim 2, wherein the CPU sets a chip select bit width and notifies the CPLD through a register, and the CPLD connects the CPU data line and the chip data line according to the chip select bit width, specifically comprising:
the CPU sets the chip selection bit width 16 bits and informs the CPLD through the register;
according to the chip selection bit width, the CPLD connects a CPU data line LD0 with a chip data line D0 by default, a CPU address line LA0 is not connected with the chip, and LA1 is connected with a chip A0.
4. The device according to claim 3, wherein the CPU allocates a base address to the chip select where the CPLD is located, the CPLD detects a big-end mode of the CPU, and the CPLD adjusts a connection sequence of the data line and the address line to the chip according to the big-end mode of the CPU, specifically comprising:
the CPU allocates a base address CPLD _ base _ adrs to the chip selection where the CPLD is located;
the CPLD detects the mode of the big end and the small end of the CPU;
and the CPLD adjusts the connection sequence of the data line and the address line to the chip according to the large end mode and the small end mode of the CPU.
5. The CPU and chip connection control device according to claim 4, wherein the CPLD detects a size end mode of the CPU, and specifically includes:
the CPU reads the address of CPLD _ base _ adrs +1, only one address line provided by the CPU to the CPLD is 1, and the other address lines are 0;
if LA30 is equal to 1, the CPU is the big end CPU, otherwise it is the small end CPU.
6. The CPU and chip connection control device according to claim 5, wherein the CPLD adjusts the connection sequence of the data lines and the address lines to the chip according to the CPU big-end mode, and specifically includes:
if the mode is the small-end mode, no adjustment is made;
if the mode is large-end mode, the data line switching sequence LD 15-LD 0 of the CPU is connected with the D0-D15 of the chip, and the address lines are adjusted to LA 30-LA 4 connected with the A0-A26 of the chip.
7. The CPU and chip connection control device according to claim 6, wherein the determining whether the chip and the CPU have the same byte order and the CPU informs the CPLD of a result of the release of the same byte order specifically includes:
reading two bytes of an address cpld _ base _ adrs +2 to A and reading 2 bytes of an address cpld _ base _ adrs +1 to B by the CPU;
if A is B, the CPU has the same byte order as the chip, otherwise, the byte order is opposite;
if the byte order of the chip is consistent with that of the CPU, the CPLD does not need to adjust the connection relation between the data line and the address line;
if the chip and the CPU have inconsistent byte order, the data line exchange sequence LD 15-LD 0 of the CPU is connected with the D0-D15 of the chip, and the address lines are adjusted to LA 30-LA 4 connected with the A0-A26 of the chip.
8. The CPU and chip attach control device of claim 7, wherein said determining whether the chip is endian with the CPU comprises
If the CPU is consistent with the sequence of the chip size end, the lowest order signal of the 16-bit address is not sent to the chip, and the 0 and 1 address access is the 0 address of the chip;
if the CPU is in reverse order from the chip size side, then the 0 address accesses the 0 address of the chip, and 1 accesses the offset address of 0x8000-0000 of the chip.
9. A control system for connecting a CPU and a chip is characterized in that the control system for connecting the CPU and the chip comprises: a CPU and a chip;
the data line and the address line of the CPU are all accessed into the CPLD, and the data line and the address line of the chip are all accessed into the CPLD; the CPU sets chip selection bit width and informs the CPLD through a register, and the CPLD connects a CPU data line with a chip data line according to the chip selection bit width; the CPU allocates a base address to the chip selection where the CPLD is located, the CPLD detects the large end mode and the small end mode of the CPU, and the CPLD adjusts the connection sequence of the data line and the address line to the chip according to the large end mode and the small end mode of the CPU; and confirming whether the chip is consistent with the CPU in byte order or not, and informing the CPLD of the result of consistent byte order release by the CPU.
10. A storage medium storing a CPU and chip connection control program, which when executed by a processor implements the steps of the CPU and chip connection control method according to any one of claims 1 to 8.
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| CN112685354A (en) * | 2020-12-31 | 2021-04-20 | 中国科学院长春光学精密机械与物理研究所 | Channel type FPGA (field programmable Gate array) on-chip extensible bus and data processing method thereof |
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| CN112685354A (en) * | 2020-12-31 | 2021-04-20 | 中国科学院长春光学精密机械与物理研究所 | Channel type FPGA (field programmable Gate array) on-chip extensible bus and data processing method thereof |
| CN112685354B (en) * | 2020-12-31 | 2022-04-19 | 中国科学院长春光学精密机械与物理研究所 | Channel type FPGA (field programmable Gate array) on-chip extensible bus and data processing method thereof |
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