CN1109966C - 用于在并行处理中处理推测性指令例外的方法和装置 - Google Patents
用于在并行处理中处理推测性指令例外的方法和装置 Download PDFInfo
- Publication number
- CN1109966C CN1109966C CN96100643A CN96100643A CN1109966C CN 1109966 C CN1109966 C CN 1109966C CN 96100643 A CN96100643 A CN 96100643A CN 96100643 A CN96100643 A CN 96100643A CN 1109966 C CN1109966 C CN 1109966C
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- exception
- register
- predictive
- speculative instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US377,563 | 1995-01-24 | ||
US08/377,563 US5799179A (en) | 1995-01-24 | 1995-01-24 | Handling of exceptions in speculative instructions |
US377563 | 1995-01-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1136182A CN1136182A (zh) | 1996-11-20 |
CN1109966C true CN1109966C (zh) | 2003-05-28 |
Family
ID=23489627
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN96100643A Expired - Fee Related CN1109966C (zh) | 1995-01-24 | 1996-01-12 | 用于在并行处理中处理推测性指令例外的方法和装置 |
Country Status (10)
Country | Link |
---|---|
US (1) | US5799179A (pl) |
EP (1) | EP0804759B1 (pl) |
JP (1) | JP3093624B2 (pl) |
KR (1) | KR100290269B1 (pl) |
CN (1) | CN1109966C (pl) |
CA (1) | CA2203124C (pl) |
CZ (1) | CZ293714B6 (pl) |
DE (1) | DE69600995T2 (pl) |
PL (1) | PL181901B1 (pl) |
WO (1) | WO1996023254A1 (pl) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100451950C (zh) * | 2004-08-27 | 2009-01-14 | 松下电器产业株式会社 | 信息处理装置、例外控制电路 |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5778219A (en) * | 1990-12-14 | 1998-07-07 | Hewlett-Packard Company | Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations |
US6185668B1 (en) * | 1995-12-21 | 2001-02-06 | Intergraph Corporation | Method and apparatus for speculative execution of instructions |
US5872990A (en) * | 1997-01-07 | 1999-02-16 | International Business Machines Corporation | Reordering of memory reference operations and conflict resolution via rollback in a multiprocessing environment |
EP1031076A1 (en) * | 1997-10-13 | 2000-08-30 | Institute for the Development of Emerging Architectures, L.L.C. | Method and apparatus for optimizing execution of load and store instructions |
US6505296B2 (en) | 1997-10-13 | 2003-01-07 | Hewlett-Packard Company | Emulated branch effected by trampoline mechanism |
US6044454A (en) * | 1998-02-19 | 2000-03-28 | International Business Machines Corporation | IEEE compliant floating point unit |
US6260190B1 (en) * | 1998-08-11 | 2001-07-10 | Hewlett-Packard Company | Unified compiler framework for control and data speculation with recovery code |
US6301705B1 (en) * | 1998-10-01 | 2001-10-09 | Institute For The Development Of Emerging Architectures, L.L.C. | System and method for deferring exceptions generated during speculative execution |
US6519694B2 (en) * | 1999-02-04 | 2003-02-11 | Sun Microsystems, Inc. | System for handling load errors having symbolic entity generator to generate symbolic entity and ALU to propagate the symbolic entity |
US6453463B1 (en) | 1999-06-07 | 2002-09-17 | Sun Microsystems, Inc. | Method and apparatus for providing finer marking granularity for fields within objects |
US6513109B1 (en) | 1999-08-31 | 2003-01-28 | International Business Machines Corporation | Method and apparatus for implementing execution predicates in a computer processing system |
US6487716B1 (en) | 1999-10-08 | 2002-11-26 | International Business Machines Corporation | Methods and apparatus for optimizing programs in the presence of exceptions |
US6658555B1 (en) * | 1999-11-04 | 2003-12-02 | International Business Machines Corporation | Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline |
US6766447B1 (en) * | 2000-01-25 | 2004-07-20 | Dell Products L.P. | System and method of preventing speculative reading during memory initialization |
US6631460B1 (en) | 2000-04-27 | 2003-10-07 | Institute For The Development Of Emerging Architectures, L.L.C. | Advanced load address table entry invalidation based on register address wraparound |
US7240186B2 (en) * | 2001-07-16 | 2007-07-03 | Hewlett-Packard Development Company, L.P. | System and method to avoid resource contention in the presence of exceptions |
US7565658B2 (en) * | 2001-10-08 | 2009-07-21 | Telefonaktiebolaget L M Ericsson (Publ) | Hidden job start preparation in an instruction-parallel processor system |
US7114059B2 (en) * | 2001-11-05 | 2006-09-26 | Intel Corporation | System and method to bypass execution of instructions involving unreliable data during speculative execution |
JP3900485B2 (ja) * | 2002-07-29 | 2007-04-04 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 最適化装置、コンパイラプログラム、最適化方法、及び記録媒体 |
AU2003283680A1 (en) * | 2002-12-04 | 2004-06-23 | Koninklijke Philips Electronics N.V. | Software-based control of microprocessor power dissipation |
US7263600B2 (en) * | 2004-05-05 | 2007-08-28 | Advanced Micro Devices, Inc. | System and method for validating a memory file that links speculative results of load operations to register values |
JP4806402B2 (ja) * | 2005-04-21 | 2011-11-02 | パナソニック株式会社 | プログラム難読化装置及び難読化方法 |
US7860847B2 (en) * | 2006-11-17 | 2010-12-28 | Microsoft Corporation | Exception ordering in contention management to support speculative sequential semantics |
US8010550B2 (en) | 2006-11-17 | 2011-08-30 | Microsoft Corporation | Parallelizing sequential frameworks using transactions |
US8024714B2 (en) | 2006-11-17 | 2011-09-20 | Microsoft Corporation | Parallelizing sequential frameworks using transactions |
JP5154119B2 (ja) * | 2007-03-26 | 2013-02-27 | テレフオンアクチーボラゲット エル エム エリクソン(パブル) | プロセッサ |
US8458684B2 (en) * | 2009-08-19 | 2013-06-04 | International Business Machines Corporation | Insertion of operation-and-indicate instructions for optimized SIMD code |
US20110047358A1 (en) * | 2009-08-19 | 2011-02-24 | International Business Machines Corporation | In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication |
US8825982B2 (en) | 2010-06-10 | 2014-09-02 | Global Supercomputing Corporation | Storage unsharing |
US9996348B2 (en) | 2012-06-14 | 2018-06-12 | Apple Inc. | Zero cycle load |
US11068271B2 (en) | 2014-07-28 | 2021-07-20 | Apple Inc. | Zero cycle move using free list counts |
CN104598808B (zh) * | 2015-01-08 | 2018-02-16 | 中国科学院信息工程研究所 | 基于寄存器架构的Android应用完整性验证方法 |
US10120656B1 (en) | 2017-11-07 | 2018-11-06 | Bank Of America Corporation | Robotic process automation system for functional evaluation and improvement of back end instructional constructs |
US11416254B2 (en) | 2019-12-05 | 2022-08-16 | Apple Inc. | Zero cycle load bypass in a decode group |
US11436830B2 (en) | 2020-03-11 | 2022-09-06 | Bank Of America Corporation | Cognitive robotic process automation architecture |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4539635A (en) * | 1980-02-11 | 1985-09-03 | At&T Bell Laboratories | Pipelined digital processor arranged for conditional operation |
US5487156A (en) * | 1989-12-15 | 1996-01-23 | Popescu; Valeri | Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched |
FR2656442B1 (fr) * | 1989-12-21 | 1994-07-29 | Bull Sa | Processeur a plusieurs unites microprogrammees avec mecanisme d'execution anticipee des instructions. |
US5303355A (en) * | 1991-03-27 | 1994-04-12 | Motorola, Inc. | Pipelined data processor which conditionally executes a predetermined looping instruction in hardware |
US5479616A (en) * | 1992-04-03 | 1995-12-26 | Cyrix Corporation | Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception |
JPH09500989A (ja) * | 1993-05-14 | 1997-01-28 | インテル・コーポレーション | 分岐ターゲット・バッファにおける推論履歴 |
US5421022A (en) * | 1993-06-17 | 1995-05-30 | Digital Equipment Corporation | Apparatus and method for speculatively executing instructions in a computer system |
US5428807A (en) * | 1993-06-17 | 1995-06-27 | Digital Equipment Corporation | Method and apparatus for propagating exception conditions of a computer system |
US5537559A (en) * | 1994-02-08 | 1996-07-16 | Meridian Semiconductor, Inc. | Exception handling circuit and method |
US5634023A (en) * | 1994-07-01 | 1997-05-27 | Digital Equipment Corporation | Software mechanism for accurately handling exceptions generated by speculatively scheduled instructions |
US5673426A (en) * | 1995-02-14 | 1997-09-30 | Hal Computer Systems, Inc. | Processor structure and method for tracking floating-point exceptions |
-
1995
- 1995-01-24 US US08/377,563 patent/US5799179A/en not_active Expired - Fee Related
-
1996
- 1996-01-09 WO PCT/EP1996/000060 patent/WO1996023254A1/en active IP Right Grant
- 1996-01-09 PL PL96321542A patent/PL181901B1/pl not_active IP Right Cessation
- 1996-01-09 EP EP96900925A patent/EP0804759B1/en not_active Expired - Lifetime
- 1996-01-09 KR KR1019970705171A patent/KR100290269B1/ko not_active IP Right Cessation
- 1996-01-09 CZ CZ19972084A patent/CZ293714B6/cs not_active IP Right Cessation
- 1996-01-09 CA CA002203124A patent/CA2203124C/en not_active Expired - Fee Related
- 1996-01-09 DE DE69600995T patent/DE69600995T2/de not_active Expired - Lifetime
- 1996-01-12 CN CN96100643A patent/CN1109966C/zh not_active Expired - Fee Related
- 1996-01-18 JP JP08006386A patent/JP3093624B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100451950C (zh) * | 2004-08-27 | 2009-01-14 | 松下电器产业株式会社 | 信息处理装置、例外控制电路 |
Also Published As
Publication number | Publication date |
---|---|
CZ293714B6 (cs) | 2004-07-14 |
EP0804759A1 (en) | 1997-11-05 |
EP0804759B1 (en) | 1998-11-18 |
DE69600995T2 (de) | 1999-07-08 |
US5799179A (en) | 1998-08-25 |
KR100290269B1 (ko) | 2001-05-15 |
KR19980701774A (ko) | 1998-06-25 |
CA2203124A1 (en) | 1996-08-01 |
PL181901B1 (pl) | 2001-10-31 |
PL321542A1 (en) | 1997-12-08 |
CA2203124C (en) | 2002-11-19 |
JP3093624B2 (ja) | 2000-10-03 |
CZ208497A3 (en) | 1997-12-17 |
CN1136182A (zh) | 1996-11-20 |
WO1996023254A1 (en) | 1996-08-01 |
DE69600995D1 (de) | 1998-12-24 |
JPH08263287A (ja) | 1996-10-11 |
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C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20030528 Termination date: 20100212 |