CN110995317A - Power line master-slave mode zero-crossing communication system - Google Patents
Power line master-slave mode zero-crossing communication system Download PDFInfo
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Abstract
The invention relates to a power line master-slave zero-crossing communication system, which comprises a master and a slave communication system consisting of a plurality of slaves, wherein the master sends slave addresses and commands coded by a cycle zero-crossing on-off signal sequence through a power line for the slaves to decode and execute, the slaves do not send information, and the system has a simple structure and is reliable in communication.
Description
The technical field is as follows:
the invention relates to a power line master-slave zero-crossing communication system, which comprises a master and a slave communication system consisting of a plurality of slaves, wherein the master sends slave addresses and commands coded by a cycle zero-crossing on-off signal sequence through a power line for the slaves to decode and execute, the slaves do not send information, and the system has a simple structure and is reliable in communication.
(II) background technology:
at present, power line communication mainly refers to power line carrier communication and bidirectional power frequency communication, but a distribution transformer has a blocking effect on power carrier signals, so that the power carrier signals can be transmitted only in one distribution transformer area and can be transmitted only on a single-phase power line. In practical applications, when the load on the power line is heavy, only tens of meters can be transmitted.
The TWACS adds a modulation signal in the zero crossing area of the fundamental wave of the power frequency voltage and uses the distortion signal of the voltage or current waveform in the area to carry information. The signal detection calculation is complex and rigorous, the interference is serious, the detection result is influenced, and the wide application is difficult.
The power line communication system is complex in structure and expensive in manufacturing cost.
The applicant and the inventor have referred to power line communication technology such as half-wave power line communication in the previously filed patent.
(III) the invention content:
a master-slave zero-crossing communication system of a power line comprises a master machine and a plurality of slave machines, wherein the master machine and each slave machine are connected to a special single-phase power line and are communicated through the power line under the control of the master machine. The method is characterized in that the master machine sends slave machine addresses and commands coded by sequence signals of zero-crossing time power-off cycles for the slave machines to receive and decode to execute corresponding operations, and the slave machines do not send information.
And during the period that the host sends the slave address and the command coded by the sequence signal of the zero-crossing time power-off cycle, the slave is powered off by the capacitor of the power supply module to store energy and supply power.
And a communication switch formed by bidirectional thyristors is connected in series at the starting end of the same single-phase power line, namely one end of the host, and the host controls the power line to be connected into or disconnected from a commercial power grid.
The master machine and the slave machine reject interference signals under the control of the cycle detection circuit to detect real cycle signals. And the slave machine receives the command sent by the host machine after detecting the cycle and executes corresponding operation.
The cycle detection circuit comprises two zero-crossing detection circuits and two voltage comparators, wherein one of the two voltage comparators is a positive voltage comparator, and the other one of the two voltage comparators is a negative voltage comparator. One of the two zero-crossing detection circuits is used for positive zero-crossing detection, and the other is used for negative zero-crossing detection. The zero-crossing detection circuit and the voltage comparator are both composed of hysteresis voltage comparators.
The master machine is respectively arranged on the power line at one side of the commercial power supply of the communication switch and one side of the commercial power controlled side of the communication switch, the slave machine is arranged on the power line at one side of the commercial power controlled side of the communication switch, the master machine and the slave machine are respectively connected with the power line at the corresponding side of the communication switch through resistors and then divided into four paths, wherein two paths are respectively connected with the signal input end of the positive zero-crossing detection and the signal input end of the positive voltage comparator, and the other two paths are respectively connected with the signal input end of the negative zero-crossing detection and the signal input end.
The zero-crossing detection circuit and the voltage comparator are both formed by hysteresis voltage comparators. The positive zero-crossing detection refers to positive half-cycle zero-crossing detection of a cycle wave, and the negative zero-crossing detection refers to negative half-cycle zero-crossing detection of the cycle wave.
The signal input function of the host and the slave is completed by a cycle detection circuit, namely a zero-crossing detection circuit and a voltage comparator on the power line at the side where the commercial power is controlled.
The zero-crossing detection circuit and the voltage comparator both comprise filter circuits, and reference voltage of the filter circuits is provided by the voltage stabilizing circuit. The reference voltage of the positive zero-crossing detection and the reference voltage of the negative zero-crossing detection are set to be 1V-2V; the reference voltage set by the positive voltage comparator and the reference voltage set by the negative voltage comparator are the same and are set at the positive or negative voltage of 20V-30V of the corresponding cycle; the voltage of the cycle voltage is reduced by the resistor and then the jump of the level of the output end of the voltage comparator is controlled.
The master machine and the slave machine are respectively provided with a cycle number counter detected by a voltage comparator, the output end of a primary positive voltage comparator jumps from low level to high level, the output end of an adjacent primary negative voltage comparator jumps from high level to low level to form a cycle, and the master machine and the slave machine count the cycle of each signal frame.
Detection of cycle signals: when the positive half cycle of the power grid cycle is input into the positive voltage comparator, the output end of the positive voltage comparator jumps from low level to high level and then jumps from high level to low level, and the high level holding time of the positive voltage comparator is a fixed value for the power grid cycle and is called as positive level holding time. Similarly, when the negative half cycle of the power grid cycle is converted by the inverter and then input to the negative voltage comparator, the output end of the negative voltage comparator jumps from low level to high level and then jumps from high level to low level, and the high level holding time of the negative voltage comparator is a fixed value relative to the power grid cycle and is called as negative level holding time.
When the host does not send information, the output end of the positive zero-crossing detection jumps from low level to high level, and then the output end of the adjacent negative zero-crossing detection jumps from low level to high level, which is the measured half-wave time of the cycle.
When the host sends a frame of instruction or information to the slave, when the slave detects that the high-level holding time of the positive voltage comparator is within the set error range of the average value of the positive-level holding time, the detected cycle is a real positive half cycle; similarly, when the slave detects that the high level holding time of the negative voltage comparator is within the setting error range of the average value of the negative level holding time, the detected cycle is a real negative half cycle.
The average value of the positive level holding time and the average value of the negative level holding time are stored in the corresponding memories on the basis of the calculated values, and then are replaced by the measured average values, and are measured and replaced once a working day. The method comprises the steps that a group of continuous real cycle half-wave time, positive level holding time and negative level holding time detected by a host when information is not sent are detected, 10 groups of continuous real cycle half-wave time, positive level holding time and negative level holding time are detected, the average values of the 10 groups of continuous real cycle half-wave time, the positive level holding time and the negative level holding time are respectively taken to replace corresponding average values in a memory, and the average values are. The setting error range of the level holding time of the host and the slave is uniformly set by the host in proportion according to the allowable cycle time error range of the power grid.
Power-off of zero-crossing time of cycle: the master machine sends a zero-crossing time power-off coded signal in a cycle zero-crossing period, or the slave machine receives a zero-crossing time power-off coded signal sent by the master machine, wherein the zero-crossing time means that when the master machine sends a zero-crossing time power-off signal, the communication switch is powered off when the output voltage of the negative voltage comparator jumps from high to low, the timer starts to time, the communication switch is powered on and times are finished when the output voltage of the adjacent positive voltage comparator jumps from low to high, the time is measured for several times, the average value of the time is taken as a time interval T1 of cycle zero-crossing time power-off, the T1 is obtained by timing detection of the master machine and sent to the slave machine, and the slave machine is stored in a memory for.
Sending of host signals: the host comprises a power supply module, a singlechip, a communication switch and a cycle detection circuit; the slave machine comprises a power supply module, a singlechip and a cycle detection circuit.
When the host sends the slave address and the command coded by the sequence signal of the zero-crossing time power-off cycle, the host simultaneously receives the sent sequence coded signal of the zero-crossing time power-off cycle on the power line at the side where the commercial power is controlled and compares and identifies the sequence coded signal, and if errors are found, the slave retransmits the sequence coded signal.
The communication switch controlled by the single chip microcomputer in the host computer is used as a signal transmitter, and the signal transmission is realized under the control of the host computer cycle detection circuit. A singlechip in the slave receives a cycle signal through a cycle detection circuit, eliminates interference, and correspondingly marks a cycle positive and negative half-cycle zero-crossing time power-off signal of a received signal frame; and cycle count values corresponding to the positive and negative half cycles of the cycle are stored in a memory together, and the corresponding instructions are executed after decoding. The host sends the cycle zero-crossing time power-off cycle according to the coding of the information to be sent and the coding structure of the information.
A signal frame contains a start bit, a data bit and a stop bit, where the data bit contains several hexadecimal characters. Each bit of a signal frame is coded by the combination of a value represented by the positive half cycle zero crossing power-off and a value represented by the negative half cycle zero crossing power-off.
When the host detects the jump of the output voltage of the negative voltage comparator from high to low on the side of a mains supply of the communication switch, the communication switch is switched off, and the communication switch is switched on when the jump of the output voltage of the adjacent positive voltage comparator from low to high is detected, which is called as positive half cycle zero crossing time power failure; when the host computer detects that the output voltage of the positive voltage comparator jumps from high to low, the communication switch is switched off, and then when the output voltage of the adjacent negative voltage comparator jumps from low to high, the communication switch is switched on to power off for the zero-crossing time of the negative half cycle.
Signal frame format of the transceiving signal: the method comprises the steps that the power-off of the zero-crossing time of the positive half cycle represents a numerical value 1, the power-off of the zero-crossing time of the negative half cycle represents a numerical value 2, and a signal frame is formed by the combination codes of the numerical value 1, the numerical value 2 and the zero-crossing of the cycle without power-off and is used for representing hexadecimal characters. The encoding of each hexadecimal character takes 2 to 6 cycles, with the positive and negative half-cycle zero-crossings of the last cycle being unpowered as an end marker for one hexadecimal character encoding.
Appointing: in the following encoding of the signal frame format, the "cycle" in the encoding of a hexadecimal character or control bit indicates that the positive half cycle zero crossing time of the cycle is powered off while the negative half cycle zero crossing time is powered off. The "positive half cycle of the cycle" and "negative half cycle of the cycle" represent the positive half cycle zero crossing time power off of the cycle and the negative half cycle zero crossing time power off of the cycle.
If the cycle occupied by a hexadecimal character is not an integer, the zero crossing of the cycle at the end of coding is not powered off or the zero crossing of the negative half cycle is not powered off, the data bit is represented by the hexadecimal character, and the coding of the hexadecimal character is as follows:
the cycle number in the data bits described below is counted from the 1 st cycle of the data bit.
Data bit: the positive half cycle of the 1 st cycle and the negative half cycle of the 2 nd cycle are characters 0; the positive half cycle of the 1 st cycle is a character 1; the negative half cycle of the 1 st cycle is a character 2; the 1 st cycle is character 3; the positive half cycles of the 1 st cycle and the 2 nd cycle are characters 4; the negative half cycle of the 1 st cycle and the 2 nd cycle are characters 5; the 1 st cycle and the 2 nd cycle are characters 6; the positive half cycles of the 1 st cycle, the 2 nd cycle and the 3 rd cycle are characters 7; the negative half cycle of the 1 st cycle and the 2 nd cycle and the 3 rd cycle are characters 8; the 1 st cycle, the 2 nd cycle and the 3 rd cycle are characters 9; the positive half cycles of the 1 st, 2 nd, 3 rd and 4 th cycles are characters A; the negative half cycle of the 1 st cycle and the 2 nd, 3 rd and 4 th cycles are characters B; the 1 st, 2 nd, 3 th and 4 th cycles are characters C; the positive half cycles of the 1 st, 2 nd, 3 rd, 4 th and 5 th cycles are characters D; the negative half cycle of the 1 st cycle and the 2 nd, 3 rd, 4 th and 5 th cycles are characters E; the 1 st, 2 nd, 3 rd, 4 th and 5 th cycles are the characters F.
The positive half cycle of the 1 st cycle and the positive half cycle of the 2 nd cycle of the signal frame represent command frame start bits; the negative half cycle of the 1 st cycle and the negative half cycle of the 2 nd cycle of the signal frame represent information frame start bits; the first 1 cycle is empty and constitutes a stop bit with the next 1 cycle minus half cycle. A hexadecimal character comprises an end marker that takes up a maximum of 6 cycles, and in addition, the start bit and stop bit each take up 2 cycles. Here, the first hexadecimal character is set to indicate the slave address, and "0" indicates that the slave address is not specified. The data bits in the signal frame may be represented by one or several hexadecimal characters in order to express various codes, chinese characters, simple figures, etc.
Receiving a slave signal: when the master machine and the slave machine detect that the output voltage of the negative voltage comparator and the output voltage of the negative zero-crossing detection jump from high to low simultaneously on a power line at the commercial power controlled side of the communication switch, the timer starts timing, the timing is finished when the output voltage of the adjacent positive voltage comparator and the output voltage of the positive zero-crossing detection jump from low to high simultaneously, and if the timing value is in the allowable error range of T1, the power-off of the zero-crossing time of the positive half cycle is received; similarly, when the slave detects that the output voltage of the positive voltage comparator and the output voltage of the positive zero-crossing detection simultaneously jump from high to low, the timer starts to time, and then immediately detects that the output voltage of the adjacent negative voltage comparator and the output voltage of the negative zero-crossing detection simultaneously jump from low to high, the timer finishes timing, and if the timing value is in the allowable error range of T1, the timer indicates that the negative half-cycle zero-crossing time is received and power is cut off.
(IV) description of the drawings:
fig. 1 is a schematic circuit structure diagram of a power line master-slave zero-crossing communication system.
(V) specific embodiment:
fig. 1 is a schematic circuit structure diagram of a power line master-slave zero-crossing communication system, which is applied to Chinese character placard control as an embodiment. The host A comprises a power supply module 12, a communication switch 11, a singlechip 14, a cycle detection circuit 13 and a keyboard display module 15; the slave B comprises a power supply module 21, a singlechip 22, a cycle detection circuit 24 and a Chinese character placard 23.
The display of each Chinese character placard 23 is controlled by using power line communication, and the system is low in cost and easy to maintain.
One slogan is composed of a plurality of Chinese character slogan boards 23, each Chinese character slogan board 23 controls the Chinese character display of an LED lamp in the Chinese character slogan board 23 by a single chip microcomputer 22 in a corresponding slave computer B, each Chinese character slogan board 23 displays one Chinese character or a plurality of Chinese characters, a host computer A stores a plurality of slogan data, each slogan is transmitted to a corresponding slave computer B by a single chip microcomputer 14 in the host computer A, and the slogan and the display mode can be manually input through a keyboard display module 15 in the host computer A.
The master machine A transmits slave machine addresses coded by sequence signals of zero-crossing time power-off cycles and sequentially displayed slogan contents and display modes to the slave machines B through the power lines, and each slave machine B controls the display of an LED lamp in the Chinese character slogan board 23 after receiving information and instructions sent by the master machine A.
Claims (3)
1. A method for realizing a power line master-slave zero-crossing communication system comprises a master machine and a plurality of slave machines, wherein the master machine and each slave machine are connected with a special single-phase power line and communicate through a power line under the control of the master machine, and the method is characterized in that:
the host machine sends slave machine addresses and instructions coded by sequence signals of zero-crossing time power-off cycles for the slave machines to receive and decode to execute corresponding operations, and the slave machines do not send information;
when the host machine sends a zero-crossing time power-off coded signal in a cycle zero-crossing period or the slave machine receives a zero-crossing time power-off coded signal sent by the host machine, the zero-crossing time means that when the host machine sends a zero-crossing time power-off signal, the communication switch is powered off when the output voltage of a negative voltage comparator jumps from high to low, a timer starts to time, the communication switch is powered on when the output voltage of an adjacent positive voltage comparator jumps from low to high, the time is ended, and the average value of the time after several measurements is taken as a cycle zero-crossing time power-off time interval T1;
the method comprises the steps that a positive half cycle zero-crossing time power-off representation value 1 and a negative half cycle zero-crossing time power-off representation value 2 of a cycle are carried out, and a signal frame is formed by the combination codes of the value 1, the value 2 and the cycle zero-crossing power-off representation value, and is used for representing hexadecimal characters; the code of each hexadecimal character occupies 2 to 6 cycles, wherein the positive and negative half-cycle zero-crossing of the last cycle is not powered off and is used as an end mark of the hexadecimal character code;
the positive half cycle of the 1 st cycle and the positive half cycle of the 2 nd cycle of the signal frame represent command frame start bits; the negative half cycle of the 1 st cycle and the negative half cycle of the 2 nd cycle of the signal frame represent information frame start bits; the first 1 cycle is empty and forms a stop bit with the negative half cycle of the next 1 cycle; a hexadecimal character comprises an end mark occupying 6 cycles at most, and in addition, a start bit and a stop bit respectively occupy 2 cycles; here, the first hexadecimal character is set to represent the slave address, and "0" represents that the slave address is not specified; the data bits in the signal frame may be represented by one or several hexadecimal characters to express various codes, Chinese characters, simple figures.
2. The method of claim 1, wherein the master sends slave addresses and commands encoded by the sequence of zero-crossing power-down cycles for the slaves to decode and perform the corresponding operations, comprising the steps of:
receiving and transmitting host signals: when the host detects the jump of the output voltage of the negative voltage comparator from high to low on the side of a mains supply of the communication switch, the communication switch is switched off, and the communication switch is switched on when the jump of the output voltage of the adjacent positive voltage comparator from low to high is detected, which is called as positive half cycle zero crossing time power failure; when the host detects that the output voltage of the positive voltage comparator jumps from high to low, the communication switch is switched off, and then the communication switch is switched on when the output voltage of the adjacent negative voltage comparator jumps from low to high, so that the power is cut off at the zero-crossing time of the negative half cycle;
receiving a slave signal: when the master machine and the slave machine detect that the output voltage of the negative voltage comparator and the output voltage of the negative zero-crossing detection jump from high to low simultaneously on a power line at the commercial power controlled side of the communication switch, the timer starts timing, the timing is finished when the output voltage of the adjacent positive voltage comparator and the output voltage of the positive zero-crossing detection jump from low to high simultaneously, and if the timing value is in the allowable error range of T1, the power-off of the zero-crossing time of the positive half cycle is received; similarly, when the slave detects that the output voltage of the positive voltage comparator and the output voltage of the positive zero-crossing detection simultaneously jump from high to low, the timer starts to time, and then immediately detects that the output voltage of the adjacent negative voltage comparator and the output voltage of the negative zero-crossing detection simultaneously jump from low to high, the timer finishes timing, and if the timing value is in the allowable error range of T1, the timer indicates that the negative half-cycle zero-crossing time is received and power is cut off.
3. An apparatus of a power line zero-crossing communication system,
the host comprises a power module, a communication switch, a singlechip and a cycle detection circuit; the slave machine comprises a power supply module, a singlechip and a cycle detection circuit;
a communication switch composed of bidirectional thyristors is connected in series with the starting end of the same single-phase power line, namely one end of the host, a singlechip in the host controls the power line to be connected with or disconnected from a commercial power grid, and the communication switch is used as a host signal transmitter;
the cycle detection circuit comprises two zero-crossing detection circuits and two voltage comparators, wherein one of the two voltage comparators is a positive voltage comparator, the other one of the two zero-crossing detection circuits is a negative voltage comparator, one of the two zero-crossing detection circuits is positive zero-crossing detection, the other one of the two zero-crossing detection circuits is negative zero-crossing detection, and the zero-crossing detection circuit and the voltage comparators are formed by hysteresis voltage comparators;
the master machine is respectively arranged on the power line at one side of the commercial power supply of the communication switch and one side of the commercial power controlled side of the communication switch, the slave machine is arranged on the power line at one side of the commercial power controlled side of the communication switch, the master machine and the slave machine are respectively connected with the power line at the corresponding side of the communication switch through resistors and then divided into four paths, wherein two paths are respectively connected with the signal input end of the positive zero-crossing detection and the signal input end of the positive voltage comparator, and the other two paths are respectively connected with the signal input end of the negative zero-crossing detection and the signal input end.
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| US10211883B1 (en) * | 2018-04-02 | 2019-02-19 | Unilux Inc. | Power line communication system of closed circuit |
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| CN102571150A (en) * | 2011-03-22 | 2012-07-11 | 张广涵 | Time-sharing communication system on basis of power grid |
| CN102929316A (en) * | 2012-11-12 | 2013-02-13 | 张金木 | Measurement and control system for temperature, humidity and illuminance |
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Effective date of registration: 20230329 Address after: 518000, 309, Huashenghui Commercial Building, Jinhai Road, Yantian Community, Xixiang Street, Bao'an District, Shenzhen, Guangdong Province Patentee after: Shenzhen Yuqian Technology Co.,Ltd. Address before: 350208 shop 906, building 4, hardware furniture and building materials market, Heshang Town, Changle District, Fuzhou City, Fujian Province Patentee before: FUZHOU ZHUNDIAN INFORMATION TECHNOLOGY Co.,Ltd. |