CN110994540A

CN110994540A - Dual-redundancy control system of airborne direct current control protector

Info

Publication number: CN110994540A
Application number: CN201911227216.0A
Authority: CN
Inventors: 陈原野
Original assignee: Guiyang Aviation Electrical Machinery Co Ltd
Current assignee: Guiyang Aviation Electrical Machinery Co Ltd
Priority date: 2019-12-04
Filing date: 2019-12-04
Publication date: 2020-04-10

Abstract

The invention discloses a dual-redundancy control system of an airborne direct-current control protector, which comprises a power supply and an upper computer; the input end of the power supply is connected with a first control authority switching circuit and a second control authority switching circuit respectively, and the input end of the first control authority switching circuit is connected with a DSP control unit; the output end of the DSP control unit is connected with the second control authority switching circuit, the output end of the DSP control unit is connected with an FPGA interface processing unit, and the input end of the FPGA interface processing unit is connected with an upper computer through an RS422 communication module. The invention has the double-control channel control framework of the DSP + FPGA framework, has stronger safety and higher reliability, and protects the on-board power utilization safety.

Description

Dual-redundancy control system of airborne direct current control protector

Technical Field

The invention relates to the technical field of airplane power distribution devices, in particular to a dual-redundancy control system of an airborne direct-current control protector.

Background

In the airplane direct-current power supply system, 115V alternating current on the airplane passes through a TRU or other conversion devices and then outputs 28V direct current for supplying power to loads on the airplane. In order to protect the power consumption safety and power consumption quality of the load equipment at the last stage of the motor, the fault detection and protection of the direct current power supply are important, faults or alarm detection such as reverse flow, short circuit, overvoltage, undervoltage and pulsation generally exist according to the failure mode of the conversion device and the power consumption characteristics of the system, and a product for realizing the functions is generally called as a protection power distribution device or a control protector.

At the present stage, electrical equipment develops towards digitalization, automation and precision, the requirement of the equipment on the electricity quality is higher and higher, and meanwhile, the requirement on the reliability of a control protector product is higher and higher under the complex service environment and electromagnetic interference environment on the machine.

At present, the control protector product only adopts single channel control framework basically, and this kind of mode has economy, simple, easy advantage of realizing, but after product control channel trouble, will lead to whole product function to lose, and then influences the last back level consumer of machine, can influence the task completion or the safety on the machine seriously.

Disclosure of Invention

The invention aims to provide a dual-redundancy control system of an airborne direct current control protector, which aims to solve the problems that the function of the whole product is lost, the rear-stage electric equipment on a machine is influenced, and the task completion or the safety on the machine is influenced after the control channel of the existing direct current control protector provided in the background art fails.

In order to achieve the purpose, the invention provides the following technical scheme: comprises a power supply and an upper computer; the input end of the power supply is connected with a first control authority switching circuit and a second control authority switching circuit respectively, and the input end of the first control authority switching circuit is connected with a DSP control unit; the output end of the DSP control unit is connected with the second control authority switching circuit, and the DSP control unit comprises a master DSP direct current control circuit and a slave DSP direct current control circuit; the output end of the DSP control unit is connected with an FPGA interface processing unit, and the input end of the FPGA interface processing unit is connected with an upper computer through an RS422 communication module; the FPGA interface processing unit comprises a main FPGA direct-current interface processing circuit and a slave FPGA direct-current interface processing circuit; the main DSP direct current control circuit is connected with the main FPGA direct current interface processing circuit through a bus interface to form a main control channel, the slave DSP direct current control circuit is connected with the slave FPGA direct current interface processing circuit through a bus interface to form a slave control channel, and the main control channel and the slave control channel carry out information interaction through the CCDL communication module.

Preferably, a first memory is connected between the main DSP direct current control circuit and the main FPGA direct current interface processing circuit; and a second memory is also connected between the slave DSP direct current control circuit and the slave FPGA direct current interface processing circuit, and the first memory and the second memory are both used for storing the fault information of the direct current control protector so as to facilitate fault information inquiry and fault positioning.

Preferably, the control authority switching circuits of the first control authority switching circuit and the second control authority switching circuit are connected with the power supply of the power supply through the main power unit part; the main power unit component comprises a contactor, a right emergency bus bar, a conversion relay and a right main bus bar, wherein the right emergency bus bar is connected with the right main bus bar through the conversion relay, and the right emergency bus bar is connected with power supply through the contactor.

Preferably, the output end of the main power unit component is connected with two groups of signal conditioning circuits, the output end of one group of signal conditioning circuit is connected with the main FPGA direct-current interface processing circuit, and the output end of the other group of signal conditioning circuit is connected with the slave FPGA direct-current interface processing circuit; the signal conditioning circuit is used for sampling analog quantity, discrete quantity and frequency quantity signals of the direct current control protector.

Preferably, one output end of the first control authority switching circuit is further connected with a double-control-channel fault signal output unit, and an input end of the double-control-channel fault signal output unit is connected with the second control authority switching circuit.

Compared with the prior art, the invention has the beneficial effects that: the invention has a double-control channel control framework of a DSP + FPGA framework, wherein the DSP is used as a control processing core and is mainly used for functions of built-in self-checking, system detection, system control, information recording and the like; the FPGA is used as an interface information processing unit and is mainly used for data acquisition processing, communication interface management and other functions; the safety is stronger, the reliability is higher, in single product, possess two control channels from owner, in normal condition master control channel possess the control authority, follow the control channel and be in hot backup state, when one of them control channel trouble, can realize seamless switching to another control channel to guarantee the realization of product function, protect the power consumption safety on the machine.

Drawings

FIG. 1 is an architectural diagram of the present invention;

fig. 2 is a control block diagram of the present invention.

In the figure: the system comprises a power supply 1, a first control authority switching circuit 2, a second control authority switching circuit 3, a 4 DSP control unit, a 41 master DSP direct current control circuit, a 42 slave DSP direct current control circuit, a 5 first memory, a 6 second memory, a 7 FPGA interface processing unit, a 71 master FPGA direct current interface processing circuit, a 72 slave FPGA direct current interface processing circuit, an 8 CCDL communication module, a 9 upper computer, a 10 master power unit component, a 101 contactor, a 102 right emergency bus bar, a 103 conversion relay, a 104 right master bus bar, an 11 signal conditioning circuit and a 12 double-control channel fault signal output unit.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1-2, the present invention provides a technical solution: comprises a power supply 1 and an upper computer 3; the input end of the power supply 1 is respectively connected with a first control authority switching circuit 2 and a second control authority switching circuit 3, and the input end of the first control authority switching circuit 2 is connected with a DSP control unit 4; the output end of the DSP control unit 4 is connected to the second control authority switching circuit 3, and the DSP control unit 4 includes a master DSP dc control circuit 41 and a slave DSP dc control circuit 42; the output end of the DSP control unit 4 is connected with an FPGA interface processing unit 7, and the input end of the FPGA interface processing unit 7 is connected with the upper computer 3 through an RS422 communication module; the upper computer 3 is used for displaying communication data; the FPGA interface processing unit 7 includes a master FPGA dc interface processing circuit 71 and a slave FPGA dc interface processing circuit 72.

Referring to fig. 1 and 2, a first memory 5 is connected between the main DSP dc control circuit 41 and the main FPGA dc interface processing circuit 71; a second memory 6 is connected between the slave DSP direct current control circuit 42 and the slave FPGA direct current interface processing circuit 72, and the first memory 5 and the second memory 6 are used for storing fault information of the direct current control protector so as to facilitate fault information query and fault positioning; the control authority switching circuits of the first control authority switching circuit 2 and the second control authority switching circuit 3 are connected with the power supply 1 through a main power unit part 10; the main power unit part 10 includes a contactor 101, a right emergency bus bar 102, a transfer relay 103, and a right main bus bar 104, the right emergency bus bar 102 is connected to the right main bus bar 104 through the transfer relay 103, and the right emergency bus bar 102 is connected to the power supply 1 through the contactor 101; the output end of the main power unit component 10 is connected with two groups of signal conditioning circuits 11, the output end of one group of signal conditioning circuits 11 is connected with a main FPGA direct current interface processing circuit 71, and the output end of the other group of signal conditioning circuits 11 is connected with a slave FPGA direct current interface processing circuit 72; the signal conditioning circuit 11 is used for sampling analog quantity, discrete quantity and frequency quantity signals of the direct-current control protector; the output end of one position of the first control authority switching circuit 2 is also connected with a double-control-channel fault signal output unit 12, and the input end of the double-control-channel fault signal output unit 12 is connected with the second control authority switching circuit 3; the main power unit 10 is used for switching and shunting of the power supply 1, and the contactor 101 and the switching relay 103 are used for controlling the control target of the protector.

Referring to fig. 1 and fig. 2, the master DSP dc control circuit 41 is connected to the master FPGA dc interface processing circuit 71 through a bus interface to form a master control channel, the slave DSP dc control circuit 42 is connected to the slave FPGA dc interface processing circuit 72 through a bus interface to form a slave control channel, and the master control channel and the slave control channel perform information interaction through the CCDL communication module 8, including information such as detection result and status of the dc control protector; the main control channel carries out fault detection and protection according to the signal data sampling result, when faults such as overcurrent, short circuit, reverse flow, overvoltage, pulsation and the like occur in the direct current control protector, protection or alarm measures are executed according to system characteristic requirements, and the channel of the power supply 1 is controlled; the slave control channel outputs corresponding control logic by adopting a detection result transmitted by the main control channel through the CCDL communication module 8 so as to ensure that the control logic of the main control channel is consistent with that of the slave control channel, and when the main control channel fails, the slave control channel carries out system logic control according to the detection result of the slave control channel; when the master control channel and the slave control channel both fail, the control authority switching circuit of the first control authority switching circuit 2 and the second control authority switching circuit 3 controls the system to be in a safe state, and cuts off the control authority of the master control channel and the slave control channel, and simultaneously, the double-control channel failure signal output unit 12 of the circuit outputs a double-control channel failure signal.

Referring to fig. 1 and 2, the FPGA interface processing unit 7 is used as an interface processing unit and is responsible for signal data sampling processing, communication signal management, and other functions; the DSP circuit unit 4 is used for BIT and logic control, and the DSP circuit unit 4, the first control authority switching circuit 2 and the second control authority switching circuit 3 are matched as a control unit and are responsible for functions of self-checking, system detection, system control, information recording and the like in the upper computer 9; the main control channel realizes target control through the first control authority switching circuit 2, the slave control channel realizes target control through the second control authority switching circuit 3, the control authority of the main control channel is valid in a normal state, and the control authority of the slave control channel is invalid; the master control channel and the slave control channel periodically upload information such as detection results and system states to the upper computer 9 through the RS422 communication module bus, namely, the control authority switching circuit controls the communication data output of the two channels; the first control authority switching circuit 2 and the master control channel form a master control authority channel, and the second control authority switching circuit 3 and the slave control channel form a slave control authority channel; meanwhile, when the main control authority channel and the slave control authority channel detect faults, the related signals can be respectively stored in the first storage 5 and the second storage 6, and fault information inquiry and fault positioning are facilitated.

The working principle is as follows: after the product of the direct current control protector is powered on, the DSP control unit 4 is reset, and then, the same initialization is carried out firstly, and the machine position address of the upper computer 9 is identified to determine a main control channel and a slave control channel, namely, the main control channel preferably has a control authority switching circuit, then, the power-on self-check and the periodic self-check are carried out, and the maintenance self-check is carried out according to the instruction of the upper computer 9; the main control channel defaults to carry out system detection and system control, and cuts off the contactor 101 when detecting faults of power supply overvoltage, overcurrent, reflux and the like of the power supply 1, and executes other control logics according to the state of the system; the slave control channel does not default to system detection, but uses the detection result transmitted by the master control channel through the CCDL communication module 8 to ensure that the control logics of the master control channel and the slave control channel are consistent, and when the slave control channel is switched to the slave control channel, the system state can be transited stably; when the main control channel and the slave control channel perform self-checking, if a CPU fault and an internal power supply fault are detected, namely the internal power supply of the main power unit component 10 or a reference source fault is detected, the control channel at the side is judged to be in fault, the control channel at the side of the peer loses the control authority, and the control authority is obtained through the other side of the authority switching circuits of the first control authority switching circuit 2 and the second control authority switching circuit 3; when the master control channel and the slave control channel both have faults, the control authorities of the master control channel and the slave control channel are forbidden through the authority switching circuit, the hardware linkage control system is in a safe state, and meanwhile, a double-control-channel fault signal is output through the double-control-channel fault signal output unit 12, namely, the external communication of the control protector is forbidden at the same time.

The dual-redundancy control architecture has stronger safety and higher reliability; the system is characterized in that a master control channel and a slave control channel are provided in a single product, the master control channel has control authority in a normal state, the slave control channel is in a hot backup state, and when one control channel fails, seamless switching to the other control channel can be realized, so that the realization of product functions is ensured, and the on-board power utilization safety of an upper computer 9 is protected; the internal double control channels adopt a DSP + FPGA architecture, and the DSP is used as a control processing core and is mainly used for functions of built-in self-checking, system detection, system control, information recording and the like; the FPGA is used as an interface information processing unit and is mainly used for data acquisition processing, communication interface management and other functions, namely RS422 communication and CCDL communication between channels; the FPGA of the master control channel and the FPGA of the slave control channel sample the system state data and transmit the processing result to the master/slave DSP, the DSP of the master control channel implements fault detection and protection according to the system state data, the DSP of the slave control channel is in a hot backup state and receives the detection result of the master control channel through CCDL communication between the control channels so as to keep the states of the two parties consistent; the DSP periodically performs built-in self-checking, such as power supply detection, sampling reference detection, CPU detection, control drive detection and the like, and when the detection item fails, the control channel at the side is judged to be failed, and meanwhile, the control channel at the other side is switched to; when the double control channels are in failure, a hardware linkage mode is adopted, and a control target is in a safe state according to system requirements; the problem of current direct current control protector control channel trouble back, can lead to whole product function to lose, influence the machine and go up the later stage consumer, can seriously influence task completion or the machine safety is gone up is solved.

The RS-422 communication module is entirely called as the electrical characteristic of a balanced voltage digital interface circuit, defines the characteristic of the interface circuit, and actually has a signal ground wire with 5 lines, because a receiver adopts high input impedance and the transmission driver has stronger driving capability than RS232, a plurality of receiving nodes are allowed to be connected on the same transmission line, at most 10 nodes can be connected, namely a master device, the rest are slave devices, and communication cannot be carried out between the slave devices, therefore, the RS-422 supports point-to-multipoint bidirectional communication, the input impedance of the receiver is 4k, and the maximum load capacity of an originating terminal is 10 multiplied by 4k +100 omega terminating resistance; DSP is short for digital signal processing; the FPGA interface, namely field programmable gate array, it is the product that further develops on the basis of programmable devices such as PAL, GAL, CPLD, etc., it appears as a semi-custom circuit in the ASIC field of the specialized integrated circuit, have already solved the deficiency of the custom circuit, have overcome the limited disadvantage of the gate circuit of original programmable device; the CPLD communication module 8, a complex programmable logic device, is a device developed from PAL and GAL devices, relatively large in scale and complex in structure, and belongs to the large-scale integrated circuit range; the digital integrated circuit is a digital integrated circuit which is used by a user to construct logic functions according to respective needs.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A dual-redundancy control system of an airborne direct current control protector comprises a power supply (1) and an upper computer (3); the method is characterized in that: the input end of the power supply (1) is respectively connected with a first control authority switching circuit (2) and a second control authority switching circuit (3), and the input end of the first control authority switching circuit (2) is connected with a DSP control unit (4); the output end of the DSP control unit (4) is connected with the second control authority switching circuit (3), and the DSP control unit (4) comprises a master DSP direct current control circuit (41) and a slave DSP direct current control circuit (42); the output end of the DSP control unit (4) is connected with an FPGA interface processing unit (7), and the input end of the FPGA interface processing unit (7) is connected with the upper computer (3) through an RS422 communication module; the FPGA interface processing unit (7) comprises a main FPGA direct-current interface processing circuit (71) and a slave FPGA direct-current interface processing circuit (72); the main DSP direct current control circuit (41) is connected with the main FPGA direct current interface processing circuit (71) through a bus interface to form a main control channel, the slave DSP direct current control circuit (42) is connected with the slave FPGA direct current interface processing circuit (72) through the bus interface to form a slave control channel, and the main control channel and the slave control channel carry out information interaction through the CCDL communication module (8).

2. The dual redundancy control system of an airborne dc control protector according to claim 1, wherein: a first memory (5) is connected between the main DSP direct current control circuit (41) and the main FPGA direct current interface processing circuit (71); and a second memory (6) is also connected between the slave DSP direct current control circuit (42) and the slave FPGA direct current interface processing circuit (72), and the first memory (5) and the second memory (6) are used for storing the fault information of the direct current control protector so as to facilitate fault information query and fault positioning.

3. The dual redundancy control system of an airborne dc control protector according to claim 1, wherein: the control authority switching circuits of the first control authority switching circuit (2) and the second control authority switching circuit (3) are connected with a power supply (1) through a main power unit component (10); the main power unit component (10) comprises a contactor (101), a right emergency bus bar (102), a conversion relay (103) and a right main bus bar (104), wherein the right emergency bus bar (102) is connected with the right main bus bar (104) through the conversion relay (103), and the right emergency bus bar (102) is connected with a power supply (1) through the contactor (101).

4. The dual redundancy control system of an airborne dc control protector according to claim 3, wherein: the output end of the main power unit component (10) is connected with two groups of signal conditioning circuits (11), the output end of one group of signal conditioning circuit (11) is connected with a main FPGA direct current interface processing circuit (71), and the output end of the other group of signal conditioning circuit (11) is connected with a slave FPGA direct current interface processing circuit (72); the signal conditioning circuit (11) is used for sampling analog quantity, discrete quantity and frequency quantity signals of the direct current control protector.

5. The dual redundancy control system of an airborne dc control protector according to claim 1, wherein: one output end of the first control authority switching circuit (2) is further connected with a double-control-channel fault signal output unit (12), and the input end of the double-control-channel fault signal output unit (12) is connected with the second control authority switching circuit (3).