CN110992998A

CN110992998A - Leakage current compensation device and semiconductor memory device

Info

Publication number: CN110992998A
Application number: CN201910728178.0A
Authority: CN
Inventors: 白钟民; 维维克·文卡塔·卡鲁尔; 金鍾律; 比拉·阿哈默德·扬尤亚
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2018-10-02
Filing date: 2019-08-08
Publication date: 2020-04-10
Also published as: KR20200038346A; SG10201904054VA; US20200105345A1

Abstract

Disclosed are a leakage current compensation device and a semiconductor memory device. The leakage current compensation device includes: a current supply unit configured to supply a current to at least one operation unit among a plurality of cells of the memory device disposed at intersections of word lines and bit lines; a leakage current sensing unit configured to sense an amount of leakage current flowing to a non-operating unit among the plurality of units to output a result value based on the sensed amount of leakage current; and a compensation current supply unit configured to receive the result value and supply the compensation current to the operation unit.

Description

Leakage current compensation device and semiconductor memory device

This application claims priority and benefit of korean patent application No. 10-2018-0117301, filed in 2018, 10/2.2018, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present inventive concept relates to a leakage current compensating device and a semiconductor memory device, and more particularly, to a leakage current compensating device for adaptively compensating for a leakage current and a semiconductor memory device including the same.

Background

Semiconductor memory devices include volatile memory devices such as Dynamic Random Access Memory (DRAM) and non-volatile memory devices such as Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), phase change random access memory (PRAM), Resistive Random Access Memory (RRAM), and the like.

Such a semiconductor memory includes a large number of memory cells connected to each other. Such memory cells are disposed at intersections of a plurality of word lines and a plurality of bit lines. Read operations, write operations, and/or erase operations may be performed on such memory cells. In the case of a write operation, it is necessary to control a current flowing into a target cell of the write operation so that the target cell is written with correct data.

Disclosure of Invention

At least one exemplary embodiment of the inventive concept provides a leakage current compensating apparatus for preventing a case where a sufficient current does not flow to an operating cell due to a leakage current flowing through other cells and/or bit lines. When an operation is performed on an operation cell among a plurality of cells existing in a semiconductor memory device, a leakage current is generated. The leakage current compensation device may be disposed within a semiconductor memory device.

According to an exemplary embodiment of the inventive concept, a leakage current compensating device includes: a current supply unit configured to supply a current to at least one operation unit among a plurality of cells of the memory device disposed at intersections of word lines and bit lines; a leakage current sensing unit configured to sense an amount of leakage current flowing to a non-operating unit among the plurality of units to output a result value based on the sensed amount of leakage current; and a compensation current supply unit configured to receive the result value and supply the compensation current to the operation unit.

According to an exemplary embodiment of the inventive concept, a leakage current compensating device includes: a current supply unit configured to supply a current to at least one operation unit among a plurality of cells of the memory device disposed at intersections of word lines and bit lines; and a leakage current compensation unit configured to sense an amount of leakage current flowing to a non-operating unit among the plurality of units during a sampling period prior to the operating period, to determine a result value based on the sensed amount of leakage current, and to supply a compensation current to the operating unit based on the result value during the operating period.

According to an exemplary embodiment of the inventive concept, a semiconductor memory device includes: a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines; a current supply unit connected to one end of at least one word line among the plurality of word lines to supply a current to at least one operation unit among the plurality of memory cells; and a leakage current compensation unit configured to sense an amount of leakage current flowing to a non-operation unit among the plurality of memory cells to supply a compensation current to the operation unit according to the sensed amount of leakage current.

Drawings

Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic diagram showing the arrangement of memory cells in a semiconductor memory;

fig. 2 is a schematic diagram showing a case where a current is supplied to a cell remote from a current source in a semiconductor memory;

fig. 3 is a schematic diagram showing a case where a current is supplied to a cell near a current source in a semiconductor memory;

fig. 4 is a diagram showing a relationship between the position of a memory cell in a semiconductor memory and the amount of leakage current;

fig. 5 is a block diagram of a leakage current compensating apparatus according to an exemplary embodiment of the inventive concept;

fig. 6 is a circuit diagram illustrating a simplified circuit configuration of a leakage current compensating device according to an exemplary embodiment of the inventive concept;

fig. 7A and 7B are graphs illustrating a leakage current compensation operation according to the exemplary embodiment illustrated in fig. 6;

FIG. 8 is a circuit diagram illustrating one or more sense amplifiers used in at least one exemplary embodiment of the inventive concept applied during a read operation;

fig. 9 is a circuit diagram illustrating a circuit configuration of a leakage current compensating device according to an exemplary embodiment of the inventive concept;

fig. 10 is a circuit diagram illustrating a circuit configuration of a leakage current compensating device according to an exemplary embodiment of the inventive concept;

fig. 11 is a block diagram of a leakage current compensating apparatus according to an exemplary embodiment of the inventive concept;

fig. 12 is a circuit diagram illustrating a circuit configuration of a leakage current compensating device according to an exemplary embodiment of the inventive concept; and

fig. 13 is a graph illustrating an operation of the exemplary embodiment illustrated in fig. 12.

Detailed Description

Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

The inventive concept will become apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. It is to be understood that the inventive concept is not limited to the following embodiments, which are provided for complete disclosure and to assist those skilled in the art in understanding the invention, and may be embodied in various forms. Like components will be denoted by like reference numerals throughout the specification.

Fig. 1 is a schematic diagram showing the arrangement of memory cells in a semiconductor memory. A semiconductor memory includes a large number of memory cells connected to each other.

As shown in fig. 1, memory cells are disposed at intersections of a plurality of word lines (e.g., WL0, WL1, WL2, WL3, … …, WLn) and a plurality of bit lines (e.g., BL0, BL1, BL2, BL3, … …, BLn). In order to perform a read operation, a write operation, an erase operation, etc. on a specific cell among a plurality of memory cells, an appropriate amount of current needs to be supplied to the corresponding cell.

Fig. 2 is a schematic diagram showing a case where a current is supplied to a cell far from a current source in a semiconductor memory, fig. 3 is a schematic diagram showing a case where a current is supplied to a cell near a current source in a semiconductor memory, and fig. 4 is a schematic diagram showing a relationship between a position of a memory cell in a semiconductor memory and an amount of a leakage current.

Fig. 2 shows a case where a current is supplied to a memory cell at an intersection relatively distant from a current source among a plurality of intersections of a plurality of word lines and a plurality of bit lines. The voltage VPP is applied to the bit line passing through the cross point P3 to operate the memory cell disposed at the cross point P3. By the driving of the current source 10, a current flows through the paths of the intersection points P1, P2, P3, P4, and P5. Ideally, current does not flow to other bit lines and word lines not associated with the memory cell to be driven.

However, when a current flows, a voltage drop is caused by parasitic resistance existing on the line between the intersections. Since a voltage drop occurs due to parasitic resistance when a current flows through the paths of the intersection points P1, P2, P3, P4, and P5, the voltage applied to the one terminal VA of the current source 10 may have a value significantly lower than a value of 0 volt. Similarly, the voltage applied to the intersection points P3, P4, and P5 has a value greater than the value of the voltage applied to VA, but a value significantly less than 0 volts. Therefore, unnecessary leakage currents IOFF2 and IOFF1 flow to the bit line passing through the cross point P4 and the bit line passing through the cross point P5. As a result, the current supplied by the current source 10 does not flow directly to the memory cell existing at the intersection point P3 while maintaining its magnitude. In contrast, the current ICELL having a magnitude that reduces the amounts of the leakage currents IOFF1 and IOFF2 flows to the memory cell existing at the cross point P3, and thus, a current having an amount smaller than the expected amount is supplied to the operation cell.

When the memory cell to be operated is disposed at a position distant from the current source 10, the number of current paths increases. Therefore, the degree of voltage drop increases, resulting in a significant difference between the voltage value passing through the intersection on the word line of the long-distance cell and the value of 0 volts. As a result, the value of the leak current IOFF2 flowing to the bit line passing through the intersection P4 and the value of the leak current IOFF1 flowing to the bit line passing through the intersection P5 also increase. Due to the leakage currents IOFF1 and IOFF2, the current ICELL flowing to the drive unit may have a value significantly lower than the value of the supply current IPGM of the current source 10. In addition, since a voltage drop further occurs due to parasitic resistance existing between the intersection points P4 and P5 when a current passes through the intersection points P4 and P5, the leakage current IOFF1 may have a value greater than that of the leakage current IOFF 2.

On the other hand, referring to fig. 3, when a memory cell existing at a relatively short distance (e.g., the intersection point P6) from the current source 10 is driven, since the current flow path is short, the possibility of being affected by parasitic resistance on the bit line or the word line is reduced. Thus, leakage currents IOFF1 and IOFF2 may be very small or may be negligible, since voltage drops are infrequent.

As explained with reference to fig. 2 and 3, the amount of leakage current generated may vary depending on the location of the memory cell on the semiconductor memory. Referring to fig. 4, a near cell represents a cell having a short distance from a current source 10 configured to supply a current through a word line. For example, a near cell may represent a cell adjacent to the intersection of the first word line WL0 and the first bit line BL 0. As shown in fig. 3, the near cell represents a cell in which a significantly smaller leakage current is generated because a flow path of a current supplied to the operation cell is short. In addition, the far cell means a cell having a long distance from the current source 10. For example, the far cell may represent a cell adjacent to an intersection of the nth word line WLn and the nth bit line BLn. As shown in fig. 2, the remote cell represents a cell in which more leakage current is generated because a flow path of current supplied to the operation cell is long.

In one exemplary embodiment, the resistor Rc shown in fig. 2 and 3 represents a resistive material of the resistive memory cell. As shown in fig. 2 and 3, the current source 10 may be disposed between one end of the word line and the ground voltage VNES.

Fig. 5 is a block diagram of a leakage current compensating device according to an exemplary embodiment of the inventive concept, and fig. 6 is a circuit diagram illustrating a simplified circuit configuration of the leakage current compensating device according to an exemplary embodiment of the inventive concept. Fig. 7A and 7B are graphs illustrating a leakage current compensation operation according to the exemplary embodiment illustrated in fig. 6. Fig. 8 is a circuit diagram illustrating one or more sense amplifiers used in at least one exemplary embodiment applying the inventive concept during a read operation.

The leakage current compensating apparatus 100 according to an exemplary embodiment includes a current supply unit 110 (e.g., a current source) and a leakage current compensating unit 120 (e.g., a circuit). In one exemplary embodiment, the leakage current compensating unit 120 includes a leakage current sensing unit 122 (e.g., a circuit) and a compensating current supplying unit 124 (e.g., a current source).

The current supply unit 110 supplies a current to at least one memory cell or a plurality of memory cells among a plurality of cells disposed at intersections of word lines and bit lines. A current supply unit 110 may be connected to each word line. In the exemplary embodiment shown in fig. 6, the current supply unit 110 is a transistor 10 that conducts the programmable current IPGM in response to the input signal IPGM _ EN, but is not limited thereto. Since current is supplied to the memory cells at a specific timing to operate the corresponding memory cells, the memory cells to which current will be supplied will be referred to as "operation cells" and the cells other than the operation cells will be referred to as "non-operation cells" for convenience of description.

The leakage current sensing unit 122 senses the amount of leakage current flowing to non-operating units other than the operating units to output a result value according to the sensed amount of leakage current. In the circuit shown in fig. 6, the manner of measuring the voltage value at the one end SDL of the current supply unit 110 may be applied as an example of sensing the amount of leakage current. For example, while current flows to the bit line and the word line, the degree of voltage drop increases as the amount of leakage current increases. Therefore, the smaller the voltage value at the one end SDL of the determination current supply unit 110 is, the larger the amount of the leakage current is.

To this end, the leakage current sensing unit 122 may include a first Sense Amplifier (SA)20 configured to sense a voltage value at one end SDL of the current supply unit 110. In one exemplary embodiment, it is determined that the compensation current will be supplied when the amount of leakage current is higher than a reference value (REF). For example, the technique may be applied to the exemplary embodiment shown in fig. 6. In this case, the voltage value at the one end SDL of the

current supply units

110 and 10 is supplied to the first input terminal of the first sense amplifier 20, the first reference voltage REF is supplied to the second input terminal of the first sense amplifier 20, and the first sense amplifier 20 compares the voltage value at the one end SDL of the

current supply units

110 and 10 with the first reference voltage REF to output a result value varying according to the comparison result.

In the present embodiment, the first sense amplifier 20 suggested as an example of the leakage current sensing unit 122 may be an amplifier already existing in the semiconductor memory device. For example, in the case where there already exists an amplifier that does not participate in a write operation but only participates in a read operation in the semiconductor memory device, the corresponding amplifier may be used as the first sense amplifier 20. As shown in fig. 8, the sense amplifier 20 may be an amplifier that originally participates in a read operation in the semiconductor memory device. In the present disclosure, since an existing amplifier for other purposes may be used to sense the leakage current, it is not necessary to additionally install a new amplifier for sensing the leakage current. For example, in fig. 8, when the signal READ _ EN is in an ON (enable) state, the sense amplifier 20 participates in the READ operation, but when the signal WRITE _ EN is in an ON state, the sense amplifier 20 is used to sense information about the amount of leakage current generated during the WRITE operation. In one embodiment, both the signal READ _ EN and the signal WRITE _ EN are not in the ON state at the same time. For example, when the signal READ _ EN is in an ON state during a READ operation, the signal WRITE _ EN is in an OFF (deactivated) state. For example, when the signal WRITE _ EN is in the ON state during a WRITE operation, the signal READ _ EN is in the OFF state. The circuit of fig. 8 may include a WRITE enable transistor connected between the word line and the compensation current supply unit 124, and a gate terminal of the WRITE enable transistor receives a WRITE enable signal WRITE _ EN. In one embodiment, the circuit of FIG. 8 includes a sensing circuit 80, the sensing circuit 80 including a sense amplifier 20 outputting a result value SAOUT, a READ enable transistor having a gate terminal receiving a READ enable signal READ _ EN, and a precharge transistor having a gate terminal receiving a precharge signal Pre-charge. The read enable transistor may be connected between one end of the word line and a first input of the sense amplifier 20. In one embodiment, the precharge transistor is connected between one terminal SDL of the current supply unit 110 and the negative voltage-VR.

Although only one sense amplifier 20 is depicted in FIG. 8, one or more of the

sense amplifiers

20, 22, 24, and 28 shown in FIG. 9 are similar to sense amplifier 20. A plurality of such amplifiers are also involved in read operations, but may be used to sense leakage current during write operations.

The compensation current supply unit 124 receives the result value output by the leakage current sensing unit 122 and supplies the compensation current to the operation unit. For example, in the embodiment shown in fig. 6, the compensation current supply unit 124 is implemented using a transistor 40 that conducts the compensation current ICOMP in response to the result value ICOMP _ EN output by the leakage current sensing unit 122 (or the sense amplifier 20). However, embodiments of the compensating current supply unit 124 are not limited to the use of the transistor 40.

In fig. 6 and fig. 9 and 11, for convenience of description and simplification of explanation, an example of the leakage current compensating apparatus 100 according to the present disclosure is shown as being disposed on only one word line among a plurality of word lines. However, the leakage current compensating device 100 according to the present disclosure may be disposed on some of the plurality of word lines. For example, the leakage current compensating device 100 may be disposed only on a word line including any far cells, or may be disposed on all word lines.

Hereinafter, an operation of the leakage current compensating device 100 according to an exemplary embodiment of the present disclosure will be described in detail with reference to fig. 6, 7A and 7B. In fig. 6, it is assumed that the first reference voltage REF is preset to a specific value. The amount of leakage current in the case where the memory cells disposed relatively close to the

current supply units

110 and 10 at the intersections existing on the specific word lines connected to the leakage current compensating device 100 are the operation units may be smaller than the amount of leakage current in the case where the memory cells disposed relatively far from the

current supply units

110 and 10 are the operation units. When the voltage value at the point of one end SDL of the

current supply units

110 and 10 is greater than a predetermined specific value, it is determined that the voltage drop at the point of SDL occurs to some extent due to the leakage current, but is not sufficient to compensate for the current. Fig. 7A is a graph showing a case where the compensation current supply unit 124 does not further supply the compensation current to the operation unit because the amount of the leakage current is too small to have the need for the compensation current.

In contrast, the amount of leakage current in the case where the memory cell disposed relatively far from the

current supply units

110 and 10 is the operation unit at the intersection existing on the specific word line connected to the leakage current compensating device 100 may be larger than the amount of leakage current in the case where the memory cell disposed relatively near to the

current supply units

110 and 10 is the operation unit. Therefore, in the case where the voltage value at one end SDL of the

current supply units

110 and 10 is less than a predetermined specific value, the amount of leakage current is large, and thus a large voltage drop occurs at the SDL point. As a result, it may be determined that there is a need to supply the compensation current ICOMP to the operation unit according to the amount of the leakage current.

In this case, a criterion for determining the compensation current, according to which the value of the first reference voltage REF is set in advance, may be determined as needed. For example, in the embodiment of fig. 6, the reference voltage REF may be a negative value (such as-1.5 volts).

In one embodiment, the current supply unit 10 of fig. 6 includes a first transistor having a gate terminal that receives the first BIAS signal BIAS1 and a second transistor having a gate terminal that receives the input signal IPGM _ EN. In one embodiment, the second transistor of the current supply unit 10 is connected between the first transistor of the current supply unit 10 and the ground voltage VNEG. In one embodiment, compensation current supply unit 124 includes a first transistor having a gate terminal that receives second BIAS signal BIAS2 and a second transistor that receives the output of sense amplifier 20. In one embodiment, the second transistor of the compensation current supply unit 124 is disposed between the first transistor of the compensation current supply unit 124 and the ground voltage VNEG.

The value of the first reference voltage REF applied to each leakage current compensating device 100 connected to each word line may be differently set for each word line. This causes the boundary value at which the compensation current ICOMP starts to be supplied for each word line to be set differently for each word line. More specifically, as shown in fig. 6 and as will be shown in fig. 9 and 11, an example of the leakage current compensating device according to the present disclosure is provided on only one word line among a plurality of word lines for convenience of description and simplicity of explanation. In the case where the leakage current compensating device according to the present disclosure is mounted on one or more word lines other than the lowermost word line in fig. 6, the value of the reference voltage applied to each word line may become different. For example, the preset value of the first reference voltage REF is set differently for each word line.

When the reference voltage value is differently set for each word line as described above, a current compensation operation start point depending on the position of the operation unit may be differently set to flexibly supply a flexible compensation current. For example, the value of the reference voltage REF supplied to the leakage current compensating device disposed on the upper word line may be set to be greater than the value of the reference voltage REF supplied to the leakage current compensating device disposed on the lowermost word line. Accordingly, the current compensation operation start point of the upper word line, which is expected to generate a relatively smaller amount of leakage current than the lower word line, may be set to be more sensitive than the current compensation operation start point of the lower word line.

In addition, the reference voltage value supplied to all the leakage current compensating devices disposed on the respective word lines may be generally adjusted according to a change in temperature in the ambient elements. For example, when the temperature of the semiconductor memory device is increased step by step, the amount of leakage current increases, thereby increasing the probability that the voltage value at one end (SDL) point of the current supply unit 10 is lower than the reference voltage value. Therefore, the possibility of leakage current compensation can be increased. However, as necessary, the value of the reference voltage supplied to the leakage current compensating device provided on each word line may be changed according to the temperature variation of the semiconductor memory device to further advance or delay the leakage current compensation start point according to the temperature increase.

Fig. 7A shows a case where the voltage at the SDL point is larger than the first reference voltage REF and current compensation is not performed. Fig. 7B shows a case where the voltage at the SDL point is smaller than the first reference voltage REF and thus current compensation is performed. The increment shown by the broken line in the box on the right side of the graphs in fig. 7A and 7B is the amount of the compensation current ICOMP further supplied to the operation unit by the compensation

current supply units

124 and 40.

Returning to fig. 5, the leakage current compensating device 100 according to an exemplary embodiment may further include a compensation current information storing unit 130 (e.g., a memory device). The compensation current information storage unit 130 stores different compensation current amount information according to at least one of different temperature sections and different unit locations.

When the voltage at the SDL point falls below the predetermined first reference voltage REF and the compensation current supply unit 124 supplies the compensation current, the compensation current supply unit 124 supplies compensation currents different from each other. As described above, this is because the leakage current may vary depending on the cell location. Therefore, the magnitude of the current to be compensated may vary depending on the cell position.

The parasitic resistance present on each line (e.g., bit line or word line) is variable depending on temperature. Assuming that the voltage is equivalently supplied, the amount of leakage current tends to increase as the temperature increases. Therefore, the magnitude of the compensation current to be compensated also needs to be adaptively determined according to the temperature variation.

The compensation current information storage unit 130 stores the magnitude of the compensation current to be compensated in the form of a lookup table according to such a unit position and/or a temperature section as an environmental element. Accordingly, the leakage current compensating device 100 according to at least one exemplary embodiment may accurately perform current compensation.

The leakage current compensating device 100 according to an exemplary embodiment may further include a temperature sensing unit 140 (e.g., a temperature sensor or a circuit), the temperature sensing unit 140 being configured to sense the temperature of the plurality of cells or the ambient temperature of the plurality of cells in such a manner that the magnitude of the compensation current to be compensated varies according to the temperature interval as the environmental element. The temperature sensing unit 140 senses the temperature of the semiconductor memory device in which the plurality of cells are disposed, and transmits the sensed temperature to the compensation current information storage unit 130.

When the environmental element is not considered, the compensation current information storage unit 130 may provide the compensation current to the compensation current supply unit 124 according to the location of the memory cell. When considering the environmental elements, the compensation current information storage unit 130 may determine a compensation current value using a lookup table previously stored for each temperature interval based on the temperature information received from the temperature sensing unit 140, and may provide the determined value to the compensation current supply unit 124.

The compensation current supply unit 124 receives compensation current information from the compensation current information storage unit 130 and supplies a compensation current to the operation unit according to the received compensation current information.

Fig. 9 is a circuit diagram illustrating a circuit configuration of a leakage current compensating device according to an exemplary embodiment of the inventive concept. In the present embodiment shown in fig. 9, there are a plurality of sense amplifiers. For example, there may be n sense amplifiers (n is an integer greater than or equal to 2). There are four sense amplifiers in the embodiment shown in fig. 9, but exemplary embodiments of the inventive concept are not limited thereto.

In the embodiment shown in fig. 9, there are first to

fourth sense amplifiers

20, 22, 24, and 28. The voltage value at one end SDL of the

current supply units

110 and 10 is input to first input terminals of the first to

fourth sense amplifiers

20, 22, 24 and 28. The first to fourth reference voltages REF0, REF1, REF2 and REF3 are input to second inputs of the first to

fourth sense amplifiers

20, 22, 24 and 28, respectively. In one embodiment, the first to fourth reference voltages REF0, REF1, REF2, and REF3 have different values from each other. However, embodiments of the inventive concept are not limited thereto, and some reference voltage values may have the same value as needed.

Hereinafter, the case where the first to fourth reference voltages REF0, REF1, REF2, and REF3 are preset to have different values of-1 volt, -1.5 volts, -2.5 volts, and-3 volts, respectively, will be described as an example. When the voltage value at the point SDL of the current supply unit 10 is-2.6 volts, the voltage value is lower than the first to third reference voltages REF0, REF1, and REF2 and is greater than the fourth reference voltage REF 3. In this case, as shown in fig. 9, the leakage current sensing unit 122 may output four result values of ICOMP _ EN0 to ICOMP _ EN 3. When the voltage value at the SDL point of the current supply unit 10 has a specific value other than-2.5 to-3 volts, the result value output by the leakage current sensing unit 122 may vary. Accordingly, the number of result values output by the leakage current sensing unit 122 is one more than the number of reference voltages having different values, and the compensation current supply unit 124 supplies different amounts of current sources to the operation unit.

In one exemplary embodiment, the circuit of fig. 9 includes a current supply unit 10 and a plurality of

current supply units

40, 42, 44, and 46. In one embodiment, each current supply cell includes a first transistor having a gate terminal receiving the second BIAS signal BIAS2 and a second transistor having a gate terminal receiving the outputs of the first through

fourth sense amplifiers

20, 22, 24, and 28.

With the embodiment shown in fig. 9, the amount of leakage current can be sensed more accurately, and thus, the amount of compensated current also has a different value. As a result, an appropriate amount of leakage current corresponding to the amount of leakage current can be supplied to the operation unit.

Further, in the embodiment shown in fig. 9, the magnitude of the compensation current may be determined by further reflecting the cell location and environmental elements. For example, the compensation current supply unit 124 may supply the compensation current value in consideration of only the location of the memory cell from the compensation current storage unit 130, in consideration of only the environmental element (temperature), or in consideration of both the location of the memory cell and the environmental element, and may reflect the supplied compensation current value to the magnitude of the compensation current.

Fig. 10 is a circuit diagram illustrating a circuit configuration of a leakage current compensating device according to an exemplary embodiment of the inventive concept. According to another example of the leakage current compensating apparatus 100, the current supplying unit 110 and the leakage current compensating unit 120 shown in fig. 5 are included. The leakage current compensating unit 120 may include one of leakage

current sensing units

122 and 60 and one of compensation current supplying

units

124 and 40. Since the leakage

current supply units

110 and 10 are the same as the leakage

current supply units

110 and 10 described with reference to fig. 6 or 9, a repetitive description thereof will be omitted.

Referring to fig. 10, the leakage current sensing units 112 and 60 may include

regulator units

62 and 64 and current mirror units 66 and 68 (current mirror circuits).

Regulator cells

62 and 64 sense the amount of leakage current (e.g., IOFF) flowing to unselected bit lines on which selected cells are not located. The

current mirror units

66 and 68 output the amount of leakage current as a result value and supply the result value to the compensation current supply unit 40. The

regulator units

62 and 64 may include an amplifier 62 and a first transistor 64, an output terminal of the amplifier 62 being connected to a gate terminal M1 of the first transistor 64, a source terminal of the first transistor 64 being connected to a power supply VDD, and the

current mirror units

66 and 68 may include a second transistor 66 and a third transistor 68.

According to another embodiment of the leakage current compensating device of the present disclosure, information on a sum IOFF _ TOTAL of leakage currents IOFF1 and IOFF2 flowing to the bit line is sensed. The sensed information is provided to the compensation current supply unit 40 through a current mirror to compensate the current. According to the related art, the unselected bit lines are grounded to be connected to an unselected voltage (e.g., 0 v) via switches, and according to at least one embodiment of the inventive concept, the unselected bit lines are connected to the

regulator units

62 and 64 via switches (not shown).

Specifically, in the present embodiment, the bit line is connected to any one of a voltage VPP supplied via a switch (not shown) and an unselected voltage supplied via an input terminal of the amplifier 62. Thus, unselected bit lines are supplied with unselected voltages via the inputs of amplifier 62, and selected bit lines are supplied with voltage VPP via a switch (not shown). The sum IOFF _ TOTAL of the drain currents IOFF1 and IOFF2 flowing to the unselected bit lines flows to the first transistor 64 and is reflected in the second transistor 66 by the current mirror circuit. A current corresponding to the sum IOFF _ TOTAL of the leakage currents IOFF1 and IOFF2 flows to the second transistor 66 and the third transistor 68, and is finally transmitted to the compensating current supplying unit 40.

The compensating current supplying unit 40 supplies the compensating current ICOMP through information on the sum IOFF _ TOTAL of the received drain currents. In this case, a determination may be made as to whether the operation of compensating the current is performed by the separate input signal ICOMP _ EN supplied to the compensation current supply unit 40.

Fig. 11 is a block diagram of a leakage current compensating device according to an exemplary embodiment of the inventive concept, fig. 12 is a circuit diagram illustrating a circuit configuration of the leakage current compensating device according to an exemplary embodiment of the inventive concept, and fig. 13 is a graph illustrating an operation of the exemplary embodiment illustrated in fig. 12.

The leakage current compensating device 200 according to an exemplary embodiment includes a current supply unit 210 (e.g., a current source) and a leakage current compensating unit 220 (e.g., a circuit).

The current supply unit 210 has the same basic function as the current supply unit 110 in the embodiment described with reference to fig. 5, but differs therefrom in that: no current is supplied to the operation unit during the sampling period.

The leakage current compensating unit 220 senses an amount of leakage current flowing to non-operating units other than the operating units during a sampling period before the operating period to store a result value corresponding to the sensed amount of leakage current and supplies a compensation current to the operating units according to the result value.

Compared to the embodiment shown in fig. 5, the embodiment shown in fig. 11 has a sampling period of a cell operation before the current supply unit 210 supplies a current to the memory cell. During the sampling period, the leakage current compensating unit 220 senses the amount of leakage current flowing to non-operating units other than the operating unit. Sensing of the amount of leakage current is performed by supplying a sampling voltage to one end of a current supply unit according to the position of a cell to be operated during a sampling period.

To this end, the leakage current compensating device 200 may further include a sampling voltage supply unit 230, the sampling voltage supply unit 230 being configured to supply different sampling voltages to one end of the current supply unit according to the cell position.

The sampling voltage supply unit 230 receives location information (e.g., address information) of the cell and supplies sampling voltages according to the location information to supply different sampling voltages according to the location of the cell. As described above, when a current is supplied to operate a specific memory cell, a voltage drop occurs due to the presence of a leakage current. Since the amount of leakage current varies depending on the position of the cell to be operated, a difference in the degree of voltage drop occurs. As a result, the voltage applied to one end of the current supply unit 210 varies. The sampling voltage supply unit 230 receives the location information of the cell during a sampling period and supplies a voltage value, which is to be applied to one end of the current supply unit 210 and varies according to the location information, to one end of the current supply unit 210 in advance. The value of the voltage to be supplied during the sampling period may be set according to the measured value or preset.

As described above, since the amount of the leakage current may vary according to environmental elements (e.g., temperature variation), the memory cell may determine the sampling voltage in consideration of the influence of temperature, and may supply the determined sampling voltage to one end of the current supply unit. According to another exemplary embodiment, the sampling voltage supply unit 230 may store the sampling voltage in the form of a lookup table. According to another exemplary embodiment, a temperature sensing unit 240 (e.g., a sensor or a circuit) may also be provided to sense the temperature of the plurality of cells or the ambient temperature of the plurality of cells to take into account the effect of the temperature. In this case, the temperature sensing unit 240 may transmit the sensed temperature information to the sampling voltage supply unit 230.

The leakage current compensating unit 220 senses an amount of leakage current flowing to non-operating units other than the operating unit in advance during the sampling period to store a result value according to the sensed amount of leakage current, and supplies a compensation current to the operating unit according to the result value during the operating period. This will be described below with reference to fig. 12.

Fig. 12 shows a simplified circuit configuration according to an exemplary embodiment of the leakage current compensating device 200 shown in fig. 11.

The current supply unit 210 may be connected to each word line. In the embodiment shown in fig. 12, the current supply unit 210 is described as the transistor 10 configured to conduct the current IPGM in response to the input signal IPGM _ EN, but exemplary embodiments of the inventive concept are not limited thereto.

In fig. 12, a leakage current compensating unit 60 including a first transistor 62, a switch 64, and a capacitor 66 is provided as an example of the leakage current compensating unit 220 shown in fig. 11.

The first transistor 62 transmits a compensation current during an operation period. A switch 64 is connected between the drain terminal and the gate terminal of the first transistor 62. The capacitor 66 has one terminal connected to the gate terminal of the first transistor 62 and the other terminal connected to the source terminal of the first transistor 62.

The switch 64 may be a second transistor 64 having a drain terminal and a source terminal connected to the drain terminal and the gate terminal of the first transistor 62, respectively, and the second transistor 64 receives the sampling period information signal SH _ EN through the gate terminal. The gate terminal of the second transistor 64 receives "1" as the sampling period information signal in the sampling period and receives "0" as the sampling period information signal in the non-sampling period. For example, the sampling period has started when the sampling period information signal SH _ EN is "1", and the sampling period has ended when the sampling period information signal SH _ EN is "0".

Referring to fig. 13, a period t representing "1" in the waveform indicated by the SH _ EN signal corresponds to a sampling period. When the signal input to the gate terminal of the second transistor 64 is "1", the drain terminal and the gate terminal of the first transistor 62 are turned on. In this case, the first transistor 62 similarly functions as a diode. During the sampling period t, the sampling voltage supply unit 230 supplies the sampling voltage to one end SDL of the current supply unit 10. Fig. 12 illustrates an example in which the sampling voltage Vsampling is supplied through the amplifier 50, but exemplary embodiments of the inventive concept are not limited thereto.

When the sampling voltage is supplied to the SDL terminal, the control input signal IPGM _ EN supplied to the current supply unit 10 has a value of "0". Since a leakage potential difference occurs when the sampling voltage is supplied to the SDL terminal, a leakage current is expected to occur during the operation period. For example, the sampling current flows from the drain terminal to the source terminal of the first transistor 62. The voltage value stored in the capacitor 66 varies depending on the magnitude of the sampling current. For example, when the magnitude of the sampling current is large, the value of the voltage applied to the capacitor 66 also increases.

Then, the sampling period t ends, and the SH _ EN signal becomes "0". When the operation period starts, a current is supplied to the memory cell through the current supply unit 10, and the positive compensation current ICOMP corresponding to the voltage value applied to the capacitor 66 passes through the first transistor 62. For example, the amount of compensation current compensated by the first transistor 62 is determined according to the magnitude of the voltage applied to the gate-source terminal of the first transistor 62.

In another embodiment, information about the amount of leakage current generated in a state where the sampling voltage supply unit 230 does not supply the sampling voltage to the one end SDL of the current supply unit during the sampling period may be determined. In other words, a state (e.g., a state in which no cell operates) in which an unselected voltage (e.g., 0 v) is applied to all bit lines and all word lines of the semiconductor memory device is set, and information on how much leakage current is generated in the corresponding semiconductor memory device is stored in the leakage current compensating unit 220.

The leakage current compensation unit 220 may include a latch circuit configured to store information about leakage current. The latch circuit may include a first transistor 62. The configuration of the leakage current compensating unit 60 including the switch 64 and the capacitor 66 may be applied as an example of a latch circuit. For example, information on the leakage current may be stored as a voltage value applied to the capacitor 66 of the leakage current compensation unit 60, and then the compensation current supply amount may be determined. In this case, the period in which the SH _ EN signal is "1" shown in fig. 13 may include a period in which the sampling voltage is not supplied, in addition to a period in which the sampling voltage is supplied to the one end SDL of the current supply unit. Information on the leakage current collected during the period in which the sampling voltage is not supplied (for example, the amount of the generated leakage current) may be used to determine the compensation current ICOMP corresponding to the leakage current generated when the SH _ EN signal becomes "0" and current is supplied to the memory cell to be operated by applying the control input signal IPGM _ EN to the current supply unit 10.

The present inventive concept relates to a semiconductor memory device which supplies a current to a memory cell to be operated among a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines, and senses an amount of a leakage current flowing to a non-operating cell other than the operating cell to supply a compensation current to the operating cell according to the sensed amount of the leakage current. The semiconductor memory device includes: a current supply unit connected to one end of at least one of the plurality of word lines to supply a current to at least one of the plurality of memory cells, and a leakage current compensation unit configured to sense an amount of leakage current flowing to a non-operating unit other than the operating unit to supply a compensation current to the operating unit according to the sensed amount of leakage current. The leakage current compensating unit may employ the leakage current compensating unit 120 described in fig. 5 and the leakage current compensating unit 220 described in fig. 11, and a detailed description thereof will be omitted to avoid a repetitive description.

In the specification, the terms "unit," "module," "table," and the like may represent a software component or a hardware component, such as a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), and the module performs some functions. However, the module is not limited to hardware or software. A module may be configured to reside in an addressable storage medium or configured to drive one or more processors. A module may represent a software component, an object-oriented software component, a class component, a task component, a procedure, a function, an attribute, a procedure, a subprogram, a segment of program code, a driver, firmware, microcode, circuitry, data, a database, a data structure, a table, an array, or a variable. The functionality provided by the components and modules may be combined into smaller components and modules and may be combined with other components and modules to form larger components and modules. The components and modules may be configured to drive one or more Central Processing Units (CPUs) in the components and modules.

As described above, at least one exemplary embodiment of the inventive concept provides a semiconductor memory that senses a leakage current and compensates for the leakage current. When an operation is performed on a specific cell among a plurality of cells existing in a semiconductor memory, a leakage current may be generated. The amount of compensation may adaptively vary based on the location of the unit and/or the surrounding environment.

While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept.

Claims

1. A leakage current compensation device, comprising:

a current supply unit configured to supply a current to at least one operation unit among a plurality of cells of the memory device disposed at intersections of word lines and bit lines;

a leakage current sensing unit configured to sense an amount of leakage current flowing to a non-operating unit among the plurality of units to output a result value based on the sensed amount of leakage current; and

a compensation current supply unit configured to receive the result value and supply a compensation current to the operation unit.

2. The leakage current compensating device of claim 1, wherein the leakage current sensing unit comprises: a first sense amplifier configured to sense a voltage value at one end of the current supply unit.

3. The leakage current compensating device of claim 2, wherein the voltage value at the one terminal of the current supplying unit is supplied to a first input terminal of a first sense amplifier, a first reference voltage is supplied to a second input terminal of the first sense amplifier, and the first sense amplifier compares the voltage value at the one terminal of the current supplying unit with the first reference voltage to output the resultant value.

4. The leakage current compensating device of claim 1, wherein the leakage current sensing unit comprises: first to nth sense amplifiers configured to sense a voltage value at the one end of the current supply unit, wherein n is an integer greater than or equal to 2.

5. The leakage current compensation device according to claim 4, wherein a voltage value at the one end of the current supply unit is supplied to a first input terminal of each of the first to n-th sense amplifiers, and

first to nth reference voltages different from each other are supplied to the second input terminal of each of the first to nth sense amplifiers.

6. The leakage current compensating device of claim 5, wherein the leakage current sensing unit compares a voltage value at the one terminal of the current supplying unit with each of the first to nth reference voltages to output a different result value.

7. The leakage current compensation device of claim 1, further comprising:

a storage unit configured to store different compensation current information according to at least one of different temperature intervals and different unit locations.

8. The leakage current compensation device of claim 7, further comprising:

a temperature sensing unit configured to sense a temperature of the plurality of cells or an ambient temperature of the plurality of cells to generate sensed temperature information,

wherein the temperature sensing unit transmits the sensed temperature information to the storage unit.

9. The leakage current compensation device of claim 7, wherein the compensation current supply unit receives compensation current information and supplies the compensation current to the operation unit according to the received compensation current information.

10. The leakage current compensating device of claim 1, wherein the leakage current sensing unit comprises:

a regulator unit configured to sense an amount of leakage current flowing to unselected bit lines on which the selected cell is not disposed; and

a current mirror unit configured to output an amount of the leakage current as a result value to the compensation current supply unit.

11. The leakage current compensation device of claim 10, wherein the regulator unit comprises:

an amplifier configured to provide an unselected voltage to an unselected bit line; and

and a first transistor to which a current corresponding to a total value of drain currents flowing to the unselected bit lines flows.

12. A leakage current compensation device, comprising:

a current supply unit configured to supply a current to at least one operation unit among a plurality of cells of the memory device disposed at intersections of word lines and bit lines; and

a leakage current compensation unit configured to sense an amount of leakage current flowing to a non-operating unit among the plurality of units during a sampling period prior to the operating period, to determine a result value based on the sensed amount of leakage current, and to supply a compensation current to the operating unit based on the result value during the operating period.

13. The leakage current compensation device of claim 12, further comprising:

a sampling voltage supply unit configured to supply different sampling voltages to one end of the current supply unit based on the cell position.

14. The leakage current compensation device of claim 12, further comprising:

a sampling voltage supply unit configured to supply different sampling voltages to one end of the current supply unit based on the unit position and different temperature intervals.

15. The leakage current compensation device of claim 14, further comprising:

wherein the temperature sensing unit transmits the sensed temperature information to the sampling voltage supply unit.

16. The leakage current compensating device of claim 12, wherein the leakage current compensating unit comprises:

a first transistor through which a compensation current passes;

a switch configured to be connected to a drain terminal of the first transistor and a gate terminal of the first transistor to each other; and

and a capacitor configured to be connected to the gate terminal of the first transistor and the source terminal of the first transistor.

17. The leakage current compensation device according to claim 16, wherein the switch is a second transistor configured to receive the sampling period information signal through a gate terminal of the second transistor, and

a drain terminal of the second transistor and a source terminal of the second transistor are connected to a drain terminal of the first transistor and a gate terminal of the first transistor, respectively.

18. The leakage current compensation device according to claim 17, wherein the sampling period information signal is a digital signal which is 1 during the sampling period and 0 outside the sampling period.

19. The leakage current compensation device of claim 16, wherein the capacitor stores the resultant value as a voltage value based on an amount of leakage current sensed during the sampling period.

20. A semiconductor memory device, the semiconductor memory device comprising:

a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines;

a current supply unit connected to one end of at least one word line among the plurality of word lines to supply a current to at least one operation unit among the plurality of memory cells; and

a leakage current compensation unit configured to sense an amount of leakage current flowing to a non-operation unit among the plurality of memory cells to supply a compensation current to the operation unit according to the sensed amount of leakage current.