CN110990298A - Data copy processing method and device, electronic equipment and storage medium - Google Patents
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/543—User-generated data transfer, e.g. clipboards, dynamic data exchange [DDE], object linking and embedding [OLE]
Abstract
The invention provides a data copy processing method, a data copy processing device, electronic equipment and a storage medium, which are applied to a RISC reduced instruction set architecture and determine a data copy request message; determining whether the source data address and the target data address are both 16 bytes aligned according to the data copy request message; when the source data address and the target data address are 16 bytes aligned, copying the bytes to be copied from the source data address to the target data address by 128 bits by adopting a first access instruction group, and acquiring the rest bytes in the bytes to be copied; and copying the rest bytes from the source data address to the target data address by adopting a byte-by-byte copying mode or adopting 64-bit-based copying processing of a second access instruction group. Compared with the prior art, the address is aligned firstly, and then the byte to be copied is directly copied by adopting the first access instruction group, so that the processing efficiency and the running speed of the copied data are effectively improved.
Description
Technical Field
The present disclosure relates to computer technologies, and in particular, to a method and an apparatus for processing data copy, an electronic device, and a storage medium.
Background
The data copying by using the copying function is an indispensable step of a computer in the process of processing data.
In the prior art, a computer performs copy processing on data by using some function instructions, for example, a memory copy function memcpy. In particular, the memcpy function may be used to copy n bytes to be copied from a source data address to a target data address. When the memcpy function is used for data copying, when a target data address stores a plurality of bytes, the stored bytes are covered after the memory copy function is executed; furthermore, when there is an address overlap between the target data address and the source data address, a portion of the bytes stored in the source data address that overlap the address to be copied may be overwritten after the memory copy function is executed. That is to say, when the source data address and the target data address are not aligned, the memcpy function copies n bytes to be copied in a byte-by-byte copying manner, and copies the n bytes after the addresses are aligned by using a cpu word length, where the cpu word length is generally 32 bits or 64 bits.
However, as the amount of copied data increases, the copying efficiency of data copying by using the memcpy function cannot meet the increasing demand of the amount of data, and is not beneficial to data and operation of a computer on large data.
Disclosure of Invention
In view of the above-mentioned problems, the present disclosure provides a data copy processing method, apparatus, electronic device, and storage medium.
In a first aspect, the present disclosure provides a processing method for data copy, which is applied to a RISC reduced instruction set architecture, and the processing method includes:
determining a data copy request message, the data copy request message comprising: a source data address, a destination data address, and a byte to be copied;
determining whether the source data address and the target data address are both 16 bytes aligned according to the data copy request message;
when the source data address and the target data address are 16 bytes aligned, copying the bytes to be copied from the source data address to the target data address by 128 bits by adopting a first access instruction group, and acquiring the rest bytes in the bytes to be copied;
and copying the rest bytes from the source data address to the target data address by adopting a byte-by-byte copying mode or adopting 64-bit-based copying processing of a second access instruction group.
In other optional examples, the processing method further comprises:
when the source data address and the target data address are not aligned by 16 bytes, the byte to be copied is aligned, so that the source data address and the target data address are both aligned by 16 bytes;
and copying the bytes to be copied from a source data address to the target data address by adopting a first memory access instruction group, and acquiring the rest bytes in the bytes to be copied.
In other optional examples, the aligning the byte to be copied includes:
when the byte misalignment part of the source data address and the target data address exceeds 64 bits, copying the misalignment part by adopting a second memory access instruction group until the source data address and the target data address are aligned by 16 bytes.
In other optional examples, the aligning the byte to be copied includes:
when the byte misalignment part of the source data address and the target data address does not exceed 64 bits, copying the byte to be copied from the source data address to the target data address in a byte-by-byte copying mode until the source data address and the target data address are both 16 bytes aligned.
In other optional examples, the copying the remaining bytes from the source data address to the target data address includes:
when the remaining bytes exceed 64 bits, copying the remaining bytes by adopting a second memory access instruction group;
and when the residual bytes are determined not to exceed 64 bits, copying the residual bytes from the source data address to the target data address in a byte-by-byte copying mode.
In a second aspect, the disclosed example provides a processing apparatus for data copying, which is applied to a RISC reduced instruction set architecture, and includes:
a transceiving unit configured to determine a data copy request message, where the data copy request message includes: a source data address, a destination data address, and a byte to be copied;
a determining unit, configured to determine whether the source data address and the target data address are both 16-byte aligned according to the data copy request message;
the copying unit is used for copying the bytes to be copied from the source data address to the target data address by 128 bits by adopting a first access instruction group when the source data address and the target data address are aligned to 16 bytes, and acquiring the rest bytes in the bytes to be copied; and the processor is further configured to copy the remaining bytes from the source data address to the target data address in a byte-by-byte copy manner or based on 64-bit copy processing by using a second access instruction group.
In other optional examples, the processing device further comprises:
the copying unit is used for aligning the bytes to be copied when the source data address and the target data address are not aligned by 16 bytes, so that the source data address and the target data address are both aligned by 16 bytes; and copying the bytes to be copied from a source data address to the target data address by adopting a first memory access instruction group, and acquiring the rest bytes in the bytes to be copied.
In other optional examples, the copy unit is configured to, when it is determined that a byte-misaligned portion of a source data address and a target data address exceeds 64 bits, copy the misaligned portion with a second access instruction group until the source data address and the target data address are both 16 bytes aligned.
In other optional examples, the copying unit is configured to, when it is determined that the byte misalignment portion between the source data address and the target data address does not exceed 64 bits, copy the byte to be copied from the source data address to the target data address in a byte-by-byte copying manner until the source data address and the target data address are both 16 bytes aligned.
In other optional examples, the copying unit is configured to copy the remaining byte with a second access instruction group when it is determined that the remaining byte exceeds 64 bits; and when the residual bytes are determined not to exceed 64 bits, copying the residual bytes from the source data address to the target data address in a byte-by-byte copying mode.
In a third aspect, the present disclosure provides an electronic device, comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to:
determining a data copy request message, the data copy request message comprising: a source data address, a destination data address, and a byte to be copied;
determining whether the source data address and the target data address are both 16 bytes aligned according to the data copy request message;
when the source data address and the target data address are 16 bytes aligned, copying the bytes to be copied from the source data address to the target data address by 128 bits by adopting a first access instruction group, and acquiring the rest bytes in the bytes to be copied;
and copying the rest bytes from the source data address to the target data address by adopting a byte-by-byte copying mode or adopting 64-bit-based copying processing of a second access instruction group.
In a fourth aspect, the present disclosure provides a storage medium containing computer-executable instructions for performing the method of any one of the preceding claims when executed by a computer processor.
The present disclosure provides a data copy processing method, apparatus, electronic device and storage medium, which are applied to a RISC reduced instruction set architecture, and determine a data copy request message, where the data copy request message includes: a source data address, a destination data address, and a byte to be copied; determining whether the source data address and the target data address are both 16 bytes aligned according to the data copy request message; when the source data address and the target data address are 16 bytes aligned, copying the bytes to be copied from the source data address to the target data address by 128 bits by adopting a first access instruction group, and acquiring the rest bytes in the bytes to be copied; and copying the rest bytes from the source data address to the target data address by adopting a byte-by-byte copying mode or adopting 64-bit-based copying processing of a second access instruction group. Compared with the method for copying data by using the memory copy function memcpy in the prior art, the processing method provided by the disclosure can align the addresses first and then directly copy the bytes to be copied by using the first memory access instruction group, so that the processing efficiency and the operating speed of the copied data are effectively improved.
Drawings
Explicit examples of the present disclosure have been shown by the above figures and will be described in more detail later. These drawings and written description are not intended to limit the scope of the disclosed concepts in any manner, but rather to illustrate the concepts of the disclosure to those skilled in the art by reference to specific examples.
Fig. 1 is a schematic flow chart of a data copy processing method provided by the present disclosure;
FIG. 2 is a schematic flow chart of another data copy processing method provided by the present disclosure;
fig. 3 is a schematic structural diagram of a data copy processing apparatus provided in the present disclosure;
fig. 4 is a schematic diagram of a hardware structure of an electronic device provided in the present disclosure.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate examples consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
Detailed Description
To make the purpose, technical solutions and advantages of the disclosed examples clearer, the technical solutions in the disclosed examples will be clearly and completely described below with reference to the drawings in the disclosed examples.
The data copying by using the copying function is an indispensable step of a computer in the process of processing data. In the prior art, a computer performs copy processing on data by using some function instructions, for example, a memory copy function memcpy.
The computer performs a copy process on the data using some function instructions, for example, a memory copy function memcpy. In particular, the memcpy function may be used to copy n bytes to be copied from a source data address to a target data address. When the memcpy function is used for data copying, when a target data address stores a plurality of bytes, the stored bytes are covered after the memory copy function is executed; furthermore, when there is an address overlap between the target data address and the source data address, a portion of the bytes stored in the source data address that overlap the address to be copied may be overwritten after the memory copy function is executed. That is to say, when the source data address and the target data address are not aligned, the memcpy function copies n bytes to be copied in a byte-by-byte copying manner, and copies the n bytes after the addresses are aligned by using a cpu word length, where the cpu word length is generally 32 bits or 64 bits.
In the face of the above problems, the prior art uses the ldc1/sdc 164 bit load/store instruction to optimize the memory copy function memcpy so that it can perform operations even if the addresses are not aligned when data copy is performed. However, only 64 bits of data can be copied at a time in such a manner, and as the amount of copied data increases, the performance of the method is insufficient and the efficiency is reduced.
In order to solve the above problems, the present disclosure provides a data copy processing method, an apparatus, an electronic device, and a storage medium, in which the address is aligned first, and then the byte to be copied is directly copied by using the first access instruction group, so that the processing efficiency and the operating speed of the copy data are effectively improved.
For the sake of understanding, the technical terms related to the present disclosure will be explained:
n byte alignment: starting from the source data address src, n bytes are copied to the destination data address dest. Where, if src and dest can both divide by n, it is referred to as n-byte aligned source data address with the target data, for example, if src and dest can both divide by 32, it is referred to as 32-byte aligned source data address with the target data.
Fig. 1 is a schematic flowchart of a data copy processing method provided by the present disclosure, and as shown in fig. 1, the data copy processing method includes:
103, when the source data address and the target data address are aligned to 16 bytes, copying the bytes to be copied from the source data address to the target data address by 128 bits by adopting a first access instruction group, and acquiring the rest bytes in the bytes to be copied;
and 104, copying the rest bytes from the source data address to the target data address by adopting a byte-by-byte copying mode or adopting 64-bit-based copying processing of a second memory access instruction group.
It should be noted that the execution subject of the processing method for data copy provided by the present disclosure is a processing apparatus for data copy, and the processing method for data copy may be applied to an electronic device provided with the processing apparatus for data copy. Meanwhile, the processing method is applied to RISC reduced instruction set architecture which can specifically comprise MIPS, ARM, PowerPC and the like.
In addition, the processing device for data copy can be written by C/C + +, Java, Shell or Python; the electronic device may be, for example, a desktop computer, a tablet computer, a smart phone, etc.; the present disclosure does not set any limit to the electronic device.
In the data copy processing method provided by the present disclosure, first, the data copy processing apparatus determines a data copy request message, where the data copy request message includes: source data address src, destination data address dest, and the byte to be copied.
Subsequently, the processing device for data copy determines whether the source data address and the target data address are both 16-byte aligned according to the data copy request message. Specifically, as mentioned above, when the source data address src and the target data address dest are both divisible by 16, it is determined whether the source data address and the target data address are 16 bytes; and when any one of the source data address src and the target data address dest cannot be divided by 16, determining that the source data address and the target data address are not 16 bytes.
When the source data address src and the target data address dest are both 16 bytes aligned, a first memory access instruction group is adopted, and the bytes to be copied are copied from the source data address to the target data address by 128 bits, wherein the first memory access instruction group comprises gslqc1/gssqc1 instructions. Then, the processing device acquires the rest bytes in the bytes to be copied, and copies the rest bytes from the source data address to the target data address in a byte-by-byte copying mode or in a 64-bit-based copying process by adopting a second memory access instruction group, wherein the second memory access instruction group comprises an ldc1/sdc1 instruction.
The gslqc1/gssqc1 instructions in the first memory access instruction group can load/store 128-bit data, but require 16-byte alignment of addresses, so when the source data address src and the target data address dest are both 16-byte aligned, the gslqc1/gssqc1 instructions are used for processing, thereby effectively improving the copy efficiency.
Compared with the prior art that data is copied by using a memory copy function memcpy, under the condition that a source data address and a target data address are 16 bytes aligned, the method directly uses a first memory access instruction group comprising gslqc1/gssqc1 instructions to copy corresponding 128-bit data, and compared with the prior art that the data is copied by using a memory copy function memcpy, the processing efficiency is higher, and the method is favorable for improving the operational capability of electronic equipment.
On the basis of the above example, in order to further improve the processing efficiency of the processing method for data copy provided by the example of the present disclosure, fig. 2 is a schematic flow chart of another processing method for data copy provided by the present disclosure, as shown in fig. 2, the processing method for data copy includes:
if the source data address and the target data address are both 16 bytes aligned, go to step 203; otherwise, go to step 205;
and step 204, copying the rest bytes from the source data address to the target data address by adopting a byte-by-byte copying mode or adopting 64-bit-based copying processing of a second memory access instruction group.
and step 206, copying the bytes to be copied from the source data address to the target data address by adopting a first access instruction group, and acquiring the rest bytes in the bytes to be copied.
It should be noted that the execution subject of the processing method for data copy provided by the present disclosure is a processing apparatus for data copy, and the processing method for data copy may be applied to an electronic device provided with the processing apparatus for data copy. Meanwhile, the processing method is applied to RISC reduced instruction set architecture which can specifically comprise MIPS, ARM, PowerPC and the like.
In addition, the processing device for data copy can be written by C/C + +, Java, Shell or Python; the electronic device may be, for example, a desktop computer, a tablet computer, a smart phone, etc.; the present disclosure does not set any limit to the electronic device.
In the processing method for data copy provided by the present disclosure, similar to the foregoing example, first, the processing device for data copy will determine a data copy request message, wherein, as described above, the data copy request message includes: source data address src, destination data address dest, and the byte to be copied.
Subsequently, the processing device for data copy determines whether the source data address and the target data address are both 16-byte aligned according to the data copy request message. Specifically, as mentioned above, when the source data address src and the target data address dest are both divisible by 16, it is determined whether the source data address and the target data address are 16 bytes; and when any one of the source data address src and the target data address dest cannot be divided by 16, determining that the source data address and the target data address are not 16 bytes.
When the source data address src and the target data address dest are both 16 bytes aligned, a first memory access instruction group is adopted, and the bytes to be copied are copied from the source data address to the target data address by 128 bits, wherein the first memory access instruction group comprises gslqc1/gssqc1 instructions. Then, the processing device acquires the rest bytes in the bytes to be copied, and copies the rest bytes from the source data address to the target data address in a byte-by-byte copying mode or in a 64-bit-based copying process by adopting a second memory access instruction group, wherein the second memory access instruction group comprises an ldc1/sdc1 instruction.
Different from the foregoing example, when it is determined that the source data address and the target data address are not 16 bytes, alignment processing needs to be performed on the bytes to be copied, so that when the source data address and the target data address both show 16-byte alignment, a gslqc1/gssqc1 instruction is adopted to copy the bytes to be copied from the source data address to the target data address based on 64 bits, and the remaining bytes in the bytes to be copied are obtained.
Specifically, the aligning process is performed on the bytes to be copied, and the aligning process includes various implementation manners, wherein different aligning processes may be adopted based on the byte bit number of the misalignment portion:
for example, when it is determined that the byte misaligned portion of the source data address and the target data address exceeds 64 bits, the misaligned portion is copied using a second access instruction group including an ldc1/sdc1 instruction until the source data address and the target data address are both 16-byte aligned.
For another example, when it is determined that the byte misalignment portion of the source data address and the target data address does not exceed 64 bits, the byte to be copied is copied from the source data address to the target data address in a byte-by-byte copying manner until the source data address and the target data address are both 16 bytes aligned.
Therefore, compared with the prior art, in the case that the source data address and the target data address are 16-byte aligned, the present disclosure directly performs the copy processing of the corresponding 128-bit data by using the first access instruction group including the gslqc1/gssqc1 instruction, and in the case that the source data address and the target data address are 16-byte misaligned, first performs the alignment processing on the byte to be copied to make the source data address and the target data address both 16-byte aligned, and then performs the copy processing of the corresponding 128-bit data by using the first access instruction group including the gslqc1/gssqc1 instruction.
Fig. 3 is a schematic structural diagram of a processing apparatus for data copying according to the present disclosure, as shown in fig. 3, applied to a RISC reduced instruction set architecture, the processing apparatus including:
a transceiver unit 10, configured to determine a data copy request message, where the data copy request message includes: a source data address, a destination data address, and a byte to be copied;
a determining unit 20, configured to determine whether the source data address and the target data address are both 16-byte aligned according to the data copy request message;
the copying unit 30 is configured to, when the source data address and the target data address are 16-byte aligned, copy the to-be-copied bytes from the source data address to the target data address with 128 bits by using a first access instruction group, and obtain remaining bytes in the to-be-copied bytes; and the processor is further configured to copy the remaining bytes from the source data address to the target data address in a byte-by-byte copy manner or based on 64-bit copy processing by using a second access instruction group.
In other optional examples, the processing device further comprises:
a copy unit 30, configured to, when there is a 16-byte misalignment between the source data address and the target data address, perform alignment processing on the bytes to be copied, so that the source data address and the target data address are both 16-byte aligned; and copying the bytes to be copied from a source data address to the target data address by adopting a first memory access instruction group, and acquiring the rest bytes in the bytes to be copied.
In other optional examples, the copy unit 30 is configured to, when it is determined that a byte-misaligned portion of a source data address and a target data address exceeds 64 bits, copy the misaligned portion with a second access instruction group until the source data address and the target data address are both 16 bytes aligned.
In other optional examples, the copy unit 30 is configured to, when it is determined that the byte misalignment portion between the source data address and the target data address does not exceed 64 bits, perform a copy process on the byte to be copied from the source data address to the target data address in a byte-by-byte copy manner until the source data address and the target data address are both 16 bytes aligned.
In other optional examples, the copy unit 30 is configured to copy the remaining byte with the second access instruction group when it is determined that the remaining byte exceeds 64 bits; and when the residual bytes are determined not to exceed 64 bits, copying the residual bytes from the source data address to the target data address in a byte-by-byte copying mode.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process and corresponding beneficial effects of the system described above may refer to the corresponding process in the foregoing method example, and are not described herein again.
The processing device for data copy provided by the present disclosure is applied to a RISC reduced instruction set architecture, and determines a data copy request message; determining whether the source data address and the target data address are both 16 bytes aligned according to the data copy request message; when the source data address and the target data address are 16 bytes aligned, copying the bytes to be copied from the source data address to the target data address by 128 bits by adopting a first access instruction group, and acquiring the rest bytes in the bytes to be copied; and copying the rest bytes from the source data address to the target data address by adopting a byte-by-byte copying mode or adopting 64-bit-based copying processing of a second access instruction group. Compared with the prior art, the address is aligned firstly, and then the byte to be copied is directly copied by adopting the first access instruction group, so that the processing efficiency and the running speed of the copied data are effectively improved.
Fig. 4 is a schematic diagram of a hardware structure of an electronic device provided in the present disclosure, as shown in fig. 4, the electronic device includes:
a processor 42;
a memory 41 for storing processor-executable instructions;
wherein the memory 41 is configured to store instructions executable by the processor 42;
the processor 42, when executing the executable instructions, may perform any of the methods described above.
The memory 41 may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like. And processor 42 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital signal processor architectures (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessor architectures or other electronic components.
The above instructions may be written in languages such as C/C + +, Java, Shell, Python, etc., and this example is not intended to be limiting.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process and corresponding beneficial effects of the system described above may refer to the corresponding process in the foregoing method example, and are not described herein again.
The present disclosure provides a storage medium comprising instructions which, when executed on the computer, may carry out any of the methods described above.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (12)
1. A processing method for data copy, which is applied to RISC reduced instruction set architecture, the processing method comprising:
determining a data copy request message, the data copy request message comprising: a source data address, a destination data address, and a byte to be copied;
determining whether the source data address and the target data address are both 16 bytes aligned according to the data copy request message;
when the source data address and the target data address are 16 bytes aligned, copying the bytes to be copied from the source data address to the target data address by 128 bits by adopting a first access instruction group, and acquiring the rest bytes in the bytes to be copied;
and copying the rest bytes from the source data address to the target data address by adopting a byte-by-byte copying mode or adopting 64-bit-based copying processing of a second access instruction group.
2. The processing method of claim 1, further comprising:
when the source data address and the target data address are not aligned by 16 bytes, the byte to be copied is aligned, so that the source data address and the target data address are both aligned by 16 bytes;
and copying the bytes to be copied from a source data address to the target data address by adopting a first memory access instruction group, and acquiring the rest bytes in the bytes to be copied.
3. The processing method according to claim 2, wherein the aligning the bytes to be copied comprises:
when the byte misalignment part of the source data address and the target data address exceeds 64 bits, copying the misalignment part by adopting a second memory access instruction group until the source data address and the target data address are aligned by 16 bytes.
4. The processing method according to claim 2, wherein the aligning the bytes to be copied comprises:
when the byte misalignment part of the source data address and the target data address does not exceed 64 bits, copying the byte to be copied from the source data address to the target data address in a byte-by-byte copying mode until the source data address and the target data address are both 16 bytes aligned.
5. The method for processing data copy according to any one of claims 1 to 4, wherein the copying process of the remaining bytes from the source data address to the target data address includes:
when the remaining bytes exceed 64 bits, copying the remaining bytes by adopting a second memory access instruction group;
and when the residual bytes are determined not to exceed 64 bits, copying the residual bytes from the source data address to the target data address in a byte-by-byte copying mode.
6. A processing apparatus for data copying, applied to a RISC reduced instruction set architecture, the processing apparatus comprising:
a transceiving unit configured to determine a data copy request message, where the data copy request message includes: a source data address, a destination data address, and a byte to be copied;
a determining unit, configured to determine whether the source data address and the target data address are both 16-byte aligned according to the data copy request message;
the copying unit is used for copying the bytes to be copied from the source data address to the target data address by 128 bits by adopting a first access instruction group when the source data address and the target data address are aligned to 16 bytes, and acquiring the rest bytes in the bytes to be copied; and the processor is further configured to copy the remaining bytes from the source data address to the target data address in a byte-by-byte copy manner or based on 64-bit copy processing by using a second access instruction group.
7. The processing apparatus as in claim 6, further comprising:
the copying unit is used for aligning the bytes to be copied when the source data address and the target data address are not aligned by 16 bytes, so that the source data address and the target data address are both aligned by 16 bytes; and copying the bytes to be copied from a source data address to the target data address by adopting a first memory access instruction group, and acquiring the rest bytes in the bytes to be copied.
8. The processing apparatus as claimed in claim 7, wherein the copy unit is configured to, when it is determined that the byte-misaligned portion of the source data address and the target data address exceeds 64 bits, copy the byte-misaligned portion with a second access instruction group until the source data address and the target data address are both 16 byte-aligned.
9. The processing apparatus according to claim 7, wherein the copying unit is configured to, when it is determined that the byte misalignment portion between the source data address and the destination data address does not exceed 64 bits, copy the byte to be copied from the source data address to the destination data address in a byte-by-byte copying manner until the source data address and the destination data address are both 16 bytes aligned.
10. The processing apparatus according to any one of claims 6 to 9, wherein the copy unit is configured to copy the remaining byte using a second access instruction group when it is determined that the remaining byte exceeds 64 bits; and when the residual bytes are determined not to exceed 64 bits, copying the residual bytes from the source data address to the target data address in a byte-by-byte copying mode.
11. An electronic device, comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to:
determining a data copy request message, the data copy request message comprising: a source data address, a destination data address, and a byte to be copied;
determining whether the source data address and the target data address are both 16 bytes aligned according to the data copy request message;
when the source data address and the target data address are 16 bytes aligned, copying the bytes to be copied from the source data address to the target data address by 128 bits by adopting a first access instruction group, and acquiring the rest bytes in the bytes to be copied;
and copying the rest bytes from the source data address to the target data address by adopting a byte-by-byte copying mode or adopting 64-bit-based copying processing of a second access instruction group.
12. A storage medium containing computer-executable instructions for performing the method of any one of claims 1-5 when executed by a computer processor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911212805.1A CN110990298B (en) | 2019-12-02 | 2019-12-02 | Data copy processing method and device, electronic equipment and storage medium |
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