CN110990204A - Memory pressure testing method, device, equipment and computer readable storage medium - Google Patents
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Abstract
The application discloses a memory pressure testing method, a device, equipment and a computer readable storage medium. The method is suitable for a Grantly platform and a Purley platform, and comprises the steps of optimizing an edac driver of a current CPU model in advance and loading the edac driver into an operating system executing a current computer program; sending a request instruction for testing the maximum free memory, and taking the maximum free memory as a memory to be tested; for each test mode, calling threads with the same number as the CPU logic cores to perform read-write test on the memory to be tested; the test mode may be a simple read-write test mode, an address test mode, a forward algorithm test mode, a butterfly algorithm test mode, and a random number test mode. The method and the device realize the memory pressure test of each bit of the high-pressure and comprehensive coverage memory on the basis of being compatible with the Grantly platform and the Purley platform.
Description
Technical Field
The present disclosure relates to the field of hardware testing technologies, and in particular, to a method, an apparatus, a device, and a computer readable storage medium for testing memory pressure.
Background
The memory is a very large scale integrated circuit, the normal and stable operation of the computer can be influenced if one or a few transistors in the memory are damaged, and the fault phenomena shown at the same time are different, for example, a gold finger poor contact/falling off of capacitance resistance particles and the like can cause that the computer cannot be started or can be started normally but can be started for alarming, and the fault phenomena can easily position the memory. However, some fault memory problems are hidden deeply, for example, Single-bit error reporting/Row fault/column fault and other ECC error reporting are triggered only when a large-pressure and high-coverage test is performed on the memory.
However, the existing memory pressure testing method has fewer testing patterns, is incompatible with a purley platform, does not support a large-capacity memory test, has small coverage on a memory in the testing process, and cannot effectively detect faults such as Error Correction Code (ECC) error reporting and memtest.
In view of this, how to implement a test of high pressure and high coverage rate on the basis of being compatible with the Grantly platform and the Purley platform to improve the reliability and stability of the computer is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The application provides a memory pressure test method, a device, equipment and a computer readable storage medium, which realize the memory pressure test of each bit of a high-pressure and full-coverage memory on the basis of being compatible with a Grantly platform and a Purley platform.
In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:
an embodiment of the present invention provides a memory pressure testing method, which is suitable for a Grantly platform and a Purley platform, and includes:
optimizing the edac driver of the current CPU model in advance and loading the edac driver into an operating system executing the current computer program;
sending a request instruction for testing a maximum free memory, and taking the maximum free memory as a memory to be tested;
for each test mode, calling threads with the same number as the CPU logic cores to perform read-write test on the memory to be tested; the test mode is a simple read-write test mode, an address test mode, a forward algorithm test mode, a butterfly algorithm test mode and a random number test.
Optionally, after the step of calling the threads with the same number as the CPU logic cores to perform the pressure test on the memory to be tested for each test mode, the method further includes:
and outputting a pressure test result after performing a read-write test on the memory to be tested in various test modes.
Optionally, after outputting the pressure test result, the method further includes:
if the pressure test result indicates that the memory has no fault, detecting the mcelog, and if the mcelog does not have error report, determining that the memory to be tested has no fault;
and if the pressure test result is that the memory has a fault, displaying the address information of the fault bit to position the CPU slot position, the DIMM slot position and the channel information of the memory to be tested based on the edac mechanism.
Optionally, the pressure test result indicates that the memory fault is:
and if the expected value and the actual value of at least one bit are not matched, displaying the pressure test result of the memory fault.
Optionally, if the pressure test result is a memory fault, after the address information of the fault bit is displayed, the method further includes:
and backing up the address information of the fault bit, the CPU slot position where the memory to be tested is located, the DIMM slot position and the channel information into a fault log under a preset directory, and sending the fault log to a pre-bound client or a cloud.
Optionally, before sending the request instruction for testing the maximum free memory and using the maximum free memory as the memory to be tested, the method further includes:
judging whether a pressure test parameter setting instruction is received or not;
if yes, executing read-write test according to the pressure test parameters in the pressure test parameter setting instruction;
if not, executing the pressure test according to the default pressure test parameters;
the pressure testing parameters comprise a testing memory value, a testing circle number, a testing duration and a testing pressure value;
the default pressure test parameters are:
the testing memory value is the current maximum free memory, the number of testing turns is one turn, and the number of testing threads is the CPU logic core number value.
Optionally, the performing the read-write test according to the pressure test parameter in the pressure test parameter setting instruction includes:
taking a test memory value in the pressure test parameter setting instruction as the memory to be tested, and sending a request instruction for testing the memory to be tested;
and for each test mode, calling a thread matched with the test pressure value in the pressure test parameter setting instruction to perform read-write test on the memory to be tested, and stopping executing the read-write test operation and outputting a pressure test result when the test cycle number or the test time in the pressure test parameter setting instruction is reached.
Another aspect of the embodiments of the present invention provides a memory pressure testing apparatus, which is suitable for a Grantly platform and a Purley platform, and includes:
the pre-operation module is used for optimizing the edac driver of the current CPU model in advance and loading the edac driver into an operation system executing the current computer program;
the memory test request module is used for sending a request instruction for testing the maximum free memory and taking the maximum free memory as a memory to be tested;
the read-write test module is used for calling threads with the same number as the CPU logic cores to perform read-write test on the memory to be tested for each test mode; the test mode is a simple read-write test mode, an address test mode, a forward algorithm test mode, a butterfly algorithm test mode and a random number test mode.
An embodiment of the present invention further provides a memory pressure testing device, which includes a processor, where the processor is configured to implement the steps of the memory pressure testing method according to any one of the foregoing embodiments when executing a computer program stored in a storage.
Finally, an embodiment of the present invention provides a computer-readable storage medium, where a memory pressure test program is stored on the computer-readable storage medium, and when the memory pressure test program is executed by a processor, the steps of the memory pressure test method are implemented as in any one of the foregoing.
The technical scheme provided by the application has the advantages that the edac drive matched with the CPU model of the platform is optimized and loaded in advance, so that the memory pressure test can be compatible with a Purley platform; the method comprises the following steps of performing read-write test on the current maximum idle memory by using a plurality of test modes, and fully covering each bit of the memory; the threads with the same number as the CPU logic cores are called to carry out read-write test, the CPU resources are almost all used for reading and writing the memory, and the memory is subjected to large-pressure test, so that the memory pressure test with large pressure, high coverage rate and large capacity is realized, the problem of hidden deeper memory faults can be effectively triggered, the stability and the reliability of the memory are improved, and the reliable and stable operation of a computer is facilitated.
In addition, the embodiment of the invention also provides a corresponding implementation device, equipment and a computer readable storage medium for the memory pressure testing method, so that the method has higher practicability, and the device, the equipment and the computer readable storage medium have corresponding advantages.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the related art, the drawings required to be used in the description of the embodiments or the related art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for testing memory pressure according to an embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating another memory pressure testing method according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating an error report of a failed memory according to an embodiment of the present invention;
fig. 4 is a structural diagram of an embodiment of a memory pressure testing apparatus according to an embodiment of the present invention;
fig. 5 is a structural diagram of another embodiment of a memory pressure testing apparatus according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and claims of this application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may include other steps or elements not expressly listed.
Having described the technical solutions of the embodiments of the present invention, various non-limiting embodiments of the present application are described in detail below.
Referring to fig. 1, fig. 1 is a schematic flow chart of a memory pressure testing method provided in an embodiment of the present invention, and is suitable for a Grantly platform and a Purley platform, where the embodiment of the present invention may include the following:
s101: the edac driver for the current CPU model is optimized in advance and loaded into the operating system executing the current computer program.
In the present application, in order to make the computer program capable of implementing the memory pressure test compatible with the Purley platform, the edac driver of the current cpu model may be optimized and loaded, the computer program capable of implementing the memory pressure test is copied to an operating system, for example, a linux system with x 8664 bits, the computer program capable of implementing the memory pressure test may be named imt, and then the computer program capable of implementing the memory pressure test may be executed by executing the command "/imt". The epac is an error detection and correction module under the linux system, can read a chip set of a register when an error occurs, and is suitable for a CPU of intel.
Taking the cpu of skylake model of Purley platform as an example, the source code file of the edac driver is the path of skx _ edac.c, edit skx _ edac.c, add the code of error-reporting memory location to the dimmm slot and output the dimmm slot information to the/tmp/mce. Executing a command make CONFIG _ EDAC _ SKX ═ M-C/lib/modules/3.10.0-693.el 7.x86_ 64/built/M ═ pwd' modules recompile skx _ edac.ko to complete the optimization process, then copying skx _ edac.ko to the production system, and executing an insmodskx _ edac.ko loading driver.
S102: and sending a request instruction for testing the maximum free memory, and taking the maximum free memory as the memory to be tested.
In the present application, the maximum free memory is the maximum value of the free memory of the current platform, that is, in a default condition, the embodiment of the present invention performs a memory pressure test on the maximum free memory of the platform. It should be noted that the present application supports testing a memory above 1T, that is, the memory to be tested of the present application may be above 1T.
S103: and calling the threads with the same number as the CPU logic cores to perform read-write test on the memory to be tested for each test mode.
It can be understood that the operation of the memory by the user is either a read operation or a write operation, so that when the memory pressure is tested, the read/write operation test is also performed on the memory to be tested. In order to realize the high-pressure test, that is, to use most or all of the CPU resources of the platform for the memory pressure test, the memory to be tested may be subjected to a read-write test using threads having the same number as the number of the CPU logic cores. In order to ensure that the change of each bit of the tested memory can be covered and realize the memory pressure Test with high coverage rate, five Test patterns can be adopted, such as a simple Read-Write Test pattern (Write Read Test), an Address Test pattern (Address Test), a forward algorithm Test pattern (March Test), a butterfly algorithm Test pattern (ButterflyTest) and a Random number Test pattern (Random Test). Each test pattern has different emphasis points on the memory test, can comprehensively test the stability of the memory, and can accurately position the error-reporting memory to the dimm slot. The test process of the simple read-write test mode can be circulated for 16 times, wherein one of sixteen fixed values is completely written into the memory in each circulation, then the values in the memory are read one by one, whether the values are equal or not is judged, if the values are unequal, an error is reported to exit, after all the memory addresses are judged, the values are written in a negation mode, after the writing is finished, the values are read for judgment, if the values are equal, the test is passed, and if the values are unequal, an error is reported to exit; the implementation process of the address test mode can be that 16 rounds (loop) of tests are carried out on the divided memories, the address is written in the memories respectively as a value and an address negation as a value according to rules in each round, after the writing is finished, the value in the address is read, whether the read value meets the written rule or not is checked, if the read value meets the written rule, the test is successful, and if the read value does not meet the written rule, an error is reported and the memory is exited; the March (forward) algorithm test mode is a cycle of 4 times, one of four fixed values is written into the memory in each cycle, then the values in the memory are read one by one, whether the values are equal or not is judged, if the values are not equal, an error is reported to exit, if the values are equal, the values are directly negated and written into the memory again, after the values are written into the memory, the values are read again, whether the written values are the values after the negation is judged, if the values are equal, the test is passed, and if the values are not equal, an error is reported to; the writing rule of the butterfly algorithm test pattern is if (phase [ m ] [ n ] ═ 0) P _ test [ m ] [ n ] ═ pat; if (phase [ m ] [ n ] ═ 1) P _ test [ m ] [ n ] ═ pat; writing fixed data into the memory according to the rule, reading the data after writing, judging whether the writing rule is met, testing the writing rule to pass if the writing rule is met, and reporting an error to exit if the writing rule is not met; the test procedure of the random number test mode can be that the test memory is divided into 2 blocks with equal size, the generated random numbers are respectively written in the same offset positions of the two memories, then the two memories are read, the read values are compared, if the random numbers are equal, the test is passed, and if the random numbers are not equal, an error is reported and the test is exited.
In the technical scheme provided by the embodiment of the invention, the edac drive matched with the CPU model of the platform is optimized and loaded in advance, so that the memory pressure test can be compatible with a Purley platform; the method comprises the following steps of performing read-write test on the current maximum idle memory by using a plurality of test modes, and fully covering each bit of the memory; the threads with the same number as the CPU logic cores are called to carry out read-write test, the CPU resources are almost all used for reading and writing the memory, and the memory is subjected to large-pressure test, so that the memory pressure test with large pressure, high coverage rate and large capacity is realized, the problem of hidden deeper memory faults can be effectively triggered, the stability and the reliability of the memory are improved, and the reliable and stable operation of a computer is facilitated.
It can be understood that, according to the above embodiment, the memory is subjected to the pressure test under the Grantly platform and the Purley platform, the pressure and the coverage are maximum, and the problem memory reported by the pressure test can be positioned to the dimmm slot, so that an operator can conveniently replace the memory and perform the pressure test on the memory again. In order to improve the flexibility of the memory test and make it suitable for various application scenarios, the method can also control the pressure and the coverage of the memory according to the received test parameters when performing the pressure test, that is, before sending a request instruction for testing the maximum free memory and using the maximum free memory as the memory to be tested, the method further includes:
judging whether a pressure test parameter setting instruction is received or not;
if yes, executing read-write test according to the pressure test parameters in the pressure test parameter setting instruction; if not, executing the pressure test according to the default pressure test parameters;
the pressure testing parameters comprise a testing memory value, a testing circle number, a testing duration and a testing pressure value; the default pressure test parameters are: the testing memory value is the current maximum free memory, the number of testing turns is one turn, and the number of testing threads is the CPU logic core number value.
In addition, the present application provides another embodiment, please refer to fig. 2, which specifically includes the following contents:
s201: the edac driver for the current CPU model is optimized in advance and loaded into the operating system executing the current computer program.
S202: judging whether a test memory value setting instruction is received, if so, executing S203; if not, go to S204.
In order to realize the memory test with high coverage rate, the application defaults to carry out read-write test on the maximum idle memory of the current platform, and the test coverage rate can reach more than 95%. Of course, to achieve flexibility in memory stress testing, the size of the test memory may also be specified by a transfer function, such as "-m size", to the computer program implementing the memory stress test.
S203: and taking the memory information to be tested in the test memory value setting instruction as a memory to be tested, and sending a test memory request.
S204: and sending a request instruction for testing the maximum free memory, and taking the maximum free memory as the memory to be tested.
S205: judging whether a test pressure value setting instruction is received, if so, executing S206; if not, go to S207.
In order to realize the high-pressure memory test, the threads with the same number as the CPU logic cores are enabled by default to carry out the read-write test on the memory. Of course, to achieve flexibility in memory stress testing, it may also be specified to use a number of threads to read and write test the memory by passing a function, such as "-n number", to the computer program implementing the memory stress test.
S206: and for each test mode, performing read-write test on the memory to be tested by adopting the test pressure value in the test pressure value setting instruction.
S207: and calling the threads with the same number as the CPU logic cores to perform read-write test on the memory to be tested for each test mode.
S208: judging whether a test time setting instruction is received, if so, executing S209; if not, go to S210.
The method can end after performing one cycle of read-write test by adopting all test mode memories by default. Of course, to achieve flexibility in memory stress testing, the number of cycles run may also be specified by a transfer function, such as "-c cycle count", to the computer program implementing memory stress testing, and the time of run may also be specified by "-t time".
S209: and for each test mode, performing read-write test on the memory to be tested by adopting the number of test turns and/or the test duration in the test time setting instruction, and outputting a pressure test result after the test time is up.
S210: and outputting a pressure test result after performing read-write test on the memory to be tested in various test modes.
In the embodiment of the invention, for each test mode, a thread matched with the test pressure value in the pressure test parameter setting instruction is called to carry out read-write test on the memory to be tested, and when the test cycle number or the test time in the pressure test parameter setting instruction is reached, the execution of the read-write test operation is stopped, and the pressure test result is output. If there is a problem in the test, i.e. the expected value of a bit does not match the actual value, the imt procedure will report the address of the problem bit. That is, if there is a mismatch between the expected value and the actual value of at least one bit, a stress test result of the memory fault is output.
S211: judging whether the pressure test result has a memory fault, if so, executing S212; if not, S213 is executed.
S212: and displaying the address information of the fault bit to position the CPU slot position, the DIMM slot position and the channel information of the memory to be tested based on the edac mechanism.
In the application, the test result shows fail, the error-reported memory address can be displayed on the program running interface, the address of a problem bit reported by a computer program for realizing the memory pressure test is combined with an edac mechanism, the CPU socket and channel where the memory is located and the dimmm slot where the memory is located can be located, and meanwhile, the error-reported memory address can be analyzed into the corresponding socket/channel/dimm, and the memory specified by the dimmm slot is the fault memory tested by the pressure testing program. That is, after the computer program for implementing the memory pressure test is run, the system log and mce are checked to report errors, and it is found that neither the system log nor mce report errors, and 10000M memory test pass is performed. Fault memory error reporting fig. 3 shows mce error reporting checked after imt operation, and the dimm slot of the error memory can be seen through the error log. Socket is a slot of CPU, generally, 2/4 or more CPUs are available on a computer, and CPU is plugged in Socket. The first place to reach after the Channel comes out of the memory controller is where there can be multiple groups of DIMMs in each Channel. Diam (Dual In-line memory Module) is a memory module.
In addition, if the pressure test result is a memory fault, after or at the same time of displaying the address information of the fault bit, in order to quickly locate the fault, fault log information is stored, the address information of the fault bit, the position of the CPU slot where the memory to be tested is located, the position of the DIMM slot and channel information are backed up into a fault log under a preset directory, and the fault log is sent to a pre-bound client or a cloud.
S213: and detecting the mcelog, and if the mcelog detection does not report errors, determining that the memory to be detected has no fault.
If the test result shows pass, the memory to be tested has no obvious problem in terms of hardware, and if the mcelog (machinecheck engine) has no error, the memory to be tested has no problem. Mcelog is a tool used on Linux systems to check for hardware errors, particularly memory and CPU errors.
Therefore, the embodiment of the invention realizes the memory pressure test of each bit of the memory with large pressure and full coverage on the basis of being compatible with the Grantly platform and the Purley platform.
The embodiment of the invention also provides a corresponding implementation device for the memory pressure testing method, so that the method has higher practicability. In the following, the memory pressure testing apparatus provided by the embodiment of the present invention is introduced, and the memory pressure testing apparatus described below and the memory pressure testing method described above may be referred to correspondingly.
Referring to fig. 4, fig. 4 is a structural diagram of a memory pressure testing apparatus according to an embodiment of the present invention, which is suitable for a Grantly platform and a Purley platform, and the apparatus may include:
and the pre-operation module 401 is configured to optimize the edac driver of the current CPU model in advance and load the edac driver into an operating system executing the current computer program.
A test memory request module 402, configured to send a request instruction for testing the maximum free memory, and use the maximum free memory as the memory to be tested.
The read-write testing module 403 is configured to call, for each testing mode, threads with the same number as the CPU logic cores to perform read-write testing on the memory to be tested; the test mode is a simple read-write test mode, an address test mode, a forward algorithm test mode, a butterfly algorithm test mode and a random number test mode.
Optionally, in some embodiments of this embodiment, referring to fig. 5, the apparatus may further include a pressure test result output module 404, configured to output a pressure test result after performing a read-write test on the memory to be tested in each test mode; or for each test mode, calling a thread matched with the test pressure value in the pressure test parameter setting instruction to perform read-write test on the memory to be tested, and stopping executing the read-write test operation and outputting a pressure test result when the test cycle number or the test time in the pressure test parameter setting instruction is reached.
In another implementation manner of this embodiment, the apparatus may further include a result processing module 405, for detecting the mcelog if the pressure test result indicates that the memory has no fault, and if the mcelog detection has no error, the memory to be detected has no fault; and if the pressure test result is that the memory has a fault, displaying the address information of the fault bit to position the CPU slot position, the DIMM slot position and the channel information of the memory to be tested based on the edac mechanism.
As an alternative embodiment, the apparatus may further include a pressure parameter setting module 406, for example, configured to set a test memory value and/or a number of test turns and/or a test duration and/or a test pressure value of the memory pressure test according to an instruction input by the user.
The functions of the functional modules of the memory pressure testing apparatus according to the embodiment of the present invention may be specifically implemented according to the method in the foregoing method embodiment, and the specific implementation process may refer to the related description of the foregoing method embodiment, which is not described herein again.
Therefore, the embodiment of the invention realizes the memory pressure test of each bit of the memory with large pressure and full coverage on the basis of being compatible with the Grantly platform and the Purley platform.
An embodiment of the present invention further provides a memory pressure testing device, which specifically includes:
a memory for storing a computer program;
a processor for executing a computer program to implement the steps of the memory pressure testing method according to any of the above embodiments.
The functions of each functional module of the memory pressure testing device according to the embodiments of the present invention may be specifically implemented according to the method in the foregoing method embodiments, and the specific implementation process may refer to the related description of the foregoing method embodiments, which is not described herein again.
Therefore, the embodiment of the invention realizes the memory pressure test of each bit of the memory with large pressure and full coverage on the basis of being compatible with the Grantly platform and the Purley platform.
The embodiment of the present invention further provides a computer-readable storage medium, in which a memory pressure test program is stored, and the steps of the memory pressure test method according to any one of the above embodiments are performed when the memory pressure test program is executed by a processor. The storage medium may be various media capable of storing program codes, such as a U disk, a removable hard disk, a read-only memory, a random access memory, a magnetic disk, or an optical disk.
The functions of the functional modules of the computer-readable storage medium according to the embodiment of the present invention may be specifically implemented according to the method in the foregoing method embodiment, and the specific implementation process may refer to the related description of the foregoing method embodiment, which is not described herein again.
Therefore, the embodiment of the invention realizes the memory pressure test of each bit of the memory with large pressure and full coverage on the basis of being compatible with the Grantly platform and the Purley platform.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above detailed description is provided for a memory pressure testing method, apparatus, device and computer readable storage medium provided by the present application. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present application.
Claims (10)
1. A memory pressure test method is characterized in that the method is suitable for a Grantly platform and a Purley platform and comprises the following steps:
optimizing the edac driver of the current CPU model in advance and loading the edac driver into an operating system executing the current computer program;
sending a request instruction for testing a maximum free memory, and taking the maximum free memory as a memory to be tested;
for each test mode, calling threads with the same number as the CPU logic cores to perform read-write test on the memory to be tested; the test mode is a simple read-write test mode, an address test mode, a forward algorithm test mode, a butterfly algorithm test mode and a random number test.
2. The method according to claim 1, wherein after the memory under test is pressure-tested by calling threads with the same number as that of the CPU logic cores for each test mode, the method further comprises:
and outputting a pressure test result after performing a read-write test on the memory to be tested in various test modes.
3. The method according to claim 2, further comprising, after outputting the pressure test result:
if the pressure test result indicates that the memory has no fault, detecting the mcelog, and if the mcelog does not have error report, determining that the memory to be tested has no fault;
and if the pressure test result is that the memory has a fault, displaying the address information of the fault bit to position the CPU slot position, the DIMM slot position and the channel information of the memory to be tested based on the edac mechanism.
4. The memory pressure testing method according to claim 3, wherein the pressure testing result is that the memory fault is:
and if the expected value and the actual value of at least one bit are not matched, displaying the pressure test result of the memory fault.
5. The method according to claim 4, wherein if the stress test result is a memory fault, after displaying the address information of the fault bit, the method further comprises:
and backing up the address information of the fault bit, the CPU slot position where the memory to be tested is located, the DIMM slot position and the channel information into a fault log under a preset directory, and sending the fault log to a pre-bound client or a cloud.
6. The method according to any one of claims 1 to 5, wherein before sending the request instruction for testing the maximum free memory and using the maximum free memory as the memory to be tested, the method further comprises:
judging whether a pressure test parameter setting instruction is received or not;
if yes, executing read-write test according to the pressure test parameters in the pressure test parameter setting instruction;
if not, executing the pressure test according to the default pressure test parameters;
the pressure testing parameters comprise a testing memory value, a testing circle number, a testing duration and a testing pressure value;
the default pressure test parameters are:
the testing memory value is the current maximum free memory, the number of testing turns is one turn, and the number of testing threads is the CPU logic core number value.
7. The memory pressure testing method according to claim 6, wherein the performing of the read-write test according to the pressure testing parameter in the pressure testing parameter setting instruction comprises:
taking a test memory value in the pressure test parameter setting instruction as the memory to be tested, and sending a request instruction for testing the memory to be tested;
and for each test mode, calling a thread matched with the test pressure value in the pressure test parameter setting instruction to perform read-write test on the memory to be tested, and stopping executing the read-write test operation and outputting a pressure test result when the test cycle number or the test time in the pressure test parameter setting instruction is reached.
8. The memory pressure testing device is suitable for a Grantly platform and a Purley platform, and comprises the following components:
the pre-operation module is used for optimizing the edac driver of the current CPU model in advance and loading the edac driver into an operation system executing the current computer program;
the memory test request module is used for sending a request instruction for testing the maximum free memory and taking the maximum free memory as a memory to be tested;
the read-write test module is used for calling threads with the same number as the CPU logic cores to perform read-write test on the memory to be tested for each test mode; the test mode is a simple read-write test mode, an address test mode, a forward algorithm test mode, a butterfly algorithm test mode and a random number test mode.
9. Memory stress testing apparatus comprising a processor for implementing the steps of the memory stress testing method according to any one of claims 1 to 7 when executing a computer program stored in a memory.
10. A computer-readable storage medium, having a memory stress test program stored thereon, which when executed by a processor implements the steps of the memory stress testing method of any of claims 1 to 7.
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