CN110990062B - Instruction prefetching filtering method - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 21
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- 239000013598 vector Substances 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 6
- 230000001960 triggered effect Effects 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000008030 elimination Effects 0.000 description 3
- 238000003379 elimination reaction Methods 0.000 description 3
- 230000008520 organization Effects 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention relates to a method for filtering instruction prefetching.A filtering device for instruction prefetching is arranged between an instruction Cache and a next-level storage system, and comprises a filtering buffer of a plurality of entries, wherein the filtering buffer of each entry corresponds to a basic page and is used for recording and tracking Cache lines loaded into the instruction Cache in the basic page; and directly inquiring the instruction prefetching filter device when the instruction stream is prefetched every time to check whether the prefetched Cache line is in the instruction Cache or not, and then determining whether to send an instruction prefetching request to a next-level storage system or not according to an inquiry result. The invention can avoid contention of the operation contention port related to the instruction prefetch inquiry and other instruction caches, improve the utilization rate of the instruction caches and further improve the performance of the processor.
Description
Technical Field
The invention relates to the technical field of modern microprocessor design, in particular to a method for filtering instruction prefetching.
Background
Instruction caching is a key resource in modern high-performance processors, and the design of an instruction fetching pipeline mainly goes around the instruction caching. In order to improve the utilization rate of the instruction Cache and reduce instruction fetching inquiry missing, an instruction prefetching technology is often adopted to load the instruction Cache line to be used into the instruction Cache in advance. Before sending out a prefetch request, whether a prefetched Cache line is in an instruction Cache or not is firstly determined, so that the instruction Cache needs to be inquired by using a prefetch address, and if the prefetched Cache line is loaded, the prefetch request does not need to be sent out.
The instruction cache capacity in the high-performance processor is large, the high-performance processor is usually realized by adopting a customized array, the instruction Tag and the instruction data are divided into two arrays due to different functions, and the number of read-write ports is limited. Because the fetch query is on the critical path of the instruction pipeline, the fetch query is required in each cycle, and the high-performance processor usually requires the instruction data to be read within 1 cycle, the fetch query is usually provided with a dedicated port to ensure that the fetch query is not interfered or interrupted. In addition to the fetch query, the instruction cache is also capable of handling coherency requests, prefetch queries, instruction fills (writes), flushes, etc. at the same time, which are infrequent relative to the fetch query and therefore share 1 port. In order to ensure that the instruction cache function is normally completed, the processing priority of the prefetch query is the lowest, so when an instruction cache port conflict occurs, a prefetch request may not be issued, and therefore prefetching cannot be fully utilized to improve the hit rate of the instruction cache.
In summary, the handling of instruction prefetching is limited by the number of ports in the instruction cache, and prefetching has to be aborted in the event of a conflict with other high priority requests. Due to the considerations of the cost of logic implementation and the cost of physical implementation, adding ports to the instruction Cache is not cost effective.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method for filtering instruction prefetching, which avoids contention of ports between prefetching query and other instruction cache operations, improves instruction cache utilization, and further improves processor performance.
The technical scheme adopted by the invention for solving the technical problems is as follows: the method comprises the steps that an instruction prefetching filtering device is arranged between an instruction Cache and a next-level storage system, and the instruction prefetching filtering device comprises a plurality of filtering buffers of entries, wherein each filtering buffer of an entry corresponds to a basic page and is used for recording and tracking Cache lines loaded into the instruction Cache in the basic page; and directly inquiring the instruction prefetching filtering device during prefetching every time to check whether the prefetched Cache line is in the instruction Cache or not, and then determining whether to send an instruction prefetching request to a next-level storage system or not according to an inquiry result.
The filtering buffer of each entry is provided with an effective bit, a virtual page base address, a physical page base address, a process number and a thread number; and the filtering buffer of each entry also sets a Cache line effective bit vector as an indication mark of the loaded Cache line in the page, and the Cache lines in the basic page correspond to the effective bit indication vectors one by one.
When instruction prefetching is triggered, a prefetching page base address is used for inquiring the instruction prefetching filter device, if the page is hit to indicate that the page is loaded, an offset value in the page is used for checking a Cache line effective bit vector, if the Cache line is loaded, prefetching is not required to be sent, otherwise, prefetching is sent; if not, the Cache line is not in the instruction Cache, and prefetching is sent out; when the prefetch is sent out, the state of the instruction prefetch filtering device is updated according to the previous query result, if the Cache line is hit, the effective position of the Cache line at the offset corresponding to the hit entry is started, otherwise, a new filtering buffer entry is distributed and the effective position of the Cache line at the corresponding position is started, which indicates that the Cache line is loaded.
When the instruction prefetching query is not hit, the basic page where the prefetching target is located is not loaded, if the operating system uses the basic page and the buffer depth of the instruction prefetching filtering device is the same as the number of entries of the instruction stream TLB, the instruction stream page table prefetching is performed by using the query result of the instruction prefetching filtering device; if the operating system uses a large page or the instruction prefetching filtering buffer depth is smaller than the number of the instruction stream TLB entries, the prefetching inquiry result of the instruction prefetching filtering device is used as a condition for triggering the prefetching of the instruction stream page table entries.
If the instruction Cache queries the missing, when the instruction Cache initiates an instruction request to a next-level storage system, the instruction Cache queries the instruction prefetching filter device by using the missing instruction address, if the instruction Cache queries the missing instruction address, the effective position of the Cache line at the offset corresponding to the entry is hit, otherwise, a new filtering buffer entry is allocated, and the effective position of the Cache line at the corresponding position is marked to indicate that the Cache line is loaded.
When Cache lines are eliminated due to the fact that the instruction Cache is filled, the eliminated Cache line addresses are used for inquiring the instruction prefetching filtering device, and the corresponding Cache line effective bits in the hit page are cleared to be 0.
Synchronously refreshing the instruction pre-fetching filter device when a refreshing request exists; for instruction cache refreshing, if the instruction cache refreshing is full refreshing, all the instruction prefetch filtering buffer entries are invalidated; if the Cache line is refreshed, the refreshing address is used for inquiring the instruction prefetching filter device, when the Cache line is hit and the corresponding Cache line is valid, the valid bit is cleared to be 0, otherwise, no operation is performed; for instruction stream TLB refreshing, the effective bit of the hit page is cleared to 0 by using a refreshing address to query the instruction prefetching filter device.
When Cache consistency invalidation request exists, the consistency request address is used for simultaneously inquiring the instruction Cache and the instruction prefetching filtering device, when the instruction Cache is hit, a hit Cache line is invalidated, and meanwhile, the corresponding Cache line valid position in a hit entry of the instruction prefetching filtering device is invalidated; if the instruction cache is missed, no operation is performed.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention can track the Cache line state loaded in the instruction Cache in real time and decouple the dependence of the instruction prefetch inquiry on the instruction Cache, thereby being convenient to carry out prefetch inquiry, filtering redundant prefetch and preventing the prefetch from being interfered by other instruction Cache operations and being incapable of being sent out, thereby improving the utilization rate of the instruction Cache. The instruction prefetching query result can also guide the prefetching of the instruction flow page table entry so as to reduce the instruction flow page missing times and further improve the processor performance. In addition, the invention is managed according to basic page organization, and the page only corresponds to one effective bit vector, although the synchronous operation with the instruction cache has some overhead, the realization is simpler.
Drawings
FIG. 1 is a schematic diagram of the location of an instruction prefetch filter apparatus in a system according to the present invention;
FIG. 2 is a flow chart of the query of the instruction prefetch filter apparatus according to the present invention;
FIG. 3 is a diagram of an instruction prefetch filter apparatus directing instruction stream TLB prefetching according to the present invention.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The embodiment of the invention relates to an instruction prefetching filtering method, wherein an instruction prefetching filtering device is arranged between an instruction cache and a next-level storage system, the instruction prefetching filtering device is closely interacted with the instruction cache and the next-level storage system, and the position of the instruction prefetching filtering device in the system is shown in figure 1. The instruction pre-fetching filtering device is used for carrying out organization management by taking a basic page as a unit and is provided with a filtering buffer of a plurality of items. The filtering buffer of each entry corresponds to a basic page and is used for recording and tracking Cache lines loaded into the instruction Cache in the basic page, and the whole instruction pre-fetching filtering device records all the Cache lines loaded into the instruction Cache. The instruction pre-fetching filtering device adopts a fully-associative structure, and is directly inquired during pre-fetching each time to check whether a pre-fetched Cache line is in an instruction Cache or not, and then whether an instruction pre-fetching request is sent to a secondary Cache or a next-level memory bank or not is determined according to an inquiry result.
Table 1 shows the settings of the contents of the filter buffer entry in the instruction prefetch filter apparatus according to this embodiment. The filtering buffer of each entry is provided with a valid bit which indicates whether the current page is loaded or not; the filtering buffer records information such as a virtual page base address, a process number, a thread number, a physical page base address and the like of a loaded page so as to facilitate the hit judgment during the prefetching query, the instruction Cache elimination query, the refreshing query and the Cache consistency request query; and the filtering buffer of each entry is also provided with a Cache line valid bit vector ValidVec as an indication mark of the loaded Cache line in the page, the basic page comprises a plurality of Cache lines, and the valid bit indicates the number of bits of the vector and corresponds to the Cache lines one by one. Assuming that the basic page size is 4KB and the Cache line size is 128B, the Cache line valid bit vector ValidVec has 32 bits in total.
Table 1 table of contents of filter buffer entries of instruction prefetch filter apparatus
The query judgment process of the instruction prefetch filter apparatus is shown in fig. 2, and first, corresponding hit judgment is performed according to the address type carried by the query request. If the virtual address is the virtual address, the virtual page base address VPageTag, the process number UPN and the thread number Tid need to be compared, if the virtual address is the physical address, the virtual page base address VPageTag only needs to be compared, and if the contents are matched and the item is effective, the virtual address is hit. If not, the inquired Cache line is not in the instruction Cache, if the Cache line is hit, the valid bit vector ValidVec of the Cache line is inquired in the hit entry according to the offset value in the page, if the valid bit mark of the Cache line at the corresponding position is valid, the inquired Cache line is in the instruction Cache, otherwise, the Cache line is not loaded in the instruction Cache.
After the prefetch request is successfully sent to the next-level storage system, the prefetched Cache line needs to be registered in the instruction prefetch filter device. According to the previous query result, if the prefetch request of the instruction prefetch filter device is missed, a buffer entry is newly allocated. At this point, if there are free entries, they can be allocated directly, otherwise, an entry is eliminated using the LRU algorithm. After the buffer entries are allocated, filling out the virtual page address, the process number, the thread number and the physical page address (the physical page address is obtained by querying the instruction TLB) of the prefetch Cache line, setting the valid bit, and starting the Cache line valid position of the corresponding position in the ValidVec. If the prefetch query hits the filter buffer, the Cache line valid location at the corresponding location in the hit entry ValidVec is directly started, indicating that the Cache line has been loaded.
The prefetch query results of the instruction prefetch filter may be used to direct the prefetching of instruction stream page table entries, as shown in FIG. 3. When the instruction prefetch inquiry does not hit, the corresponding basic page is not loaded in the instruction prefetch filter device. If the operating system uses a basic page and the buffering depth of the instruction prefetching filtering device is the same as the number of entries of the instruction stream TLB, a page fault exception is bound to occur when the prefetched Cache line is accessed by a subsequent instruction fetching. In this case, the instruction prefetch filter not only tracks the loaded instruction cache line, but also records the loaded instruction flow page table entry, so that the prefetch of the instruction flow page table entry can be performed using the prefetch lookup result of the instruction prefetch filter. When the operating system uses large page mode, one page table entry may correspond to multiple base pages. When the instruction prefetching query is not hit, although the corresponding basic page is not loaded into the instruction prefetching filtering device, the corresponding page table is not loaded into the instruction stream TLB, and a page missing exception does not necessarily occur when a subsequent instruction is accessed to the prefetched Cache line, the prefetching query result of the instruction prefetching filtering device can be used as a condition for triggering the prefetching of the instruction stream page table entry.
Therefore, for the condition that the prefetch query filtering buffer is not hit, the basic page where the prefetch Cache line is located is not loaded, and at the moment, the page prefetching can be performed by utilizing the query result of the instruction prefetch filtering device according to specific needs and implementation, so that the instruction stream page missing frequency is reduced, and the performance of the processor is further improved.
Because the instruction prefetching filtering buffer tracks and records all loaded Cache lines in the instruction Cache, when operations (including filling, elimination, consistency invalidation request and refreshing) affecting the state of the instruction Cache are executed, the instruction prefetching filtering buffer needs to be updated synchronously, and the state of the two is guaranteed to be consistent all the time. Therefore, the instruction prefetching filter device and the instruction Cache are always kept synchronous during operation, and Cache lines loaded in the instruction Cache are indicated in real time. The synchronous operation between the instruction Cache and the instruction pre-fetching filtering device comprises the operations of instruction fetch missing registration, cache line elimination synchronization, refreshing synchronization and Cache consistency synchronization.
When the instruction fetch query is missing, the Cache line is not in the instruction Cache, and is not in the instruction prefetch filter. When an instruction Cache initiates an instruction fetching request to a lower-level storage system, a missing instruction fetching address is used for inquiring the instruction prefetching filtering device, if the instruction is hit, the valid position of a Cache line at the offset corresponding to the ValidVec of a hit entry is started, otherwise, a new filtering buffering entry is distributed, and the valid position 1 of the Cache line at the corresponding position in the ValidVec is used for indicating that the Cache line is loaded. When in allocation, if a free entry is available, the allocation can be directly carried out, otherwise, an entry is replaced by using an LRU algorithm.
When the Cache line is eliminated every time when the instruction Cache is filled, the eliminated Cache line physical address is used for inquiring the instruction prefetching filtering device, and if the instruction is hit, the Cache line effective bit corresponding to the ValidVec in the hit page is cleared to be 0.
When Cache consistency invalidation request exists, the consistency request address is used for simultaneously inquiring the instruction Cache and the instruction prefetching filtering device, and the Cache consistency request from the next-level storage system uses the physical address. When the Cache of the instruction is hit, the hit Cache line is invalid, at the moment, the instruction prefetching filter device is also hit, and the Cache line valid position corresponding to the ValidVec in the hit entry is invalid; otherwise, if the instruction cache is not hit, no operation is performed.
When a refresh request is sent, no matter the command cache is refreshed or the command stream TLB is refreshed, the command pre-fetching filter device is synchronously refreshed, and the refreshing generally adopts virtual addresses. For instruction cache refreshing, if the instruction cache refreshing is full refreshing, all the instruction prefetch filtering buffer entries are invalidated; if the Cache line is refreshed, the refreshing address is used for inquiring the instruction prefetching filtering device, when the Cache line is hit and the corresponding Cache line is valid, the valid bit is cleared to be 0, otherwise, no operation is carried out. For instruction flow TLB refreshing, the instruction prefetching filter device is queried by using a refreshing address, a plurality of pages can be hit in a large page mode, and valid bits of all the hit pages are cleared to be 0.
The Cache line state loaded in the instruction Cache can be tracked in real time, the dependence of the instruction prefetching query on the instruction Cache is decoupled, therefore, the prefetching query can be conveniently carried out, the redundant prefetching is filtered, the phenomenon that the prefetching cannot be sent out due to the interference of other instruction Cache operations is prevented, and the instruction Cache utilization rate is improved. The instruction prefetching query result can also guide the prefetching of the instruction flow page table entry so as to reduce the instruction flow page missing times and further improve the processor performance. In addition, the invention is managed according to basic page organization, and the page only corresponds to one effective bit vector, although the synchronous operation with the instruction cache has some overhead, the realization is simpler.
Claims (8)
1. A method for filtering instruction prefetching is characterized in that an instruction prefetching filtering device is arranged between an instruction Cache and a next-level storage system, and the instruction prefetching filtering device comprises a plurality of filtering buffers of entries, wherein each filtering buffer of an entry corresponds to a basic page and is used for recording and tracking Cache lines loaded into the instruction Cache in the basic page; and directly inquiring the instruction prefetching filter device during prefetching every time to check whether the prefetched Cache line is in the instruction Cache or not, and then determining whether to send an instruction prefetching request to a next-level storage system or not according to an inquiry result.
2. The instruction prefetch filtering method of claim 1, wherein the filter buffer of each entry is provided with a valid bit, a virtual page base address, a physical page base address, a process number, and a thread number; and the filtering buffer of each entry also sets the effective bit vector of the Cache line as an indication mark of the Cache line loaded in the page, and the Cache lines in the basic page correspond to the effective bit indication vectors one by one.
3. The method of claim 1, wherein when instruction prefetching is triggered, the instruction prefetching filtering apparatus is queried using a prefetching page base address, if the hit indicates that the page has been loaded, then an offset value in the page is used to look up a Cache line valid bit vector, if the Cache line has been loaded, the prefetching is not required to be issued, otherwise, the prefetching is issued; if not, the Cache line is not in the instruction Cache, and prefetching is sent out; when the prefetch is sent out, the state of the instruction prefetch filtering device is updated according to the previous query result, if the Cache line is hit, the effective position of the Cache line at the offset corresponding to the hit entry is started, otherwise, a new filtering buffer entry is distributed and the effective position of the Cache line at the corresponding position is started, which indicates that the Cache line is loaded.
4. The method as claimed in claim 3, wherein when the instruction prefetch query is not hit, the basic page where the prefetch target is located is not loaded yet, and if the operating system uses the basic page and the buffer depth of the instruction prefetch filter is the same as the number of entries of the instruction stream TLB, the instruction stream page table prefetch is performed using the query result of the instruction prefetch filter; if the operating system uses large pages or the filtering buffer depth of the instruction prefetching is smaller than the number of the TLB entries of the instruction stream, the prefetching inquiry result of the instruction prefetching filtering device is used as a condition for triggering the prefetching of the entry of the instruction stream page table.
5. The method according to claim 1, wherein if the instruction fetch query misses, when the instruction Cache initiates an instruction fetch request to a next-level storage system, the instruction fetch address missing is used to query the instruction prefetch filtering apparatus, if the instruction Cache hits, a Cache line valid location at an offset corresponding to the entry is hit, otherwise, a new filtering buffer entry is allocated and a Cache line valid location at a corresponding location is marked, indicating that the Cache line is loaded.
6. The method of claim 1, wherein each time Cache line eviction is caused by filling the instruction Cache, the evicted Cache line address is used to query the instruction prefetch filtering device, and the corresponding Cache line valid bit in the hit page is cleared to 0.
7. The method of claim 1, wherein the instruction prefetch filter means is refreshed synchronously whenever there is a refresh request; for instruction cache refreshing, if the instruction cache refreshing is full refreshing, all the instruction prefetch filtering buffer entries are invalidated; if the Cache line is refreshed, the refreshing address is used for inquiring the instruction prefetching filter device, when the Cache line is hit and the corresponding Cache line is valid, the valid bit is cleared to be 0, otherwise, no operation is performed; for instruction stream TLB refreshing, the effective bit of the hit page is cleared to 0 by using a refreshing address to query the instruction prefetching filter device.
8. The method according to claim 1, wherein when there is a Cache coherence invalidation request, the coherence request address is used to query the instruction Cache and the instruction prefetching filter at the same time, when the instruction Cache is hit, the hit Cache line is invalidated, and the corresponding Cache line valid location in the hit entry of the instruction prefetching filter is invalidated; if the instruction cache is missed, no operation is performed.
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