CN110989750B - Driver control circuit applied to optical module - Google Patents
Driver control circuit applied to optical module Download PDFInfo
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- CN110989750B CN110989750B CN201911074350.1A CN201911074350A CN110989750B CN 110989750 B CN110989750 B CN 110989750B CN 201911074350 A CN201911074350 A CN 201911074350A CN 110989750 B CN110989750 B CN 110989750B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/461—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using an operational amplifier as final control device
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/40—Transceivers
Abstract
The invention relates to a driver control circuit applied to an optical module. The driver control circuit comprises a power supply, a driver and a current constant control circuit; the power supply is used for supplying power to the driver; wherein, the output voltage of the power supply is adjustable; the constant current control circuit is respectively electrically connected with the power supply and the driver and is used for sampling the power supply current of the power supply to the driver, converting the power supply current into power supply voltage, and outputting negative gate voltage to the driver after voltage division, proportional-integral operation and output clamping control are carried out on the power supply voltage. This application gathers the power supply voltage of power to the driver through setting up the invariable control circuit of electric current, then handles the back to this power supply voltage, exports a negative gate voltage to driver, can guarantee that the electric current of exporting to the driver is stable in the full operating temperature scope to avoid in driver operating temperature scope signal output along with the condition such as temperature drift, distortion appear.
Description
Technical Field
The present invention relates to the field of optical communications, and in particular, to a driver control circuit applied to an optical module.
Background
The speed of data signals in the optical communication field is high, generally, the data signals are G (10e9) baud, meanwhile, the amplitude and the driving capacity of an electric signal required by electro-optical modulation reach certain values, and a radio frequency driver is generated for realizing the purpose.
The traditional radio frequency driver chip is made of semiconductor materials, mainly GaAs, AlGaAs and InP, a stable working point in a working temperature range can drift along with the temperature, signals can be distorted accordingly, and the key for ensuring the quality of electro-optical modulation and optical signals is how to ensure the stability of output signals in the whole temperature range.
Disclosure of Invention
In view of the above, it is necessary to provide a driver control circuit applied to an optical module.
A driver control circuit applied to an optical module comprises a driver, a power supply and a current constant control circuit;
the power supply is used for supplying power to the driver; wherein the output voltage of the power supply is adjustable;
the constant current control circuit is respectively electrically connected with the power supply and the driver and is used for sampling the power supply current of the power supply to the driver, converting the power supply current into power supply voltage, and outputting negative gate voltage to the driver after voltage division, proportional-integral operation and output clamping control are carried out on the power supply voltage.
In one embodiment, the power supply comprises a Buck-Boost power supply chip.
In one embodiment, the current constant control circuit comprises a current sampling circuit, a proportional-integral circuit and an output clamping control circuit;
the current sampling circuit is electrically connected with the driver and used for sampling the power supply current of the power supply to the driver and converting the power supply current into power supply voltage for output;
the proportional-integral circuit is electrically connected with the current sampling circuit and is used for carrying out proportional-integral operation on the power supply voltage;
and the output clamping control circuit is electrically connected with the proportional integral circuit and is used for outputting negative gate voltage to the driver after carrying out output clamping control on the power supply voltage subjected to proportional integral operation.
In one embodiment, the current sampling circuit comprises a sampling resistor R14, voltage dividing resistors R10, R11, R17 and R19, a negative feedback amplifying resistor R20 and an operational amplifier U7A;
a first end of the sampling resistor R14 is connected with an output end of the power supply, a second end of the sampling resistor R14 is connected with a first end of the voltage division resistor R17, and a second end of the voltage division resistor R17 is connected with an inverting input end of the operational amplifier U7A; a first end of the voltage dividing resistor R11 is connected with a first end of the sampling resistor R14, and a second end of the voltage dividing resistor R11 is connected with a non-inverting input end of the operational amplifier U7A; the first end of the voltage-dividing resistor R10 is connected between the second end of the voltage-dividing resistor R11 and the non-inverting input end of the operational amplifier U7A, and the second end of the voltage-dividing resistor R10 is grounded; the first end of the voltage-dividing resistor R19 is connected between the second end of the voltage-dividing resistor R17 and the inverting input end of the operational amplifier U7A, and the second end of the voltage-dividing resistor R19 is grounded; the first end of the negative feedback amplifying resistor R20 is connected between the second end of the voltage dividing resistor R17 and the inverting input end of the operational amplifier U7A, and the second end of the negative feedback amplifying resistor R20 is connected with the output end of the operational amplifier U7A.
In one embodiment, the proportional-integral circuit comprises a resistor R15, a resistor R21, a capacitor C19 and an operational amplifier U3A;
the first end of the resistor R15 is connected with the output end of the operational amplifier U7A, and the second end of the resistor R15 is connected with the inverting input end of the operational amplifier U3A; the non-inverting input end of the operational amplifier U3A is connected with an external input gate voltage, the first end of the resistor R21 is connected between the second end of the resistor R15 and the inverting input end of the operational amplifier U3A, and the second end of the resistor R21 is connected with the first end of the capacitor C19; the second terminal of the capacitor C19 is connected to the output terminal of the operational amplifier U3A.
In one embodiment, the output clamp control circuit comprises a buffer resistor R13, an operational amplifier U8A, a voltage dividing resistor R16 and a voltage dividing resistor R18;
the first end of the buffer resistor R13 is connected with the output end of the operational amplifier U3A, and the second end is connected with the non-inverting input end of the operational amplifier U8A; the inverting input end of the operational amplifier U8A is connected with the output end of the operational amplifier U8A; a first end of the voltage dividing resistor R16 is connected to an output end of the operational amplifier U8A, and a second end of the voltage dividing resistor R16 is an output end of the output clamp control circuit; the first end of the voltage dividing resistor R18 is connected with the second end of the voltage dividing resistor R16, and the second end of the voltage dividing resistor R18 is grounded.
In one embodiment, the driver control circuit further includes an output amplitude control circuit, electrically connected to the driver, configured to obtain an output amplitude monitoring voltage of the driver, compare the output amplitude monitoring voltage with a preset target voltage, and then step-adjust a gain voltage output to the driver.
In one embodiment, the output amplitude control circuit comprises an output amplitude monitoring circuit and a processing circuit;
the output amplitude control circuit is electrically connected with the driver and is used for acquiring the output amplitude monitoring voltage of the driver;
the processing circuit is respectively electrically connected with the output amplitude monitoring circuit and the driver and is used for comparing the output amplitude monitoring voltage with a preset target voltage and outputting a gain voltage adjusting signal according to a comparison result.
In one embodiment, the output amplitude control circuit further comprises a gain voltage adjustment circuit;
the gain voltage adjusting circuit is connected with the processing circuit and used for receiving the gain voltage adjusting signal and adjusting the gain voltage of the driver.
In one embodiment, the driver control circuit further comprises a switching circuit;
the switch circuit is connected between the power supply and the constant current control circuit and used for realizing the on-off of the power supply under the control of the processing circuit.
In one embodiment, the driver includes any one of a DML driver, an EML driver, or an MZM driver.
According to the driver control circuit applied to the optical module, the current constant control circuit is arranged to collect the power supply current of the power supply to the driver, then the power supply current is subjected to voltage division, proportional-integral operation and output clamping control, and then a negative gate voltage is output to the driver, so that the current output to the driver within the full working temperature range can be effectively kept stable, the quality of a full-temperature output signal is ensured, and the conditions of signal output drifting, distortion and the like along with the temperature within the working temperature range of the driver are avoided; in addition, since the negative gate voltage is outputted to the driver, the performance and the life of the driver are not affected.
Drawings
FIG. 1 is a block diagram of a driver control circuit applied in an optical module according to an embodiment;
FIG. 2 is a block diagram of a driver control circuit applied in an optical module according to another embodiment;
FIG. 3 is a schematic circuit diagram of a driver in one embodiment;
FIG. 4 is a schematic circuit diagram of a power supply in one embodiment;
FIG. 5 is a schematic diagram of a constant current control circuit in one embodiment;
FIG. 6 is a schematic diagram of processing circuitry in one embodiment;
FIG. 7 is a schematic diagram of a gain voltage adjustment circuit in one embodiment;
FIG. 8 is a schematic diagram of a bias voltage adjustment circuit in one embodiment;
FIG. 9 is a schematic diagram of an external supply voltage in one embodiment;
fig. 10 is a schematic diagram of an external supply voltage in another embodiment.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Please refer to fig. 1, which is a block diagram of a driver control circuit applied in an optical module according to an embodiment of the present disclosure. The optical module generally includes two parts, namely a Transmitter Optical Subassembly (TOSA) and a Receiver Optical Subassembly (ROSA), wherein the internal part of the TOSA is formed by a semiconductor laser and used for transmitting a modulated optical signal; the latter is internally formed by a photodetector for receiving the modulated optical signal.
Specifically, the driver control circuit may include a driver 10, a power supply 20, and a current constant control circuit 30; the power supply 20 is configured to supply power to the driver 10, that is, provide a power supply voltage for the driver 10, and the constant current control circuit 30 is electrically connected to the power supply 20 and the driver 10, and is configured to sample a power supply current of the power supply 20 to the driver 10, convert the power supply current into a power supply voltage, divide the power supply voltage, perform a proportional-integral operation, and output a negative gate voltage to the driver 10 after clamp control.
Referring to fig. 3, a schematic circuit diagram of a driver according to the present application is shown; in fig. 3, Vin and Vout are the rf signal input and output terminals of the driver 10; VCC is the power supply terminal of the external power supply, and VDD is the power supply terminal of the power supply 20; VB is a bias voltage end, VG is a gate voltage end, VGC is a gain adjustment voltage end, and the sizes of the VB, the VG and the VGC can be adjusted; VPD is the output amplitude monitoring voltage end, and C11 and C12 are filter capacitors.
In some embodiments, the driver of the present application may include any one of a DML (direct modulation) driver, an EML (external modulation) driver, or an MZM (mach zehnder) driver. That is, the driver control circuit of the present application can be used for the control circuit of the drivers such as the DML driver, the EML driver, and the MZM driver.
Further, the power supply 20 of the present application may include a Buck-Boost power chip, which is also referred to as a Buck-Boost power supply, and the output voltage of the Buck-Boost power chip may be regulated. Fig. 4 is a schematic diagram of a circuit structure of the power supply according to an embodiment. In fig. 4, U1 is a Buck-Boost power chip, the power supply terminal selects C2 and C3 as filter capacitors, and R1 is an enabling pull-up resistor; the resistor R2 is an upper voltage-dividing resistor, the FB terminal is connected with the output terminal of the power supply 20 through the upper voltage-dividing resistor R2, the resistor R4 is a lower voltage-dividing resistor, and V isFBFor the FB pin voltage of the power chip U1, C4 and C5 are output filter capacitors, R3 is a switching frequency selection resistor, C6 is a decoupling capacitor, and C1 is an energy storage capacitor. By configuring the voltage V at DAC _ DRV _ VDD terminaldacThe resistances of the upper voltage-dividing resistor R2 and the lower voltage-dividing resistor R4 can adjust the output voltage Vo of the power supply 20, and by combining the circuit structure, the output voltage calculation formula of the power supply 20 can be Vo-VFB+(VFB-Vdac)*R2/R4。
Further, the current constant control circuit 30 of the present application may include a current sampling circuit (not shown in fig. 1), a proportional-integral circuit (not shown in fig. 1) and an output clamp control circuit (not shown in fig. 1); the current sampling circuit is electrically connected with the driver 10 and is used for sampling the supply current of the power supply 20 to the driver 10 and converting the supply current into a supply voltage for output; the proportional-integral circuit is electrically connected with the current sampling circuit and is used for carrying out proportional-integral operation on the power supply voltage; the output clamp control circuit is electrically connected to the proportional-integral circuit, and is configured to output a negative gate voltage to the driver 10 after performing output clamp control on the power supply voltage after proportional-integral operation.
Fig. 5 is a schematic diagram of a current constant control circuit according to an embodiment of the present disclosure. In fig. 5, 310 denotes a current sampling circuit, 320 denotes a proportional-integral circuit, and 330 denotes an output clamp control circuit; the current sampling circuit 310 may include a sampling resistor R14, voltage dividing resistors R10, R11, R17, R19, a negative feedback amplifying resistor R20, and an operational amplifier U7A; the operational amplifier U7A can be powered by a single positive power supply, namely VCC; a first end of the sampling resistor R14 is connected to the output terminal (DRV-VDD) of the power supply 20, a second end of the sampling resistor R14 is connected to a first end of the voltage dividing resistor R17, and a second end of the voltage dividing resistor R17 is connected to the inverting input terminal 1 of the operational amplifier U7A; a first end of the voltage dividing resistor R11 is connected with a first end of the sampling resistor R14, and a second end of the voltage dividing resistor R11 is connected with a non-inverting input end 2 of the operational amplifier U7A; the first end of the voltage-dividing resistor R10 is connected between the second end of the voltage-dividing resistor R11 and the non-inverting input end 2 of the operational amplifier U7A, and the second end of the voltage-dividing resistor R10 is grounded; the first end of the voltage-dividing resistor R19 is connected between the second end of the voltage-dividing resistor R17 and the inverting input end 1 of the operational amplifier U7A, and the second end of the voltage-dividing resistor R19 is grounded; the first end of the negative feedback amplifying resistor R20 is connected between the second end of the voltage dividing resistor R17 and the inverting input terminal 1 of the operational amplifier U7A, and the second end of the negative feedback amplifying resistor R20 is connected with the output terminal 15 of the operational amplifier U7A. Although not shown, C13 and C15 are filter capacitors, R9 is an energy feedback resistor, C20 is an anti-vibration capacitor, and L2 is a low-frequency inductor, the connection relationship of the circuit devices in this portion can be understood with reference to the drawings, and is not described herein.
The output end DRV _ VDD of the power supply 20 is filtered by the low frequency inductor L2 and then sampled by the R14 resistor, and the voltage at the two ends of the R14 resistor is divided and then used as the input stage of the operational amplifier U7A. In order to monitor the current of the driver control circuit, the voltage at the output terminal of the operational amplifier U7A needs to be reported simultaneously, that is, the output voltage of the current sampling circuit 310 needs to be reported through the ADC _ IDD terminal; according to the connection relationship of each component in the current sampling circuit 310, it can be known that electricity is sampled by the currentOutput voltage V processed by way 310out1Can be expressed as: vout1＝DRV_VDD*R10/(R10+R11)+IddR14R 20/R11, wherein IddThe current flowing into the driver 10 for the VDD terminal.
Further, as shown in fig. 5, the pid circuit 320 includes a resistor R15, a resistor R21, a capacitor C19, and an operational amplifier U3A; the first end of the resistor R15 is connected to the output end 15 of the operational amplifier U7A, and the second end of the resistor R15 is connected to the inverting input end 1 of the operational amplifier U3A; a non-inverting input terminal 2 of the operational amplifier U3A is connected to an external input gate voltage DAC-VG, a first terminal of the resistor R21 is connected between a second terminal of the resistor R15 and an inverting input terminal 1 of the operational amplifier U3A, and a second terminal of the resistor R21 is connected to a first terminal of the capacitor C19; the second terminal of the capacitor C19 is connected to the output terminal 15 of the operational amplifier U3A. Referring to fig. 5, although not shown, C14 and C17 are filter capacitors, and the resistor R12 may serve as a voltage buffer. The connection relationship of the circuit devices in this part can be understood with reference to the drawings, and is not described in detail herein.
Specifically, the operational amplifier U3A in this embodiment may be powered by dual power supplies, namely, an external power supply VCC and an external power supply VEE; the power supply voltage of the external power supply VCC can be nominally 3.3V, and the power supply voltage of the external power supply VEE can be nominally-5.2V; by this arrangement, it is ensured that the output voltage processed by the proportional-integral circuit 320 is kept in phase with the external input gate voltage DAC-VG.
Further, with continued reference to fig. 5, the output clamp control circuit 330 may include a buffer resistor R13, an operational amplifier U8A, a voltage dividing resistor R16 and a voltage dividing resistor R18; the operational amplifier U8A is powered by a single negative power supply, namely, nominal-5.2V voltage is provided through a VEE terminal; the first end of the buffer resistor R13 is connected with the output end 15 of the operational amplifier U3A, and the second end is connected with the non-inverting input end 2 of the operational amplifier U8A; the inverting input terminal 1 of the operational amplifier U8A is connected with the output terminal 15 of the operational amplifier U8A; a first end of the voltage dividing resistor R16 is connected to the output end 15 of the operational amplifier U8A, and a second end of the voltage dividing resistor R16 is an output end of the output clamp control circuit; the first end of the voltage dividing resistor R18 is connected with the second end of the voltage dividing resistor R16, and the second end of the voltage dividing resistor R18 is grounded. Although not shown, C16 and C18 are filter capacitors, and the connection relationship of circuit devices in these parts can be understood with reference to the drawings, which are not described herein. The output clamping control circuit adopts two-stage voltage clamping, wherein the two-stage voltage clamping comprises a single power supply clamping negative voltage and outputs a partial voltage clamping maximum negative voltage; it can be seen that, by adjusting the external power supply voltage VEE and the voltage division ratio of the voltage division resistors R16 and R18, clamping of various output voltage ranges can be achieved, in this embodiment, the voltage division ratio of the two resistors R16 and R18 can be 1:1, so that the range of the output gate voltage VG can be achieved to be-2.6V-0V.
In an embodiment, please refer to fig. 2, the driver control circuit of the present application may further include an output amplitude control circuit (not shown in fig. 2), electrically connected to the driver 10, for obtaining an output amplitude monitoring voltage of the driver 10, comparing the output amplitude monitoring voltage with a preset target voltage, and then adjusting the gain voltage output to the driver 10 in a step-by-step manner.
Further, with continued reference to fig. 2, the output amplitude control circuit of the present application may include an output amplitude monitoring circuit 410 and a processing circuit 420; the output amplitude control circuit 410 is electrically connected to the driver 10, and is configured to obtain an output amplitude monitoring voltage ADC-VPD of the driver; the processing circuit 420 is electrically connected to the output amplitude monitoring circuit 410 and the driver 10, and configured to compare the output amplitude monitoring voltage ADC-VPD with a preset target voltage, and output a gain voltage adjusting signal DAC-VGC according to a comparison result. Further, in order to realize the adjustment of the gain voltage, the output amplitude control circuit of the present application may further include a gain voltage adjusting circuit (not shown), which is connected to the processing circuit 420, and is configured to receive the gain voltage adjusting signal DAC-VGC and adjust the gain voltage of the driver 10. The gain voltage adjusting circuit may include a digital-to-analog converter or an emitter follower amplifier, and in this embodiment, the gain voltage adjusting circuit includes an emitter follower amplifier as an example, and refer to fig. 7, the gain voltage adjusting circuit mainly includes an operational amplifier U3B and a resistor R7, the gain voltage adjusting signal DAC-VGC output by the processing circuit 420 is input to the non-inverting input terminal 4 of the operational amplifier U3B, the inverting input terminal 5 of the operational amplifier U3B is connected to the output terminal 6 of the operational amplifier U3B through the resistor R7, and the input gain voltage adjusting signal DAC-VGC is processed by the operational amplifier U3B and then outputs a gain voltage signal to the gain voltage terminal VGC of the driver 10.
Specifically, the processing circuit 420 may adjust the gain voltage subsequently output to the driver 10 by a step increase of 5mV or a step decrease of 5mV based on the original gain voltage adjustment signal according to the comparison result. That is, when the output amplitude monitoring voltage ADC-VPD is greater than or equal to the Target voltage Target-VPD, the gain voltage subsequently output to the driver 10 may be adjusted by reducing the output amplitude monitoring voltage ADC-VPD by 5mV in steps based on the original gain voltage adjustment signal; when the output amplitude monitor voltage ADC-VPD is less than the Target voltage Target-VPD, the gain voltage subsequently output to the driver 10 may be adjusted by increasing 5mV step by step based on the original gain voltage adjustment signal. It is understood that the stepping can be fine-tuned according to the actual device in the actual application.
Further, fig. 6 may be added to provide a schematic structural diagram of the processing circuit 420 in an embodiment of the disclosure. In fig. 6, U9A may be a microprocessor, or central control unit; the ADC _ VPD and the ADC _ IDD are two analog input signals for monitoring the output amplitude and the output stage supply current of the driver 10; DAC _ VG, DAC _ VB (see FIG. 8 for an aid), DAC _ VGC, and DAC _ DRV _ VDD are four-way digital output signals for adjusting the corresponding gate voltage VG, bias voltage VB, gain voltage VGC, and output stage drive voltage VDD on driver 10; VDD _ EN, VCC _ EN, and VEE _ EN are three-way enable terminals, and the on/off of the supply voltage VDD, the external supply voltage VCC, and the external supply voltage VEE can be controlled by the microprocessor MCU outputting high and low level signals (see fig. 9 and fig. 10 for assistance), so that the control of the power-on timing sequence can be realized. It is understood that the voltage at the DAC _ VGC terminal of the aforementioned proportional-integral circuit 320 can also be configured by the processing circuit 420. R22, R23, C21 and C22 form a low-pass filter circuit, and C23 and C24 are power filter capacitors.
In an embodiment, considering the requirement of power-on timing sequence for power-on of the driver 10, a power-on timing sequence error may cause a device life to be reduced, or even damaged, so it is also important to ensure the power-on timing sequence of multiple voltages, in this application, the power-on timing sequence of multiple voltages (DAC _ VG, DAC _ VB, DAC _ VGC, and DAC _ DRV _ VDD) output by the processing circuit 420 may be implemented by an algorithm inside the microprocessor MCU; in addition, with reference to fig. 2, the driver control circuit of the present application is further provided with a switch circuit 50, where the switch circuit 50 is connected between the power supply 20 and the constant current control circuit 30, and is used for switching on and off the power supply 20 under the control of the processing circuit 420, and the switch circuit 50 may include a field effect transistor chip. Specifically, referring to fig. 4 together, in fig. 4, U2 is a switch chip adopted by the switch circuit 50 of the present application, and the microprocessor MCU implements the power supply of the power supply 20 to the driver 10 by configuring the pin level of VDD _ EN.
In summary, the driver control circuit of the present application, on one hand, realizes the current constant control of the driver by a pure hardware circuit, such as a current constant control circuit, and on the other hand, samples and monitors the output amplitude voltage in real time by an output amplitude monitoring circuit in the output amplitude control circuit, and then adjusts the gain voltage output to the driver according to the real-time output amplitude monitoring voltage by a processing circuit, so as to effectively ensure that the current and the output amplitude are stable within the full working temperature range, and work in a linear working area. In addition, the problems of service life reduction and even damage of the device can be effectively avoided by controlling the power-on time sequence of the driver through the processing circuit.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A driver control circuit applied to an optical module is characterized by comprising a driver, a power supply and a current constant control circuit;
the power supply is used for supplying power to the driver; wherein the output voltage of the power supply is adjustable;
the current constant control circuit is respectively electrically connected with the power supply and the driver and is used for sampling the power supply current of the power supply to the driver, converting the power supply current into power supply voltage, and outputting negative gate voltage to the driver after voltage division, proportional-integral operation and output clamping control are carried out on the power supply voltage so as to ensure that the output current of the driver is constant;
the current constant control circuit comprises a current sampling circuit, a proportional-integral circuit and an output clamping control circuit;
the current sampling circuit is electrically connected with the driver and used for sampling the power supply current of the power supply to the driver and converting the power supply current into power supply voltage for output;
the proportional-integral circuit is electrically connected with the current sampling circuit and is used for carrying out proportional-integral operation on the power supply voltage;
and the output clamping control circuit is electrically connected with the proportional integral circuit and is used for outputting negative gate voltage to the driver after carrying out output clamping control on the power supply voltage subjected to proportional integral operation.
2. The driver control circuit applied to the optical module as claimed in claim 1, wherein the power supply comprises a Buck-Boost power chip.
3. The driver control circuit applied to the optical module as claimed in claim 1, wherein the current sampling circuit comprises a sampling resistor R14, a voltage dividing resistor R10, R11, R17, R19, a negative feedback amplifying resistor R20, an operational amplifier U7A;
a first end of the sampling resistor R14 is connected with an output end of the power supply, a second end of the sampling resistor R14 is connected with a first end of the voltage division resistor R17, and a second end of the voltage division resistor R17 is connected with an inverting input end of the operational amplifier U7A; a first end of the voltage dividing resistor R11 is connected with a first end of the sampling resistor R14, and a second end of the voltage dividing resistor R11 is connected with a non-inverting input end of the operational amplifier U7A; the first end of the voltage-dividing resistor R10 is connected between the second end of the voltage-dividing resistor R11 and the non-inverting input end of the operational amplifier U7A, and the second end of the voltage-dividing resistor R10 is grounded; the first end of the voltage-dividing resistor R19 is connected between the second end of the voltage-dividing resistor R17 and the inverting input end of the operational amplifier U7A, and the second end of the voltage-dividing resistor R19 is grounded; the first end of the negative feedback amplifying resistor R20 is connected between the second end of the voltage dividing resistor R17 and the inverting input end of the operational amplifier U7A, and the second end of the negative feedback amplifying resistor R20 is connected with the output end of the operational amplifier U7A.
4. The driver control circuit applied to the light module as claimed in claim 3, wherein the proportional-integral circuit comprises a resistor R15, a resistor R21, a capacitor C19 and an operational amplifier U3A;
the first end of the resistor R15 is connected with the output end of the operational amplifier U7A, and the second end of the resistor R15 is connected with the inverting input end of the operational amplifier U3A; the non-inverting input end of the operational amplifier U3A is connected with an external input gate voltage, the first end of the resistor R21 is connected between the second end of the resistor R15 and the inverting input end of the operational amplifier U3A, and the second end of the resistor R21 is connected with the first end of the capacitor C19; the second terminal of the capacitor C19 is connected to the output terminal of the operational amplifier U3A.
5. The driver control circuit applied to the light module as claimed in claim 4, wherein the output clamp control circuit comprises a buffer resistor R13, an operational amplifier U8A, a voltage dividing resistor R16 and a voltage dividing resistor R18;
the first end of the buffer resistor R13 is connected with the output end of the operational amplifier U3A, and the second end is connected with the non-inverting input end of the operational amplifier U8A; the inverting input end of the operational amplifier U8A is connected with the output end of the operational amplifier U8A; a first end of the voltage dividing resistor R16 is connected to an output end of the operational amplifier U8A, and a second end of the voltage dividing resistor R16 is an output end of the output clamp control circuit; the first end of the voltage dividing resistor R18 is connected with the second end of the voltage dividing resistor R16, and the second end of the voltage dividing resistor R18 is grounded.
6. The driver control circuit applied to the optical module as claimed in any one of claims 1 to 5, further comprising an output amplitude control circuit electrically connected to the driver, configured to obtain an output amplitude monitoring voltage of the driver, compare the output amplitude monitoring voltage with a preset target voltage, and then step-adjust a gain voltage output to the driver.
7. The driver control circuit applied to the light module as claimed in claim 6, wherein the output amplitude control circuit comprises an output amplitude monitoring circuit and a processing circuit;
the output amplitude control circuit is electrically connected with the driver and is used for acquiring the output amplitude monitoring voltage of the driver;
the processing circuit is respectively electrically connected with the output amplitude monitoring circuit and the driver and is used for comparing the output amplitude monitoring voltage with a preset target voltage and outputting a gain voltage adjusting signal according to a comparison result.
8. The driver control circuit applied to the optical module as claimed in claim 7, wherein the output amplitude control circuit further comprises a gain voltage adjusting circuit;
the gain voltage adjusting circuit is connected with the processing circuit and used for receiving the gain voltage adjusting signal and adjusting the gain voltage of the driver.
9. The driver control circuit applied to the light module as claimed in claim 7, further comprising a switch circuit;
the switch circuit is connected between the power supply and the constant current control circuit and used for realizing the on-off of the power supply under the control of the processing circuit.
10. The driver control circuit applied to the light module as claimed in claim 6, wherein the driver comprises any one of a DML driver, an EML driver or an MZM driver.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111600197B (en) * | 2020-05-22 | 2023-03-31 | 索尔思光电（成都）有限公司 | Light-emitting power monitoring and APC control circuit and method based on EA photocurrent |
| CN115016076B (en) * | 2021-03-04 | 2023-08-08 | 青岛海信宽带多媒体技术有限公司 | Optical module and optical module shell temperature calculation method |
| CN113447750B (en) * | 2021-08-31 | 2022-03-08 | 深圳市力子光电科技有限公司 | Optical device test circuit |
| CN114745054B (en) * | 2022-03-23 | 2024-01-12 | 武汉光迅科技股份有限公司 | Optical module equipment and voltage adjustment method |
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