CN110988505A - Phase-loss detection circuit and method for compressor and compressor - Google Patents
Phase-loss detection circuit and method for compressor and compressor Download PDFInfo
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Abstract
The invention provides a phase-lack detection circuit and a phase-lack detection method of a compressor and the compressor, wherein the phase-lack detection circuit of the compressor comprises: an inverter module: two ends of the inverter module are respectively connected with the bus and the motor and used for converting direct current into three-phase alternating current to supply power to the motor; the signal acquisition circuit: the inverter module is connected to obtain the current value of the three-phase alternating current and convert the current value into a voltage signal to be output; a logic operation circuit: and the signal acquisition circuit is connected, and specific phase-lacking line information is output to the control chip according to the logic level signal. The invention can detect the three-phase line open-phase fault of the compressor before starting; and can accurately detect the specific phase-lacking line; and a fault signal can be sent out when a phase-lack fault occurs, and the control chip can send out a phase-lack alarm and cut off the output of the inverter after receiving the fault signal.
Description
Technical Field
The invention relates to the technical field of compressors, in particular to a phase-lack detection circuit and method for a compressor and the compressor.
Background
The compressor three-phase current open-phase detection circuit is an important component of a compressor control system, and the three-phase current is acquired by connecting resistors in series on a bridge arm of a three-phase bridge inverter, so that the protection and control of the compressor are realized.
Due to the fact that a power grid is connected or a three-phase input electric wire is not connected reliably, the vehicle-mounted charger can work in a phase-lack state, and phase-lack operation cannot be found in time easily. When the charger works in a phase-loss state, no current flows through one arm of the inverter bridge, and the other arms bear larger current to ensure that the output power of the charger is unchanged, so that overcurrent damage to other bridge arms can be caused in serious cases.
Therefore, the phase loss detection needs to be carried out on the three-phase line of the compressor before the compressor is started, and if the compressor is started under the condition of phase loss, great threat is caused to equipment and personal safety.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, provides a phase-lack detection circuit and a phase-lack detection method of a compressor and the compressor, and avoids potential safety hazards to personal safety and equipment caused by phase-lack of three-phase electricity of the compressor.
The purpose of the invention is realized by the following technical scheme:
in a first aspect, the present invention provides a phase loss detection circuit for a compressor, including:
an inverter module: two ends of the inverter module are respectively connected with the bus and the motor and used for converting direct current into three-phase alternating current to supply power to the motor;
the signal acquisition circuit: the inverter module is connected to obtain the current value of the three-phase alternating current and convert the current value into a logic level signal to be output;
a logic operation circuit: and the signal acquisition circuit is connected, and specific phase-lacking line information is output to the control chip according to the logic level signal.
Further, the signal acquisition circuit includes a resistor R1, a resistor R2 and a resistor R3, the resistor R1 is connected to the U-phase loop of the inverter and is configured to obtain a U-phase current value, the resistor R2 is connected to the V-phase loop of the inverter and is configured to obtain a V-phase current value, and the resistor R3 is connected to the W-phase loop of the inverter and is configured to obtain a W-phase current value.
Further, the signal acquisition circuit further includes a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, an operational amplifier a1, an operational amplifier a2, an operational amplifier A3, a comparator A4, a comparator A5, and a power supply VCC, one end of the resistor R2 and one end of the resistor R3 are both connected to a negative electrode of a bus, the other end of the resistor R2 is connected to a non-inverting input terminal of the operational amplifier a1 through the resistor R4, the other end of the resistor R3 is connected to a non-inverting input terminal of the operational amplifier a2 through the resistor R5, an inverting input terminal of the operational amplifier a1 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to an output terminal of the operational amplifier a 6 and a common terminal is connected to a non-inverting input terminal of the comparator a 6, an inverting input terminal of the operational amplifier a 6 is connected to one end of the resistor, the other end of the resistor R7 is connected to the output end of the operational amplifier a2, the common end of the resistor R7 is connected to the non-inverting input end of the comparator a5, the inverting input end of the comparator a4 is connected to the output end of the operational amplifier A3, the common end of the comparator a4 is connected to the inverting input end of the operational amplifier A3 and the inverting input end of the comparator a5, the output end of the comparator a4 outputs a logic level signal UR2, the output end of the comparator a5 outputs a logic level signal UR3, the non-inverting input end of the operational amplifier A3 is connected to one end of the resistor R8, the common end of the resistor R9, the other end of the resistor R8 is connected to the power source VCC, and the other end of the resistor R9 is grounded.
Furthermore, the logic operation circuit comprises a first NOT gate, a second NOT gate, a first AND gate, a second AND gate, a third AND gate and a fourth AND gate, the input end of the first NOT gate is connected with the first output end of the signal acquisition circuit, the common end of the first NOT gate is connected with the first input end of the third AND gate and the first input end of the fourth AND gate, the output end of the first NOT gate is connected with the first input end of the first AND gate, the common end of the first NOT gate is connected with the first input end of the second AND gate, the input end of the second NOT gate is connected with the second output end of the signal acquisition circuit, the common end of the second NOT gate is connected with the second input end of the second AND gate and the second input end of the fourth AND gate, the output end of the second NOT gate is connected with the second input end of the first AND gate, the common end of the second NOT gate is connected with the second input end of the third AND gate, the first AND gate, the second AND gate, the third AND gate and the fourth AND gate are respectively connected with the I/O port of the control chip.
Further, the first not gate and the second not gate are both not gates with one input end and one output end, and the first and gate, the second and gate, the third and gate and the fourth and gate are both AND gates with two input ends and one output end.
In a second aspect, the present invention further provides a phase loss detection method for a compressor, which is applied to the phase loss detection circuit for a compressor according to the first aspect.
Further, the method for detecting the phase loss of the compressor comprises the following steps:
acquiring three-phase alternating current information of a motor of the compressor through the signal acquisition circuit;
and the logic operation circuit outputs specific open-phase line information to the control chip according to the three-phase alternating current information of the motor.
Further, the step of acquiring the three-phase alternating current information of the motor of the compressor through the signal acquisition circuit specifically includes:
acquiring the current values of any two phases of three-phase alternating current of the motor;
the obtained two-phase current values are converted into a logic level signal UR2 and a logic level signal UR3 respectively and output.
Further, the logic operation circuit outputs specific phase-lacking line information to the control chip according to the three-phase alternating current information of the motor specifically comprises:
the logic operation circuit performs logic operation after the logic level signal UR2 and the logic level signal UR 3;
and outputting the information of the phase-lacking line to the control chip according to the result of the logic operation.
In a third aspect, the present invention further provides a compressor, which includes the phase failure detection circuit of the compressor according to the first aspect.
The invention provides a phase-lack detection circuit and method of a compressor and the compressor, which at least have the following beneficial effects:
1. the three-phase line open-phase fault of the compressor can be detected before starting;
2. the specific phase-lack line can be accurately detected;
3. the control chip can send out a fault signal when a phase-missing fault occurs, and send out a phase-missing alarm and cut off the output of the inverter after receiving the fault signal.
Drawings
The invention is further illustrated by means of the attached drawings, but the embodiments in the drawings do not constitute any limitation to the invention, and for a person skilled in the art, other drawings can be derived on the basis of the following drawings without inventive effort.
Fig. 1 is a circuit configuration topology diagram of a phase loss detection circuit of a compressor according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of a signal acquisition circuit of a phase loss detection circuit of a compressor according to an embodiment of the present invention.
Fig. 3 is a circuit operation diagram of an inverter module of a phase loss detection circuit of a compressor according to an embodiment of the present invention, when no phase is lost.
Fig. 4 is a circuit operation diagram of the inverter module U-phase loss of the phase loss detection circuit of the compressor according to the embodiment of the present invention.
Fig. 5 is a circuit operation diagram of the inverter module V-phase loss of the phase loss detection circuit of the compressor according to the embodiment of the present invention.
Fig. 6 is a circuit operation diagram of the inverter module W-phase loss of the phase loss detection circuit of the compressor according to the embodiment of the present invention.
Fig. 7 is a schematic circuit diagram of a logical operation circuit of the open-phase detection circuit of the compressor according to the embodiment of the present invention.
Fig. 8 is a schematic flowchart of a phase loss detection method of a compressor according to another embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In a digital circuit, the high and low of a voltage are represented by logic levels, which include both high and low levels. The digital circuits formed by different components have different logic levels corresponding to voltages. The logic level is defined by a threshold level, e.g., in a TTL gate circuit, a voltage greater than 3.5 volts (threshold high level) is defined as a logic high level, represented by the number 1; a voltage less than 0.3 volts (threshold low level) is defined as a logic low level, represented by the number 0.
Embodiment 1, a phase loss detection circuit for a compressor.
As shown in fig. 1, the phase failure detection circuit of a compressor of the present embodiment includes:
an inverter module: two ends of the inverter module are respectively connected with the bus and the motor and used for converting direct current into three-phase alternating current to supply power to the motor;
the signal acquisition circuit: the inverter module is connected to obtain the current value of the three-phase alternating current and convert the current value into a logic level signal to be output;
a logic operation circuit: and the signal acquisition circuit is connected, and specific phase-lacking line information is output to the control chip according to the logic level signal.
The inverter module comprises six switching tubes Q1-Q6 and six diodes, the signal acquisition circuit comprises resistors R1-R3, and the three resistors R1-R3 of the signal acquisition circuit are connected into the inverter module, wherein the switching tubes can be triodes, MOS tubes or IGBTs, and the switching tubes in the embodiment take the MOS tubes as an example for explanation. The input ends of six MOS tubes are respectively connected with the cathodes of six diodes, the output ends of the six MOS tubes are respectively connected with the anodes of the six diodes, the grids of the six MOS tubes are respectively connected with six general I/O ports of a control chip, the six diodes are respectively parasitic diodes of the six MOS tubes, the collectors of the MOS tubes Q1, Q3 and Q5 are also connected with the anode of a bus, the emitter of the MOS tube Q1 is also connected with the collector of the MOS tube Q4, the common end of the emitter of the MOS tube Q1 is connected with the U-phase input end of a motor, the emitter of the MOS tube Q3 is also connected with the collector of the MOS tube Q6, the common end of the emitter of the MOS tube Q5 is connected with the collector of the MOS tube Q2, the common end of the emitter of the MOS tube Q4 is also connected with one end of a resistor R1, the emitter of the MOS tube Q6 is also connected with one end of a resistor R2, the emitter of the MOS tube Q2 is also connected, the other end of the resistor R1, the other end of the resistor R2 and the other end of the resistor R3 are connected with the negative electrode of the bus, the resistor R1 is used for obtaining a U-phase current value, the resistor R2 is used for obtaining a V-phase current value, and the resistor R3 is used for obtaining a W-phase current value.
The control chip may be any control chip having a logic operation function and an I/O port, such as an MCU, an ARM, and a DSP, and the control chip of this embodiment is described by taking the MCU as an example.
As shown in fig. 2, the signal acquisition circuit further includes a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, an operational amplifier a1, an operational amplifier a2, an operational amplifier A3, a comparator a4, a comparator a5 and a power supply VCC, one end of the resistor R2 and one end of the resistor R3 are both connected to a negative electrode of the bus, the other end of the resistor R3 is connected to a non-inverting input terminal of the operational amplifier A3 through the resistor R3, the inverting input terminal of the operational amplifier A3 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to an output terminal of the operational amplifier A3 and the common terminal is connected to a non-inverting input terminal of the comparator A3, the inverting input terminal of the comparator A4 is connected with the output terminal of the operational amplifier A3, the common terminal is connected with the inverting input terminal of the operational amplifier A3 and the inverting input terminal of the comparator A5, the output terminal of the comparator A4 outputs a logic level signal UR2, the output terminal of the comparator A5 outputs a logic level signal UR3, the non-inverting input terminal of the operational amplifier A3 is connected with one end of a resistor R8, the common terminal is connected with one end of a resistor R9, the other end of the resistor R8 is connected with a power supply VCC, and the other end of the resistor R9 is grounded.
After the U-phase current, the V-phase current and the W-phase current are respectively acquired by the resistors R1-R3, the U-phase current, the V-phase current and the W-phase current are converted into voltage signals U1-U3, the operational amplifier A1, the resistor R4 and the resistor R6 form a group of voltage followers, and the voltage followers are used for a voltage sampling circuit to acquire the voltage signal U2 on the resistor R2 and enable the voltage signal U2 to be input to the non-inverting input end of the comparator A4; the operational amplifier A2, the resistor R5 and the resistor R7 form another group of voltage followers for collecting a voltage signal U3 on the resistor R3, and the voltage signal U3 is input to the non-inverting input end of the comparator A5. The voltage divider circuit is configured by the resistor R8 and the resistor R9, and the voltage UREF = VCC R9/(R9 + R8) inputted to the non-inverting input terminal of the operational amplifier A3 and the operational amplifier A3 is configured as a voltage follower, so that the operational amplifier A3, the resistors R8, and the resistors R9 generate the reference voltage UREF for voltage comparison. The comparator a4 is used for comparing the sampled voltage U2 with the reference voltage UREF to generate a logic level signal UR2, wherein the logic level signal UR2 is high when the voltage U2 is greater than the reference voltage UREF, and the logic level signal UR2 is low when the voltage U2 is less than the reference voltage UREF; the comparator a5 is used to compare the sampled voltage U3 with the reference voltage UREF to generate a logic level signal UR 3.
As shown in fig. 7, the logic operation circuit includes a first not gate, a second not gate, a first and gate, a second and gate, a third and gate and a fourth and gate, an input terminal of the first not gate is connected to an output terminal of the comparator a4 and a common terminal thereof is connected to a first input terminal of the third and gate and a first input terminal of the fourth and gate, an output terminal of the first not gate is connected to a first input terminal of the first and gate and a common terminal thereof is connected to a first input terminal of the second and gate, an input terminal of the second not gate is connected to an output terminal of the comparator a5 and a common terminal thereof is connected to a second input terminal of the second and gate and a second input terminal of the fourth and gate, an output terminal of the second not gate is connected to a second input terminal of the first and gate and a common terminal thereof is connected to a second input terminal of the third and gate, and gates and the first and gate, the second and gate, the third.
The first not gate and the second not gate in the embodiment are not gates, and the first and gate, the second and gate, the third and gate and the fourth and gate are all and gates, in order to simplify the circuit and save the cost, the first and gate, the second and gate, the third and gate and the fourth and gate are all and gates. Specifically, the not gate in this embodiment is a not gate with one input terminal and one output terminal, and the and gate is an and gate with two input terminals and one output terminal.
When the logic level signal UR2 and the logic level signal UR3 are inputted to the logic operation circuit, the logic operation satisfies the following conditions as shown in the logic operation table 1:
| UR2 | UR3 | O1 | O2 | O3 | O4 | phase-lack line |
| 1 | 1 | 0 | 0 | 0 | 1 | Without phase loss |
| 1 | 0 | 0 | 0 | 1 | 0 | W phase loss |
| 0 | 1 | 0 | 1 | 0 | 0 | Phase loss of V |
| 0 | 0 | 1 | 0 | 0 | 0 | U phase loss |
Table 1 logical operation table.
The specific implementation manner of this embodiment: when the compressor is used, whether three-phase alternating current provided by the inverter is in phase failure is detected firstly, and after a detection program is started, the MCU sends out a detection pulse PLUSE to drive the MOS tube Q1, the MOS tube Q6 and the MOS tube Q2 of the inverter to be conducted. The open-phase detection circuit acquires a voltage signal U2 on a resistor R2 and a voltage signal U3 on a resistor R3 before the compressor is started, after the operation of a comparator A4 and a comparator A5, the voltage signal U2 can be converted into a logic level signal UR2, the voltage signal U3 can be converted into a logic level signal UR3, the logic level signal UR2 and the logic level signal UR3 enter a logic operation circuit for calculation to obtain a signal for specifically reflecting an open-phase line, and the MCU can determine a specific open-phase line through the signal, send out a corresponding open-phase line alarm and cut off the power supply of the inverter.
The phase loss detection circuit before starting the compressor can be divided into the following four working conditions:
(1) as shown in fig. 3, a dotted arrow indicates a current flow direction, when the phase-loss fault does not occur in the compressor, the phase-loss detection operation starts before the compressor is started, the MCU sends a phase-loss detection pulse cause, which drives the MOS transistor Q1, the MOS transistor Q6, and the MOS transistor Q2 of the inverter to conduct, and since the phase-loss fault does not occur in the compressor, at this time, the U, V, W has complete three phases, voltages are generated on the resistor R2 and the resistor R3, the signal acquisition circuit acquires the voltage U2 and the voltage U3, and the logic level signal UR2 and the logic level signal UR3 are both high level when the voltage U2 and the voltage U3 are compared with the reference voltage UREF. After the logic level signal UR2 and the logic level signal UR3 with high level are sent to the logic operation circuit, O1, O2 and O3 of the logic operation circuit all output low level, O4 of the logic operation circuit outputs high level, after the MCU is compared with the logic operation table 1, the fact that the compressor has no open-phase fault at the moment is judged, U, V, W three phases are complete, and the MCU controls the motor of the compressor to be started normally.
(2) As shown in fig. 4, a dotted arrow indicates a current flow direction, when a U-phase open-phase fault occurs in the compressor, open-phase detection starts before starting, the MCU sends out an open-phase detection pulse, which drives the MOS transistors Q1, Q6, and Q2 of the inverter to be turned on, and at this time, since the U-phase open-phase fault occurs in the compressor, V, W three phases are complete, and the U-phase is lost. No voltage is generated on the resistor R2 and the resistor R3, the voltage U2 and the voltage U3 cannot be collected by the signal collecting circuit, and the logic level signal UR2 and the logic level signal UR3 are both low level when the voltage U2 and the voltage U3 are compared with the reference voltage UREF. After the logic level signal UR2 and the logic level signal UR3 of low level are sent into the logic operation circuit, O2, O3 and O4 of the logic operation circuit all output low level, O1 of the logic operation circuit outputs high level, after the MCU is compared with the logic operation table 1, the MCU judges that the U-phase open-phase fault occurs to the compressor at the moment, the V-phase and the W-phase are complete, the MCU sends out the U-phase open-phase alarm, cuts off the power supply of the inverter and prohibits the motor of the compressor from starting.
(3) As shown in fig. 5, the dashed arrow indicates the current flow direction, when the compressor has a V-phase open-phase fault, the open-phase detection operation starts before the compressor is turned on, the MCU sends out a open-phase detection pulse, which drives the MOS transistors Q1, Q6, and Q2 of the inverter to be turned on, and at this time, since the compressor has a V-phase open-phase fault, U, W has complete three phases, and the V-phase is lost. No voltage is generated on the resistor R2, a voltage is generated on the resistor R3, the voltage U3 is collected by the signal collection circuit, and the comparison between the voltage U2 and the voltage U3 and the reference voltage UREF makes the logic level signal UR2 be at a low level and the logic level signal UR3 be at a high level. After the logic level signal UR2 with low level and the logic level signal UR3 with high level are sent into the logic operation circuit, O1, O3 and O4 of the logic operation circuit all output low level, O2 of the logic operation circuit outputs high level, after the MCU is compared with the logic operation table 1, the MCU judges that the compressor has V-phase default phase fault at the moment, the U-phase and the W-phase are complete, the MCU sends out a V-phase default alarm, and cuts off the power supply of the inverter to prohibit the starting of the motor of the compressor.
(4) As shown in fig. 6, the dashed arrows indicate the current flow, when a W-phase open-phase fault occurs in the compressor, the open-phase detection operation starts before the compressor is turned on, the MCU sends out a open-phase detection pulse, which drives the MOS transistors Q1, Q6, and Q2 of the inverter to be turned on, and at this time, since the compressor has a W-phase open-phase fault, U, V has all three phases, and the W-phase is lost. The resistor R2 has voltage generation, the resistor R3 has no voltage generation, the signal acquisition circuit acquires the voltage U2, and the comparison between the voltage U2 and the voltage U3 and the reference voltage UREF enables the logic level signal UR3 to be at a low level and the logic level signal UR2 to be at a high level. After the logic level signal UR3 with low level and the logic level signal UR2 with high level are sent into the logic operation circuit, O1, O2 and O4 of the logic operation circuit all output low level, O3 of the logic operation circuit outputs high level, after the MCU is compared with the logic operation table 1, the MCU judges that the compressor has W-phase default phase fault at the moment, the V phase and the W phase are complete, the MCU sends out W-phase default alarm, and cuts off the power supply of the inverter to prohibit the starting of the motor of the compressor.
The phase-missing detection circuit of the compressor can detect a specific missing phase line of the compressor when the compressor is missing one of three-phase currents due to faults, sends a fault signal to the MCU to enable the MCU to send a phase-missing alarm and simultaneously cut off a power supply of the inverter, protects personal and equipment safety, does not need to detect faults through a chip by adopting an algorithm, can save chip resources and greatly improve fault troubleshooting rate and maintenance rate.
Embodiment 2, a method for detecting a phase failure in a compressor.
As shown in fig. 8, the present embodiment provides a phase loss detection method for a compressor, which is applied to the phase loss detection circuit of the compressor described in embodiment 1.
The phase failure detection method of the compressor comprises the following steps:
step 1: before the compressor motor is started, the circuit phase loss detection is carried out;
and transmitting a phase-loss detection pulse PLUSE to the MOS tube through the MCU to enable the MOS tube Q1, the MOS tube Q6 and the MOS tube Q2 to be conducted.
Step 2: acquiring three-phase alternating current information of a motor of the compressor through a signal acquisition circuit;
acquiring the current values of any two phases of three-phase alternating current of the motor;
the obtained two-phase current values are converted into a logic level signal UR2 and a logic level signal UR3 respectively after comparison operation and output.
And step 3: the logic operation circuit outputs specific open-phase line information to the control chip according to the three-phase alternating current information of the motor;
the logic operation circuit performs logic operation after the logic level signal UR2 and the logic level signal UR 3;
and outputting the information of the open-phase circuit to the MCU according to the result of the logic operation.
And 4, step 4: and starting a compressor motor according to the information of the phase-lacking line or sending a phase-lacking alarm and cutting off the power supply of the inverter.
When the MCU judges that the three-phase alternating current is out of phase, the MCU sends out an out-of-phase alarm and cuts off the power supply of the inverter;
when the MCU judges that the three-phase alternating current is normal, the MCU controls the compressor to be normally started.
The present embodiment provides a phase loss detection method for a compressor, which can detect whether three phase lines of the compressor are lost or not before starting the compressor when the compressor is lost due to a fault. And when the phase is lost, a fault signal is sent to the MCU, so that the MCU can send a phase loss alarm and cut off a power supply of the inverter to protect the safety of people and equipment.
The present embodiment provides a compressor including the phase loss detection circuit of the compressor according to embodiment 1.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the protection scope of the present invention, although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.
Claims (10)
1. A phase loss detection circuit for a compressor, comprising:
an inverter module: two ends of the inverter module are respectively connected with the bus and the motor and used for converting direct current into three-phase alternating current to supply power to the motor;
the signal acquisition circuit: the inverter module is connected to obtain the current value of the three-phase alternating current and convert the current value into a voltage signal to be output;
a logic operation circuit: and the signal acquisition circuit is connected, and specific phase-lacking line information is output to the control chip according to the voltage signal.
2. The phase loss detection circuit of a compressor as claimed in claim 1, wherein said signal acquisition circuit comprises a resistor R1, a resistor R2 and a resistor R3, said resistor R1 is connected to the U-phase loop of said inverter for obtaining the U-phase current value, said resistor R2 is connected to the V-phase loop of said inverter for obtaining the V-phase current value, and said resistor R3 is connected to the W-phase loop of said inverter for obtaining the W-phase current value.
3. The open-phase detection circuit of a compressor as claimed in claim 2, wherein said signal acquisition circuit further comprises a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, an operational amplifier a1, an operational amplifier a2, an operational amplifier A3, a comparator a4, a comparator A5 and a power source VCC, one end of said resistor R2 and one end of said resistor R3 are both connected to the negative pole of a bus, the other end of said resistor R2 is connected to the non-inverting input terminal of said operational amplifier a1 through said resistor R4, the other end of said resistor R3 is connected to the non-inverting input terminal of said operational amplifier a2 through said resistor R5, the inverting input terminal of said operational amplifier a1 is connected to one end of said resistor R6, the other end of said resistor R6 is connected to the output terminal of said operational amplifier a1 and the common terminal is connected to the non-inverting input terminal of said comparator a4, the inverting input end of the operational amplifier a2 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to the output end of the operational amplifier a2, and the common end of the resistor R7 is connected to the non-inverting input end of the comparator a5, the inverting input end of the comparator a4 is connected to the output end of the operational amplifier A3, and the common end of the comparator a5 is connected to the inverting input end of the operational amplifier A3, the output end of the comparator a4 outputs a logic level signal UR2, the output end of the comparator a5 outputs a logic level signal UR3, the non-inverting input end of the operational amplifier A3 is connected to one end of the resistor R8, and the common end of the resistor R9, the other end of the resistor R8 is connected to the power supply VCC, and the other end of the resistor R9 is grounded.
4. The open-phase detection circuit of a compressor according to claim 1, wherein the logic operation circuit comprises a first not gate, a second not gate, a first and gate, a second and gate, a third and gate and a fourth and gate, wherein an input terminal of the first not gate is connected to the first output terminal of the signal acquisition circuit and a common terminal thereof is connected to the first input terminal of the third and gate and the first input terminal of the fourth and gate, an output terminal of the first not gate is connected to the first input terminal of the first and gate and a common terminal thereof is connected to the first input terminal of the second and gate, an input terminal of the second not gate is connected to the second output terminal of the signal acquisition circuit and a common terminal thereof is connected to the second input terminal of the second and gate and the second input terminal of the fourth and gate, an output terminal of the second not gate is connected to the second input terminal of the first and gate and a common terminal thereof is connected to the second input terminal of the third and gate, the first AND gate, the second AND gate, the third AND gate and the fourth AND gate are respectively connected with the I/O port of the control chip.
5. The open-phase detection circuit of a compressor as claimed in claim 4, wherein the first not gate and the second not gate are both not gates having one input terminal and one output terminal, and the first and gate, the second and gate, the third and gate and the fourth and gate are both AND gates having two input terminals and one output terminal.
6. A method for detecting a phase loss of a compressor, wherein the method is applied to a phase loss detection circuit of a compressor according to any one of claims 1 to 5.
7. A phase failure detection method of a compressor as claimed in claim 6, comprising the steps of:
acquiring three-phase alternating current information of a motor of the compressor through the signal acquisition circuit;
and the logic operation circuit outputs specific open-phase line information to the control chip according to the three-phase alternating current information of the motor.
8. The method for detecting the open phase of the compressor according to claim 7, wherein the step of obtaining the three-phase alternating current information of the motor of the compressor through the signal acquisition circuit specifically comprises:
acquiring the current values of any two phases of three-phase alternating current of the motor;
the obtained two-phase current values are converted into a logic level signal UR2 and a logic level signal UR3 respectively and output.
9. The method as claimed in claim 8, wherein the step of outputting the specific information of the phase-lacking line to the control chip according to the three-phase ac information of the motor by the logic operation circuit comprises:
the logic operation circuit performs logic operation after the logic level signal UR2 and the logic level signal UR 3;
and outputting the information of the phase-lacking line to the control chip according to the result of the logic operation.
10. A compressor, characterized in that it comprises a phase failure detection circuit of a compressor according to any one of claims 1 to 5.
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