CN110971362A

CN110971362A - Discovery reference signal sending method and device

Info

Publication number: CN110971362A
Application number: CN201811142734.8A
Authority: CN
Inventors: 吴霁; 朱俊; 贾琼
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-09-28
Filing date: 2018-09-28
Publication date: 2020-04-07
Anticipated expiration: 2038-09-28
Also published as: CN110971362B; WO2020063929A1

Abstract

A method and a device for sending a discovery reference signal are used for solving the problem that communication time delay is easy to generate when a terminal receives RMSI CORESET and a corresponding SSB. The method comprises the following steps: the network device performs listen before talk, LBT, and then accesses the channel. The network equipment sends one or more Discovery Reference Signals (DRSs) to a terminal, wherein any one of the DRSs is carried on continuous symbols.

Description

Discovery reference signal sending method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for sending discovery reference signals.

Background

A synchronization pulse sequence set (SS burst set) is defined in a New Radio (NR) standard, and is mainly used for initial access/system message update/beam (beam) management by a UE. An SS burst set is composed of several synchronization signal blocks (PBCH blocks).

Each SS/PBCH block has 4 Orthogonal Frequency Division Multiplexing (OFDM) symbols, which correspond to a Primary Synchronization Signal (PSS), a physical broadcast signal (PBCH), a Secondary Synchronization Signal (SSs), and a PBCH in sequence.

The NR system information is divided into a main system information block (MIB) and Remaining Minimum System Information (RMSI). The MIB is carried in the PBCH and transmitted, and includes basic information required to access the network, and a RMSI control resource block (core) and the like, where the RMSI core is used to indicate a Physical Downlink Shared Channel (PDSCH) carrying the RMSI.

Currently, the reference signal (DRS) found in NR systems at least includes SS/PBCH block, RMSI CORESET, RMSI PDSCH. When DRS is transmitted, it is usually transmitted at a fixed symbol position, for example, at 120kHz subcarrier spacing, the first symbol position of the SS/PBCH block is {4,8,16,20} +28 × n. As shown in fig. 1, the SS/PBCH block may be carried on symbols 4 to 7 of a first slot, may also be carried on symbols 8 to 11 of the first slot for transmission, may also be carried on symbols 2 to 5 of a second slot for transmission, and may also be carried on symbols 6 to 9 of the second slot for transmission. When the SS/PBCH block is sent on symbols 4 to 7 of the first slot, the corresponding RMSI CORESET is sent on

symbols

0 and 1 of the first slot. When the SS/PBCH block is sent on the symbols 8 to 11 of the first slot, the corresponding RMSI CORESET is sent on the

symbols

2 and 3 of the first slot. When the SS/PBCH block is sent on symbols 2 to 5 of the second slot, the corresponding RMSI core is sent on

symbols

12 and 13 of the first slot. When the SS/pbcbhblock bearer is transmitted on symbols 6 to 9 of the second slot, the corresponding RMSI CORESET bearer is transmitted on

symbols

0 and 1 of the first slot.

However, as can be seen from fig. 1, after receiving the RMSICORESET carried on symbol 1 and symbol 0 of the first slot, the UE receives the SS/PBCH block corresponding to the RMSI CORESET after a plurality of symbols are separated, thereby causing a delay in communication.

Disclosure of Invention

The application provides a discovery reference signal sending method and device, which are used for solving the problem that communication delay is easy to generate when a terminal receives RMSI CORESET and corresponding SSB.

In a first aspect, the present application provides a method for sending a discovery reference signal. The method comprises the following steps: the network device performs listen before talk, LBT, and then accesses the channel. The network equipment sends one or more Discovery Reference Signals (DRSs) to a terminal, wherein any one of the DRSs is carried on continuous symbols. In the embodiment of the application, by sending the DRS on consecutive symbols, the symbol interval between the RMSI CORESET and the SSB can be reduced, so that the terminal can receive the SSB without waiting too long after receiving the RMSI CORESET, thereby reducing the communication delay to a certain extent, and by reducing the time interval between the RMSI CORESET and the SSB, the problem of inaccurate demodulation of the DRS due to the long time interval between the RMSI CORESET and the SSB can be solved to a certain extent.

In one possible design, the DRS at least includes a synchronization signal block and control information, where the control information is used to indicate a time-frequency resource where first system information is located, the first system information is system information indicated by main system information in the synchronization signal block, and the synchronization signal block and the control information are carried at a predetermined position in the consecutive symbols.

In one possible design, the any one DRS is transmitted using a first pattern, where N symbols occupied by the synchronization signal block are located behind M symbols occupied by the control information in the first pattern, and N and M are integers greater than 0. In the above design, when the network device sends the discovery reference signal, the control information may be sent in front of the synchronization signal, in addition to the synchronization signal, or in the back of the synchronization signal, and compared with the case where the control information is sent only in front of the synchronization signal, in the above design, the control information may be sent in front of the synchronization signal or in the back of the synchronization signal according to the position of the symbol to be sent, so that the flexibility of sending the control information and the synchronization signal may be improved, the resource utilization rate may be improved, and the communication delay may be reduced to a certain extent.

In one possible design, the any one DRS is transmitted using a first pattern in which N symbols occupied by the synchronization signal block are located before M symbols occupied by the control information. In the above design, when the network device sends the discovery reference signal, the control information may be sent in front of the synchronization signal, in addition to the synchronization signal, or in the back of the synchronization signal, and compared with the case where the control information is sent only in front of the synchronization signal, in the above design, the control information may be sent in front of the synchronization signal or in the back of the synchronization signal according to the position of the symbol to be sent, so that the flexibility of sending the control information and the synchronization signal may be improved, the resource utilization rate may be improved, and the communication delay may be reduced to a certain extent.

In one possible design, the DRS includes a synchronization signal block, control information, and second system information, where the control information is used to indicate a time-frequency resource where first system information is located, the first system information is system information indicated by primary system information in the synchronization signal block, and the second system information at least includes the first system information.

In one possible design, the any DRS is sent using a second pattern, where N symbols occupied by the synchronization signal block are located behind M symbols occupied by the control information in the second pattern, P symbols occupied by the second system information are located behind N symbols occupied by the synchronization signal block, and N, M, and P are integers greater than 0. In the above design, when the network device transmits the discovery reference signal, the control information may be transmitted before the synchronization signal, and the second system information may be transmitted after the synchronization signal block, so that flexibility in transmitting the second system information may be improved.

In one possible design, the any DRS is sent using a second pattern, where N symbols occupied by the synchronization signal block are located in front of M symbols occupied by the control information in the second pattern, P symbols occupied by the second system information are located behind M symbols occupied by the control information, and P is an integer greater than 0. In the above design, when the network device transmits the discovery reference signal, the control information may be transmitted after the synchronization signal, and the second system information may be transmitted after the control information, so that flexibility in transmitting the second system information may be improved.

In a possible design, if the number of symbols behind M symbols occupied by the control information in the same timeslot is smaller than P, the second system information of any DRS occupies multiple continuous symbols in other timeslots, and the multiple continuous symbols occupied by the second system information of any DRS are in the same timeslot. Because the current control information may not support the cross-slot scheduling system information, the second system information is completely transmitted in other time slots when the remaining symbols in the current time slot are insufficient, so that the problem that the second system information cannot be accurately demodulated due to the fact that the control information does not support the cross-slot scheduling system information can be solved.

In a second aspect, the present application provides a method for discovering reference signals. The method comprises the following steps: the terminal receives one or more Discovery Reference Signals (DRSs) from network equipment, wherein any one of the DRSs is carried on continuous symbols. In the embodiment of the application, by sending the DRS on consecutive symbols, the symbol interval between the RMSI CORESET and the SSB can be reduced, so that the terminal can receive the SSB without waiting too long after receiving the RMSI CORESET, thereby reducing the communication delay to a certain extent, and by reducing the time interval between the RMSI CORESET and the SSB, the problem of inaccurate demodulation of the DRS due to the long time interval between the RMSI CORESET and the SSB can be solved to a certain extent.

In a third aspect, the present application provides a method for sending discovery reference signals. The method comprises the following steps: network equipment determines a Discovery Reference Signal (DRS), wherein the discovery reference signal at least comprises a synchronization signal and control information, the control information comprises information of a time-frequency resource where first system information is located, and the first system information is system information indicated by main system information in the synchronization signal; and the network equipment transmits the one or more discovery reference signals to a terminal, wherein any one of the DRSs is carried on continuous symbols. In the embodiment of the application, by sending the DRS on consecutive symbols, the symbol interval between the RMSI CORESET and the SSB can be reduced, so that the terminal can receive the SSB without waiting too long after receiving the RMSI CORESET, thereby reducing the communication delay to a certain extent, and by reducing the time interval between the RMSICORESET and the SSB, the problem of inaccurate demodulation of the DRS due to the long time interval between the RMSICORESET and the SSB can be solved to a certain extent.

In one possible design, the control information is carried on N of the consecutive symbols, the synchronization signal block is carried on M of the consecutive symbols, and the N symbols are adjacent to the M symbols in a time domain, the N, M is an integer greater than 0. In the above design, by reducing the symbol interval between the RMSI CORESET and the SSB, the terminal does not need to wait too long for receiving the SSB after receiving the RMSI CORESET, so that the communication delay can be reduced to some extent, and by reducing the time interval between the RMSI CORESET and the SSB, the problem of inaccurate demodulation of the DRS due to the long time interval between the RMSI CORESET and the SSB can be solved to some extent.

In one possible design, the discovery reference signal further includes second system information, the control information is carried on N symbols of the consecutive symbols, the synchronization signal block is carried on M symbols of the consecutive symbols, the second system information is carried on N symbols other than the N symbols and the M symbols, the control information and the second system information are adjacent in a time domain, and the second system information and the synchronization signal block are adjacent in the time domain. In the above design, the second system information, the control information and the synchronization signal block are borne on adjacent symbols, so that the terminal can schedule the second system information in time after receiving the control information, thereby reducing communication delay and improving resource utilization rate. In addition, the current control information may not support the cross-slot scheduling system information, so that the second system information, the control information and the corresponding second system information can be in one time slot by using the second system information, the control information and the synchronization signal block, so that the control information can be avoided from the cross-slot scheduling system information to a certain extent.

In one possible design, the discovery reference signal further includes second system information, the control information is carried on N symbols of the consecutive symbols, the synchronization signal block is carried on M symbols of the consecutive symbols, the second system information is carried on the M symbols in a frequency division multiplexing manner, and the control information and the synchronization signal block are adjacent in a time domain. In the above design, the second system information is carried on the M symbols in a frequency division multiplexing manner, and the terminal can schedule the second system information in time after receiving the control information, so that communication delay can be reduced, and resource utilization rate can be improved. In addition, currently, the control information may not support the cross-slot scheduling system information, so that the control information and the corresponding second system information can be in one slot by filling the second system information into the idle resource blocks of the M consecutive symbols, thereby avoiding the cross-slot scheduling system information of the control information to a certain extent.

In one possible design, the N symbols include from t x (N + M) +1 symbol to t x (N + M) + N symbols of a slot, the M consecutive symbols include from t x (N + M) + N +1 symbol to t (N + M) + N + M symbol of the slot, and t is an integer greater than or equal to 0.

In one possible design, the discovery reference signal further includes second system information, the control information occupies N consecutive symbols, the synchronization signal block occupies M consecutive symbols following the N consecutive symbols, and the second system information is carried on the M symbols in a frequency division multiplexing manner. In the above design, the second system information is carried on the M symbols in a frequency division multiplexing manner, and the terminal can schedule the second system information in time after receiving the control information, so that communication delay can be reduced, and resource utilization rate can be improved. In addition, currently, the control information may not support the cross-slot scheduling system information, so that the control information and the corresponding second system information can be in one slot by filling the second system information into the idle resource blocks of the M consecutive symbols, thereby avoiding the cross-slot scheduling system information of the control information to a certain extent.

In one possible design, the number of all symbols carrying the control information is carried in the synchronization signal. In the above design, the terminal may determine the transmission mode of the DRS according to the number of all symbols carrying the control information carried in the synchronization signal.

In one possible design, if the network device transmits a discovery reference signal in one time slot, the second system information in the discovery reference signal is transmitted in one or more of the following manners: the second system information is carried on the other symbols of the N continuous symbols except the symbol carrying the control information; the second system information is carried on the M continuous symbols in a frequency division multiplexing mode; the second system information is carried on other symbols in the time slot except the N consecutive symbols and the M consecutive symbols for transmission. When the resource block in one time slot is small or the second system information data volume is large, the discovery reference signal can be sent by adopting the mode, so that the discovery reference signal can be completely sent in one time slot as much as possible, and the accuracy of receiving the discovery reference signal can be further improved.

In one possible design, if the network device sends three discovery reference signals in two time slots, the second discovery reference signal is carried in the symbol carried in the first time slot, and the synchronization signal in the second discovery reference signal is carried in the first M symbols of the second time slot. When there are many resource blocks in a slot, the DRS may be transmitted by using the above design, so that the number of discovery reference signals transmitted in a slot may be increased, and the resource utilization rate may also be increased.

In one possible design, idle resource blocks in the first M symbols of the second slot are filled with downlink signals; or, the idle resource blocks in the first M symbols of the second slot are filled with the synchronization signal in the second discovery reference signal.

In a fourth aspect, the present application provides a method for sending discovery reference signals. The method comprises the following steps: the method comprises the steps that network equipment determines a discovery reference signal, wherein the discovery reference signal at least comprises a synchronization signal, control information and second system information, the control information comprises information of a time-frequency resource where first system information is located, the first system information is system information indicated by main system information in the synchronization signal, and the second system information at least comprises the first system information; the network device starts to send the discovery reference signal to a terminal at a preset position, wherein the discovery reference signal lasts for N symbols, the synchronization signal, the control information and the synchronization information are carried on the N symbols in a frequency division multiplexing mode, and N is an integer greater than 0. In the embodiment of the present application, by loading the synchronization signal, the control information, and the synchronization information on the N symbols in a frequency division multiplexing manner, a relatively large number of discovery reference signals may be sent in one time slot, and taking an example that one time slot includes 14 symbols and N is equal to 4, currently, at most 2 discovery reference signals are sent in one time slot, but according to the embodiment of the present application, 4 discovery reference signals may be sent in one time slot.

In one possible design, the preset position is the t × N +1 symbol in the timeslot, where t is an integer greater than or equal to 0.

In a fifth aspect, the present application provides an apparatus, which may be a terminal, or a network device, and may also be a chip. The device has a function of realizing any one of the designs of the first aspect to the sixth aspect described above. The function can be realized by hardware, and can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the functions described above.

In a sixth aspect, an apparatus is provided, comprising: a processor, a communication interface, and a memory. The communication interface is used for transmitting information, and/or messages, and/or data between the device and other devices. The memory is configured to store computer executable instructions, and when the apparatus is operating, the processor executes the computer executable instructions stored in the memory, so as to enable the apparatus to perform the discovery reference signal transmission method as set forth in any one of the first to fourth aspects.

In a seventh aspect, the present application further provides a system, where the system includes the network device in any embodiment of the foregoing first aspect, the foregoing third aspect, and the foregoing fourth aspect, and the terminal in any embodiment of the foregoing second aspect.

In an eighth aspect, the present application further provides a computer-readable storage medium having stored therein instructions, which, when run on a computer, cause the computer to perform the method of the above aspects.

In a ninth aspect, the present application also provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the above aspects.

Drawings

Fig. 1 is a schematic architecture diagram of a communication system provided in the present application;

fig. 2 is a schematic resource allocation diagram of a synchronization signal provided in the present application;

fig. 3 is a schematic resource allocation diagram of a discovery reference signal provided in the present application;

fig. 4 is a flowchart illustrating a method for discovering a reference signal according to the present application;

fig. 5 is a schematic diagram of a first pattern provided in the present application;

fig. 6A is a schematic resource allocation diagram of a discovery reference signal provided herein;

fig. 6B is a schematic resource allocation diagram of another discovery reference signal provided in the present application;

fig. 6C is a schematic resource allocation diagram of another discovery reference signal provided in the present application;

fig. 7A is a schematic diagram of a second pattern provided in the present application;

fig. 7B is a schematic diagram of another second pattern provided in the present application;

fig. 8A is a schematic resource allocation diagram of another discovery reference signal provided in the present application;

fig. 8B is a schematic resource allocation diagram of another discovery reference signal provided in the present application;

fig. 9A is a schematic diagram of a third pattern provided in the present application;

fig. 9B is a schematic view of another third pattern provided in the present application;

fig. 9C is a schematic view of another third pattern provided in the present application;

fig. 9D is a schematic diagram of another third pattern provided in the present application;

fig. 10 is a schematic diagram of a fourth pattern provided in the present application;

fig. 11 is a schematic diagram of a fifth pattern provided in the present application;

fig. 12 is a flowchart illustrating another method for discovering reference signal transmission provided in the present application;

fig. 13A is a schematic view of a sixth pattern provided in the present application;

fig. 13B is a schematic view of another sixth pattern provided in the present application;

fig. 14A is a schematic diagram of a seventh pattern provided in the present application;

fig. 14B is a schematic diagram of another seventh pattern provided in the present application;

fig. 14C is a schematic view of another seventh pattern provided in the present application;

fig. 15A is a schematic resource allocation diagram of a discovery reference signal provided herein;

fig. 15B is a schematic resource allocation diagram of another discovery reference signal provided in the present application;

fig. 15C is a schematic resource allocation diagram of another discovery reference signal provided in the present application;

fig. 16 is a schematic structural diagram of a communication device provided in the present application;

fig. 17 is a schematic structural diagram of a communication device according to the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings.

The communication method provided by the present application may be applied to various communication systems, for example, internet of things (IoT), narrowband band internet of things (NB-IoT), Long Term Evolution (LTE), fifth generation (5G) communication system, LTE and 5G hybrid architecture, 5G New Radio (NR) system, global system for mobile communication (GSM), mobile communication system (universal mobile telecommunications system, UMTS), Code Division Multiple Access (CDMA) system, and new communication system appearing in future communication development. The discovery reference signal transmission method provided by the embodiments of the present application may be used whenever a multi-beam (beam) is required to transmit control information and/or data in a communication system.

The terminal referred to in the embodiments of the present application is an entity for receiving or transmitting signals at the user side. The terminal may be a device that provides voice and/or data connectivity to a user, such as a handheld device, a vehicle mounted device, etc. with wireless connectivity. The terminal may also be other processing devices connected to a wireless modem. A terminal may communicate with one or more core networks through a Radio Access Network (RAN). A terminal may also be referred to as a wireless terminal, a subscriber unit (subscriber station), a subscriber station (subscriber station), a mobile station (mobile), a remote station (remote station), an access point (access point), a remote terminal (remote terminal), an access terminal (access terminal), a user terminal (user terminal), a user agent (user agent), a user equipment (user device), or a user equipment (user equipment), among others. The terminal equipment may be mobile terminals such as mobile telephones (or so-called "cellular" telephones) and computers with mobile terminals, e.g. portable, pocket, hand-held, computer-included or car-mounted mobile devices, which exchange language and/or data with a radio access network. For example, the terminal device may be a Personal Communication Service (PCS) phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), or the like. Common terminal devices include, for example: the mobile terminal includes a mobile phone, a tablet computer, a notebook computer, a handheld computer, a Mobile Internet Device (MID), and a wearable device, such as a smart watch, a smart bracelet, a pedometer, and the like, but the embodiment of the present application is not limited thereto.

The network device related in the embodiment of the present application is an entity for transmitting or receiving a signal on a network side, and may be configured to perform interconversion between a received air frame and an Internet Protocol (IP) packet, where the interconversion is used as a router between a terminal device and the rest of an access network, where the rest of the access network may include an IP network and the like. The network device may also coordinate management of attributes for the air interface. For example, the network device may be a Base Transceiver Station (BTS) in a global system for mobile communications (GSM) or Code Division Multiple Access (CDMA), a base station (NodeB) in a Wideband Code Division Multiple Access (WCDMA), an evolved Node B (eNB or e-NodeB) in LTE, a new radio controller (NR controller), may be a enode B (gNB) in a 5G system, may be a centralized network element (centralized unit), may be a new wireless base station, may be a radio remote module, may be a micro base station, may be a relay (relay), may be a distributed network element (distributed unit), may be a transmission point (TRP) or a Transmission Point (TP), or any other wireless access device, but the embodiment of the present invention is not limited thereto. The network device may cover 1 or more cells.

Referring to fig. 1, a communication system provided in the embodiment of the present application includes a network device and six terminal devices, i.e., UE 1-UE 6. In the communication system, the UEs 1 to 6 may transmit uplink data to the network device, and the network device may receive the uplink data transmitted by the UEs 1 to 6. Further, the UEs 4 through 6 may also form one sub-communication system. The network device may send downlink information to the UE1, the UE2, the UE3, and the UE5, and the UE5 may send downlink information to the UE4 and the UE6 based on a device-to-device (D2D) technology. Fig. 1 is merely a schematic diagram, and does not specifically limit the type of communication system, and the number, types, and the like of devices included in the communication system.

The network architecture and the service scenario described in the embodiment of the present application are for more clearly illustrating the technical solution of the embodiment of the present application, and do not form a limitation on the technical solution provided in the embodiment of the present application, and as a person of ordinary skill in the art knows that along with the evolution of the network architecture and the appearance of a new service scenario, the technical solution provided in the embodiment of the present application is also applicable to similar technical problems.

The NR standard defines a synchronization burst set (SS burst set) and is mainly used for initial access/system message update/beam management by the UE. An SS burst set is composed of a number of synchronization signal blocks (PBCH blocks). Each SS/PBCH lasts for 4 Orthogonal Frequency Division Multiplexing (OFDM) symbols, and these 4 OFDM symbols in turn carry Primary Synchronization Signal (PSS), physical broadcast signal (PBCH), Secondary Synchronization Signal (SSs), and PBCH, as shown in fig. 2.

In the NR system, system information is divided into a main system information block (MIB), Remaining Minimum System Information (RMSI), and Other System Information (OSI). The MIB is carried in PBCH of SS/PBCH block, and carries basic information needed for accessing network. The RMSI mainly carries cell access and cell selection related information, similar to SIB1 in LTE, as well as NR subframe configuration, scheduling and window information of other SIB blocks, etc. The RMSI includes a RMSICORESET RMSI Physical Downlink Shared Channel (PDSCH). In NR system, to improve system scheduling flexibility, RMSI PDSCH has variable time-frequency resource location and size, and RMSI PDSCH has indicated by RMSICORESET. Indication information for indicating RMSI CORESET is carried in PBCH of SS/PBCH block.

In unlicensed spectrum based NR systems, in some embodiments, the reference signal (DRS) is found to comprise the SS/PBCH block, the RMSI CORESET, RMSI PDSCH. In other embodiments, the DRS may further include OSI, paging (paging), channel state information-reference signal (CSI-RS), and the like.

Currently, the DRS is transmitted in the NR system. The SS/PBCH block is typically transmitted at fixed symbol positions. The NR standard gives the specific time-frequency position of the SS/PBCH block at different subcarrier intervals as follows:

when the subcarrier spacing is 15 KHz: the first symbol position of the SS/PBCH block is {2, 8} +14 x n. When the carrier frequency is less than 3GHz, n is 0, 1; when the carrier frequency is greater than 3GHz and less than 6GHz, n is 0, 1, 2, 3. Illustratively, one slot (slot) includes 14 symbols.

When the subcarrier spacing is 30 KHz: the first symbol position of the SS/PBCH block is {4,8,16,20} +28 x n. When the carrier frequency is less than 3GHz, n is 0; when the carrier frequency is greater than 3GHz and less than 6GHz, n is 0, 1.

When the subcarrier spacing is 30 KHz: the first symbol position of the SS/PBCH block is {2, 8} +14 x n. When the carrier frequency is less than 3GHz, n is 0, 1; when the carrier frequency is greater than 3GHz and less than 6GHz, n is 0, 1, 2, 3.

When the subcarrier spacing is 120 KHz: the first symbol position of the SS/PBCH block is {4,8,16,20} +28 x n. When the carrier frequency is greater than 6GHz, n is 0, 1, 2, 3, 5, 6, 7, 8, 10, 11, 12, 13, 15, 16, 17, 18. .

When the subcarrier spacing is 240 KHz: the first symbol position of the SS/PBCH block is {8, 12, 16,20, 32, 36, 40, 44} +56 x n. When the carrier frequency is greater than 6GHz, n is 0, 1, 2, 3, 5, 6, 7, 8.

Because the SS/PBCH block needs to last 4 symbols, the specific time-frequency position of the SS/PBCH block under different subcarrier intervals given by the NR standard is known, and when the DRS is transmitted, the RMSI CORESET corresponding to the two SS/PBCH blocks is usually transmitted in sequence. And after the RMSI CORESET corresponding to the two SS/PBCH blocks is sent, the two SS/PBCH blocks are sent in sequence. Taking the subcarrier spacing of 120KHz as an example, as shown in fig. 3,

symbols

0 and 1 occupying slot0 transmit RMSI CORESET1 in DRS1,

symbols

2 and 3 occupying slot0 transmit RMSI CORESET2 in DRS2, symbols 4 to 7 occupying slot0 transmit SS/PBCH block1 in DRS1, and symbols 8 to 11 occupying slot0 transmit SS/PBCH block2 in DRS 2.

Symbols

12 and 13 occupying slot0 transmit RMSI CORESET3 in DRS3,

symbols

0 and 1 occupying slot 1 transmit RMSI CORESET4 in DRS4, symbols 2-5 occupying slot 1 transmit SS/PBCH block3 in DRS3, and symbols 6-9 occupying slot 1 transmit SS/PBCH block4 in DRS 4.

In this transmission mode, the SS/PBCH block and the RMSI CORESET in the same DRS are separated by multiple symbols, so the UE needs to wait for multiple symbols before receiving the SS/PBCH block after receiving the RMSI CORESET, as shown in fig. 3, and after receiving RMSI CORESET1 at

symbols

0 and 1, the terminal needs to wait for two symbols (i.e., symbols 2 and 3) before receiving SS/PBCH block1 at symbols 4-6, resulting in a delay in communication. In addition, the SS/PBCH block cannot perform cross-slot scheduling, that is, PBCH in the SS/PBCH block can only schedule RMSI CORESET in the slot where the SS/PBCH block is located, but according to the transmission mode shown in fig. 3, the SS/PBCH block3 is in slot0 of RMSI CORESET3, and the SS/PBCH block3 is in slot 1, so that the terminal may not normally receive DRS3, and further, the terminal may not synchronize with the cell.

Based on this, embodiments of the present application provide a DRS sending method and apparatus, and provide a novel DRS structure, so as to avoid a problem that a terminal may not be synchronized with a cell because the terminal cannot normally receive DRSs. The method and the device are based on the same inventive concept, and because the principles of solving the problems of the method and the equipment are similar, the implementation of the device and the method can be mutually referred, and repeated parts are not repeated.

The network device transmits the DRS using a single beam (single beam) in one slot. So that the terminal can receive the DRS using a single beam in one slot. In other embodiments, the network device may transmit the DRS repeatedly using a single beam over multiple consecutive time slots. So that the terminal can repeatedly transmit the DRS using a single beam at a plurality of slots.

In still other embodiments, a network device may transmit DRSs via multiple beams (multiple beams) in a plurality of consecutive timeslots using the DRS transmission method provided herein. The mapping pattern of DRS can be seen in various patterns provided herein. The terminal can receive the DRS through the multi-beam by using the DRS transmission method provided by the present application in a plurality of consecutive time slots. Therefore, flexible configuration of the DRS under a single-beam scene or a multi-beam scene is realized. It can be understood that when the terminal receives one DRS, corresponding decoding can be performed; when the terminal receives multiple DRSs, robustness can be enhanced.

In other embodiments, a network device may transmit one DRS in one slot, or may transmit multiple DRSs, where the multiple DRSs may be the same or different. In this time slot, the network device may transmit one or more DRSs using a single beam, or may transmit multiple DRSs using multiple beams. Optionally, the multiple DRSs may be DRSs carrying the same content, or may be DRSs carrying different contents. Accordingly, a terminal may receive one DRS in one slot, or may receive multiple DRSs, where the multiple DRSs may be the same or different. In the one slot, the terminal may receive one or more DRSs using a single beam, or may receive multiple DRSs using multiple beams. Of course, the multiple DRSs may be DRSs carrying the same content, or DRSs carrying different contents.

In other embodiments, the network device may transmit one DRS in multiple consecutive slots respectively by using a transmission scheme similar to the DRS in one slot, or may transmit multiple DRSs in multiple consecutive slots continuously. Optionally, the multiple DRSs may be DRSs carrying the same content, or may be DRSs carrying different contents. Accordingly, the terminal may receive one DRS in multiple consecutive slots respectively by using a transmission scheme similar to the DRS in one slot, or may receive multiple DRSs continuously in multiple consecutive slots. Of course, the multiple DRSs may be DRSs carrying the same content, or DRSs carrying different contents.

For different beams, it may transmit the same DRS or different DRSs. For the same beam, the same DRS may be continuously transmitted, or different DRSs may be continuously transmitted.

The plural in the present application means two or more.

In addition, it is to be understood that the terms first, second, etc. in the description of the present application are used for distinguishing between the descriptions and not necessarily for describing a sequential or chronological order.

The DRS transmission method provided in the embodiment of the present application is specifically described below with reference to the drawings.

Referring to fig. 4, a flowchart of a DRS transmission method provided in the present application is shown, where the method includes:

s401, a network device determines a DRS, wherein the DRS at least comprises a synchronization signal and control information, and the control information comprises information of a time-frequency resource where first system information is located.

The synchronization signal may be an SS/PBCH block. The first system information may carry cell access and cell selection related information, as well as NR subframe configuration, scheduling and window information of other SIB blocks, and the like. The naming of the first system information is different in each access system, for example, in LTE, the first system information is SIB 1. In the NR system, the first system information is RMSIPDSCH. It is possible in future communication systems to name the first system information by other names, such as XX. It should be understood that XX may also be understood as the first system information in the embodiment of the present application if XX may also implement the function implemented by the first system information in the embodiment of the present application. For convenience of description, in the embodiment of the present application, the first system information is described as an example, which is RMSI. If the first system information is RMSI PDSCH, the control information may be RMSI CORESET.

In other embodiments, the DRS may further include second system information, which may include RMSIPDSCH, OSI, and the like. The DRS may also include other information such as paging, CSI-RS, or other downlink signals, etc.

In other embodiments, DRS may be predefined. That is, S401 is not a step that has to be executed.

S402, the network equipment sends one or more Discovery Reference Signals (DRS) to a terminal, wherein any one of the DRS is carried on continuous symbols.

And S403, the terminal receives one or more DRSs sent by the network equipment. Wherein, the terminal may receive the DRS at a preset location.

In one possible embodiment, the DRS may be transmitted in a first pattern. In the first pattern, N symbols occupied by the synchronization signal block are located behind M symbols occupied by the control information, where N and M are integers greater than 0.

In one example, in the first pattern, N consecutive symbols, M consecutive symbols include a fixed number of symbols, and a position in the time domain is fixed. For example, the positions of N consecutive symbols may be from the t × N + M +1 symbol to the t × N + M + N symbol of one slot, and the positions of M consecutive symbols may be from the t × N + M + N +1 symbol to the t × N + M symbol of one slot, where t is an integer greater than or equal to 0. Taking an example where one slot includes 14 symbols, N is 3, and M is 4, the first pattern may be: the symbol positions for carrying the first RMSI CORESET are symbols 0-2, the symbol positions for carrying the first SS/PBCH block are symbols 3-6, the symbol positions for carrying the second RMSICORESET are symbols 7-9, and the symbol positions for carrying the second SS/PBCH block are symbols 10-13, as shown in FIG. 5.

Alternatively, in the first pattern, the number of symbols included in M consecutive symbols is fixed, and the position in the time domain is fixed. For example, the positions of the M consecutive symbols may be from the t × N + M + N +1 symbol to the t × N + M + N + M symbol of one slot, the M symbols may carry the SS/PBCH block, and the N symbols located before and adjacent to the M symbols in the time domain may carry the RMSI CORESET. If two DRSs are transmitted in one slot, the first N consecutive symbols carrying the RMSI CORESET precede the first M consecutive symbols carrying the SS/PBCH block, and the second N consecutive symbols carrying the RMSI CORESET precede the first M consecutive symbols carrying the SS/PBCH block and the second M consecutive symbols carrying the SS/PBCH block. When there is an idle symbol between the RMSICORESET and the corresponding SS/PBCH block, the padding may be performed with the second system information, other information in the DRS (e.g., paging, CSI-RS, or other downlink signals, etc.).

Illustratively, the N consecutive symbols may be referred to as a first symbol group, and the M consecutive symbols may be referred to as a second symbol group.

In one implementation, when the network device sends the DRS to the terminal according to the first pattern, the method may be implemented as follows:

a1, padding RMSI CORESET to N symbols, and padding SS/PBCH block to M symbols after the N symbols.

A2, referring to fig. 6A, if the RMSI CORESET occupies N symbols in one slot, the second system information, and other information in the DRS and the SS/PBCH block occupy M symbols in a frequency division multiplexing manner. Referring to fig. 6B and 6C, if the RMSI CORESET occupies N symbols in one slot, where N is an integer less than N, the second system information, as well as other information in the DRS, may be padded on one or more of the following resources: an idle symbol of the N symbols, i.e., a symbol of the N symbols that does not carry a RMSI core set, and an idle resource block of the M symbols, i.e., a resource block of the M symbols that does not carry a SS/PBCH block.

Taking the first pattern shown in fig. 5 as an example, when the network device sends two DRSs to the terminal according to the first pattern, the two DRSs occupy 14 symbols of one slot, where RMSI CORESET in the first DRS occupies symbols 0 to 2, and PSS, PBCH, SSs, and PBCH in SS/PBCH block of the first DRS occupy symbols 3 to 6 in sequence. And filling the second system information of the first DRS and other information included in the first DRS into idle resource blocks in symbols 0-2 and/or idle resource blocks in symbols 3-6. The symbols 7-9 are occupied by RMSI CORESET of the second DRS, and the symbols 10-13 are sequentially occupied by PSS, PBCH, SSS and PBCH in SS/PBCH block of the second DRS. And filling the second system information of the second DRS and other information included in the second DRS into idle resource blocks in symbols 7-9 and/or idle resource blocks in symbols 10-13. The RMSI CORESET lasts for 3 symbols, that is, the first RMSI CORESET occupies all symbols in the symbols 0-2, the second RMSICORESET occupies all symbols in the symbols 7-9, and the resource allocation of the two DRSs can be seen in FIG. 6A. The RMSI CORESET lasts for 2 symbols, i.e., the first RMSI CORESET occupies symbol 0 and symbol 1 in symbols 0-2, and the second RMSICORESET occupies symbol 7 and symbol 8 in symbols 7-9, and the resource allocation of the two DRSs can be seen in FIG. 6B. RMSICORESET lasts for 1 symbol, namely the first RMSI CORESET occupies symbol 0 in symbols 0-2, the second RMSICORESET occupies symbol 7 in symbols 7-9, and the resource allocation of the two DRSs can be seen in FIG. 6C.

The occupation in the foregoing embodiment means that corresponding symbols carry corresponding information, and taking RMSIORESET occupation symbols 0-2 in the first DRS as an example, means that symbols 0-2 carry RMSI CORESET in the first DRS.

In a first pattern, when the RMSI CORESET occupies all 3 symbols in the first symbol group, no idle symbol in the first symbol group may transmit the second system information, as well as other information included in the DRS. Due to the fact that the number of resource blocks contained in the 20MHz bandwidth is larger at the low subcarrier spacing, more second system information, other information included in the DRS and SS/PBCH block are frequency division multiplexed into the second symbol group, and therefore the method can be suitable for the low subcarrier spacing scene. When the RMSI CORESET occupies all 1 symbol in the first symbol group, 2 idle symbols in the first symbol group may transmit the second system information, as well as other information included in the DRS, i.e., symbol 1 and symbol 2, or symbol 9 and symbol 9. When the RMSI CORESET occupies all 1 symbol in the first symbol group, 1 free symbol in the first symbol group may transmit the second system information, and other information included in the DRS, for example: symbol 2 in fig. 6B, or symbol 9.

The PBCH of the SS/PBCH block in the DRS may carry a time index to indicate the sequence number of the current SS/PBCH block. In the above scenario, the terminal detects the SS/PBCH block and then obtains the symbol-level time synchronization according to the time index carried in the PBCH block. Taking the first pattern shown in fig. 5 as an example, if the timeidedex carried in the SS/PBCH block is 0, the SS/PBCH block is located at symbols 3-6, the PSS is located at symbol 3, and if the timeidedex carried in the SS/PBCH block is 1, the SS/PBCH block is located at symbols 10-13, and the PSS is located at symbol 10. So that the terminal can perform cell synchronization according to the symbol position of the PSS.

In another possible implementation, when the network device sends the DRS to the terminal, the network device may also send the DRS according to the second pattern. In the second pattern, the RMSI CORESET occupies N symbols, the SS/PBCH block occupies M symbols, and the symbols occupied by the SS/PBCH block immediately follow the symbols occupied by the RMSI CORESET.

Take the example where a slot includes 14 symbols, N equals 2, and M equals 4, i.e. RMSI CORESET lasts 2 symbols, and SS/PBCH block lasts 4 symbols. The first RMSI CORESET occupies symbol 0 and symbol 1, the first SS/pbcblock occupies symbols 2-5, the second RMSI CORESET occupies symbols 6 and symbol 7, the second SS/PBCH block occupies symbols 8-11, and the second pattern can be seen in fig. 7A. If N is equal to 1, M is equal to 4, i.e., RMSI CORESET lasts 1 symbol, SS/PBCH block lasts 4 symbols, the first RMSI CORESET occupies symbol 0, the first SS/PBCH block occupies symbols 1 to 4, the second RMSI CORESET occupies symbol 5, the second SS/PBCH block occupies symbols 6 to 9, and the second pattern can be seen in fig. 7B.

In an implementation manner, when the network device sends the DRS to the terminal according to the second pattern, the method may be implemented as follows:

b1, referring to fig. 8A or fig. 8B, the RMSI CORESET occupies N symbols, and the SS/PBCH block occupies M symbols after the N symbols.

B2, the second system information and other information included in DRS occupy M symbols in a frequency division multiplexing manner.

Taking the second pattern shown in fig. 7A as an example, when the network device sends two DRSs to the terminal according to the second pattern, the two DRSs occupy 14 symbols of one slot, where RMSI CORESET in the first DRS occupies symbol 0 and symbol 1, and PSS, PBCH, SSs, and PBCH in SS/PBCH block of the first DRS occupy symbols 2 to 5 in sequence. And the second system information of the first DRS and other information included in the first DRS can occupy symbols 2-5 in a frequency division multiplexing mode. And the symbol 6 and the symbol 7 are occupied by RMSI CORESET of the second DRS, and the symbols 8-11 are sequentially occupied by PSS, PBCH, SSS and PBCH in SS/PBCH block of the second DRS. The second system information of the second DRS and other information included in the second DRS may occupy symbols 8 to 11 in a frequency division multiplexing manner, and resource allocation of the two DRSs may be shown in fig. 8A.

Taking the second pattern shown in fig. 7B as an example, when the network device sends two DRSs to the terminal according to the second pattern, the two DRSs occupy 14 symbols of one slot, where RMSI CORESET in the first DRS occupies symbol 0, and PSS, PBCH, SSs, and PBCH in SS/PBCH block of the first DRS occupy symbols 1 to 4 in sequence. And the second system information of the first DRS and other information included in the first DRS can occupy symbols 1-4 in a frequency division multiplexing mode. And the symbol 5 is occupied by RMSI CORESET of the second DRS, and the symbols 6-9 are sequentially occupied by PSS, PBCH, SSS and PBCH in SS/PBCH block of the second DRS. The second system information of the second DRS and other information included in the second DRS may occupy symbols 6 to 9 in a frequency division multiplexing manner, and resource allocation of the two DRSs may be shown in fig. 8B.

As shown in fig. 8A and 8B, there are last 2-4 idle symbols in the slot, and these idle symbols can be used to transmit other information in the DRS, such as CSI-RS or other downlink reference signals/control signals/data, etc.

In one implementation, the PBCH in the SS/PBCH block may carry the number of all symbols carrying the RMSI CORESET. That is, PBCH in SS/PBCH block may carry the number of symbols occupied by RMSI CORESET. Therefore, the terminal can determine the number of persistent symbols of the RMSI core by using the PBCH carrying information, thereby determining which of the multiple patterns shown in fig. 5, 7A, and 7B is used for the DRS to transmit.

When the symbol carrying the RMSI CORESET and the symbol carrying the corresponding SS/PBCH block are continuous in time and the RMSI CORESET duration is less than 3 symbols, the last 2-4 symbols in the slot can be vacated to transmit other downlink signals/data, such as CSI-RS and the like. And the terminal can judge the actual symbol position of the SS/PBCH block according to the continuous symbol number of RMSI CORESET in the SS/PBCH block and obtain accurate time synchronization. The PBCH of the SS/PBCH block in the DRS can carry time index to indicate the sequence number of the current SS/PBCH block, so that the terminal can acquire the time synchronization of symbol level according to the time index carried in the PBCH after detecting the SS/PBCH block. For example, when the time index carried in the SS/PBCH block is 0 and the RMSI core lasts for 1 symbol, the terminal may determine that the network device adopts the pattern shown in fig. 7B. Thus, the terminal may determine that the SS/PBCH block is located at symbols 1-4 and the PSS is located at symbol 3. The terminal may determine that the network device is using the pattern shown in fig. 7B when the time index carried in the SS/pbcblock is 1 and the RMSI core lasts 1 symbol. Thus, the terminal may determine that the SS/PBCH block is located at symbol 6-9 and the PSS is located at symbol 6. So that the terminal can perform cell synchronization according to the symbol position of the PSS.

Further, the number of RMSI CORESET continuous symbols corresponding to two SS/PBCH blocks in a slot can be the same.

In another possible implementation, if the network device sends one DRS in one slot, the network device may send the DRS according to a third pattern when sending the DRS to the terminal. In the third pattern, the N symbols occupied by the RMSI CORESET and the M symbols occupied by the SS/PBCH block may refer to the symbol occupied by the first RMSI CORESET and the symbol occupied by the first SS/PBCH block in the patterns shown in fig. 5, fig. 7A, or fig. 7B, which is not repeated herein. In the third pattern, the second system information and other information in the DRS may occupy other symbols except for the symbol occupied by the RMSI CORESET and the symbol occupied by the SS/PBCH block in the timeslot, and the second system information and other information in the DRS may also occupy M symbols carrying the SS/PBCH block in a frequency division multiplexing manner.

The N symbols occupied by the RMSI CORESET and the M symbols occupied by the SS/PBCH block in the third pattern are similar to the symbols occupied by the first RMSI CORESET and the first SS/PBCH block in the first pattern, that is, the number of symbols included in N consecutive symbols and M consecutive symbols is fixed, and the position in the time domain is fixed. Taking an example where one slot includes 14 symbols, if N is 1 and M is 4, the third pattern may be: RMSI CORESET occupies the symbol 0. The SS/PBCH block occupies symbols 3-6. The symbols 3-6 are occupied by the second system information and other information in the DRS in a frequency division multiplexing manner, and the

symbols

1, 2, and 7-13 are occupied by the second system information and other information in the DRS, as shown in fig. 9A. If N is 2 and M is 4, the third pattern may be: RMSI CORESET occupies symbol 0 and symbol 1. The SS/PBCH block occupies symbols 3-6. The symbols 3-6 are occupied by the second system information and other information in the DRS in a frequency division multiplexing manner, and the symbols 2 and 7-13 are occupied by the second system information and other information in the DRS, as shown in fig. 9B. If N is 3 and M is 4, the third pattern may be: RMSICORESET occupies symbols 0-2. The SS/PBCH block occupies symbols 3-6. The symbols 3-6 are occupied by the second system information and other information in the DRS in a frequency division multiplexing manner, and the symbols 7-13 are occupied by the second system information and other information in the DRS, as shown in fig. 9C.

It should be noted that, this is only an exemplary illustration, and the time domain position of the symbol occupied by the SS/PBCH block may not be fixed to the symbols 3-6 in the slot, may also be fixed to 9-12, and so on. Therefore, when CSI-RS or other downlink reference signals need to be transmitted at symbols 3-6, the SS/PBCH block may be transmitted at other locations within the slot, such as symbols 9-12. The starting position of the RMSI CORESET may be fixed at the symbol 0, but the number of persistent symbols may be dynamically adjusted.

The N symbols occupied by the RMSI CORESET and the M symbols occupied by the SS/PBCH block in the third pattern are similar to the symbols occupied by the first RMSI CORESET and the first SS/PBCH block in the second pattern, that is, the number of symbols included in N consecutive symbols and M consecutive symbols is fixed, and the position in the time domain is fixed. Taking an example where one slot includes 14 symbols, if N is 1 and M is 4, the third pattern may be: RMSI CORESET occupies the symbol 0. The SS/PBCH block occupies symbols 1-4. The symbols 1-4 are occupied by the second system information and other information in the DRS in a frequency division multiplexing manner, and the symbols 5-13 are occupied by the second system information and other information in the DRS, as shown in fig. 9D.

In one implementation, when the network device sends the DRS to the terminal according to the third pattern, the DRS may be implemented as follows, with reference to fig. 9A to 9D:

d1, RMSI CORESET occupies N symbols, SS/PBCH block occupies M symbols.

D2, the second system information, other information occupying one or more of the following resources: the idle symbols in the slot are symbols which do not carry the RMSI CORESET and the SS/PBCH block in the slot, and the idle resource blocks in the M symbols which carry the SS/PBCH block are resource blocks which do not carry the SS/PBCH block in the M symbols.

In one implementation, the PBCH in the SS/PBCH block may carry the number of all symbols carrying the RMSI CORESET. That is, PBCH in SS/PBCH block may carry the number of symbols occupied by RMSI CORESET. Therefore, the terminal can determine the number of persistent symbols of the RMSI CORESET by using the information carried by the PBCH, and thus determine which of the multiple patterns shown in fig. 9A to 9D is used for the DRS to transmit.

Since the 20MHz bandwidth contains a smaller number of RBs at high subcarrier spacing, more symbols are needed to transmit the second system information, as well as other information in the DRS. In an implementation where one DRS is transmitted in one slot, when the RMSI core lasts for 3 symbols, there are 7 separate symbols in the slot that can transmit the second system information and other information in the DRS. When the RMSI CORESET lasts 2 symbols, there are 8 separate symbols in the slot that can transmit the second system information, as well as other information in the DRS. When the RMSI CORESET lasts 1 symbol, there are 9 separate symbols in the slot that can transmit the second system information, as well as other information in the DRS. This implementation may be suitable for large subcarrier spacing scenarios.

In the implementation manner, when the network device sends multiple DRSs in multiple slots, the terminal detects the SS/PBCH block and then obtains symbol-level time synchronization in the slots according to the time index carried in the PBCH. For example, taking the example that the time domain position of the symbol occupied by the SS/PBCH block is fixed at symbols 3-6, if the time index carried in the SS/PBCH block is 0, the PSS of the SS/PBCH block is located at symbol 3 of slot 0. And the PSS of the SS/PBCH block is positioned in a symbol 3 of slot 1 if the time index carried in the SS/PBCH block is 1. Therefore, the terminal can carry out cell synchronization according to the slot position of the SS/PBCH block and the symbol position of the PSS.

In another possible implementation, if the network device sends three DRSs in two slots, the network device may send the DRSs according to a fourth pattern when sending the DRSs to the terminal. A fourth pattern may be in units of two slots, wherein a second DRS may immediately follow the first DRS, a third DRS may immediately follow the second DRS, and second system information of the second DRS may all be in the same slot when a symbol occupied by the second DRS spans the slot. When the second system information of the second DRS and the SS/PBCH block of the second DRS are in two slots, respectively, the bandwidth of M symbols carrying the SS/PBCH block of the second DRS may be filled with other information in the second DRS, or the bandwidth of M symbols carrying the SS/PBCH block of the second DRS may be filled with repeated SS/PBCH blocks.

Taking a slot including 14 symbols, N equals 3, and M equals 4 as an example, as shown in fig. 10, the fourth pattern may be: the first DRS can occupy symbols 0-8 of slot0, the second DRS can occupy symbols 9-13 of slot0 and symbols 0-3 of slot 1, and the third DRS can occupy symbols 4-12 of slot 1. In the symbol 0-8 of slot0, RMSI CORESET of the first DRS occupies symbol 0-2 of slot0, SS/PBCH block of the first DRS occupies symbol 3-6 of slot0, second system information and other information of the first DRS occupy symbol 3-6 of slot0 in a frequency division multiplexing mode, and the second system information and other information of the first DRS also occupy symbol 7 and symbol 8 of slot 0. In the symbols 9-13 of slot0 and the symbols 0-3 of slot 1, the RMSI CORESET of the second DRS occupies the symbols 9-11 of slot0, the SS/PBCH block of the second DRS occupies the symbols 0-3 of slot 1, the second system information of the second DRS occupies the

symbols

12 and 13 of slot0, and other information of the second DRS can occupy the symbols 0-3 of slot 1 and/or the

symbols

12 and 13 of slot0 in a frequency division multiplexing manner.

In one implementation, when the network device sends the DRS to the terminal according to the fourth pattern, the method may be implemented as follows, with reference to fig. 10:

e1, the first DRS occupies the first P symbols of the first slot, where P is an integer greater than or equal to N + M.

E2, the RMSI CORESET of the second DRS and the second system information occupy the idle symbol of the first slot, i.e., the symbol in the first slot that does not carry the first DRS. The SS/PBCH block of the second DRS occupies the first M symbols of the second slot.

The idle resource blocks of the SS/PBCH block not carrying the second DRS in the first M symbols of slot 1 may be filled with other information in the second DRS, or may be filled by repeating the SS/PBCH block.

E3, the third DRS occupies symbols after the first M symbols of the second slot.

In one possible implementation, PBCH in SS/PBCH block may indicate the number of persistent symbols of RMSI CORESET and slot where the number of persistent symbols of RMSI CORESET may be set to be selectable, and when the SS/PBCH lock transmission mode is fixed, the number of persistent symbols of RMSI CORESET may not need to be indicated.

The second system information of the second DRS may also occupy the first M symbols of the second slot in a frequency division multiplexing manner. In this case, the RMSI CORESET may indicate whether there is second system information frequency division multiplexed with the SS/PBCH block. When there is frequency division multiplexing of the second system information and the SS/PBCH block, transmission parameters such as Modulation and Coding Scheme (MCS), modulation mode, and the like of the second system information frequency division multiplexed with the SS/PBCH block may be the same as RMSI PDSCH of the complete symbol. Taking fig. 10 as an example, if the second system information of the second DRS occupies

symbols

12 and 13 of slot0 and occupies symbols 0 to 3 of slot 1 in a frequency division multiplexing manner with the SS/PBCH block, the RMSI CORESET may indicate that the second system information is frequency division multiplexed with the SS/PBCH block. Therefore, when demodulating the second system information carried on the symbols 0-3 of slot 1, the terminal device may adopt the transmission parameters such as MCS, modulation mode and the like adopted when demodulating the complete second system information, thereby realizing the cross-slot scheduling of the second system information. The duration of the second system information frequency-division multiplexed with the SS/PBCH block may also be indicated in the RMSI core, such as for 1, or 2, or 3, or 4 symbols. Within the persistent symbol, only the second system information and the SS/PBCH block may be frequency division multiplexed, i.e., both occupy the entire bandwidth.

If the second system information is not frequency division multiplexed with the SS/PBCH block, that is, when the second system information is all carried in the

symbols

12 and 13 of slot0, the bandwidth of the symbols 0 to 3 of slot 1 may be filled with other information in the DRS, or the bandwidth of the symbols 0 to 3 of slot 1 may be filled with the repeated SS/PBCH block. As shown in fig. 10, there are last 1 idle symbol in the slot, and this idle symbol may be used to transmit other information in the DRS, such as CSI-RS or other downlink reference signals/control signals/data, and so on.

In another possible implementation, if the network device transmits three DRSs in one slot, the DRSs may be transmitted according to a fifth pattern. In a fifth pattern, a second DRS may immediately follow the first DRS, and a third DRS may immediately follow the second DRS. Each DRS occupies M symbols, and SS/PBCH block, RMSICORESET and second system information of the DRS are carried on the M symbols in a frequency division multiplexing mode.

Taking a slot including 14 symbols, M equals 4 as an example, as shown in fig. 11, the fifth pattern may be: the first DRS can occupy symbols 0-3, the second DRS can occupy symbols 4-7, and the third DRS can occupy symbols 8-11. And the SS/PBCH block and the RMSI CORESET of the first DRS, the second system information and other information occupy symbols 0-3 in a frequency division multiplexing mode. And the SS/PBCH block and the RMSI CORESET of the second DRS, second system information and other information occupy symbols 4-7 in a frequency division multiplexing mode. And the SS/PBCH block and RMSICORESET of the third DRS, the second system information and other information occupy symbols 8-11 in a frequency division multiplexing mode.

In one implementation, when the network device sends the DRS to the terminal according to the fifth pattern, the method may be implemented as follows, with reference to fig. 11:

f1, the SS/PBCH block and RMSI CORESET of the first DRS, the second system information and other information occupy the first M symbols of the time slot by adopting a frequency division multiplexing mode.

F2, the SS/PBCH block and RMSI CORESET of the second DRS, the second system information and other information occupy M symbols behind the first DRS in a frequency division multiplexing mode.

F3, the SS/PBCH block and RMSI CORESET of the third DRS, the second system information and other information occupy M symbols behind the second DRS in a frequency division multiplexing mode.

In a scenario with a large subcarrier spacing, such as a 60kHz subcarrier spacing, the 20MHz bandwidth contains fewer RBs, and therefore only RMSI CORESET and SS/PBCH block may be frequency division multiplexed, and at this time, corresponding second system information and other information may be sent in subsequent slots.

A terminal operating in an unlicensed band can detect whether a channel is idle and access the channel to operate without authorization. In order to ensure coexistence with other terminals operating in the unlicensed frequency band, a Listen-Before-Talk (Listen-Before-Talk, LBT) channel contention access mechanism may be employed. Before LBT, the terminal determines a backoff priority according to the importance of data to be transmitted and the data size, and randomly selects a backoff number according to the priority, wherein the backoff number is the number of time slots that the terminal needs to wait when listening to the idle channel. For example, when the backoff number is 7, the terminal needs to continuously listen to all of 7 slots being idle during LBT to transmit data. The terminal may not pass before the first symbol of a slot after LBT and thus may generate a time offset, e.g., a symbol level offset of 4 symbols if the terminal passes before symbol 4 of a slot after LBT. Based on this, the embodiment of the present application further provides another DRS transmission method. Referring to fig. 12, the method includes:

s1201, the network device performs listen before talk, LBT, and then accesses the channel.

S1202, the network device sends one or more DRSs to a terminal, where any one of the DRSs is carried on a continuous symbol.

For example, the DRS may include a synchronization signal and control information, where the control information is used to indicate a time-frequency resource where first system information is located, where the first system information is system information indicated by primary system information in the synchronization signal block, and the synchronization signal block and the control information are carried in a predetermined position in the consecutive symbols.

The synchronization signal may be an SS/PBCH block. The first system information may be RMSI PDSCH. The control information may be RMSI CORESET.

In some further embodiments, second system information may also be included in the DRS. The second system information may include RMSI PDSCH, and may also include OSI, etc.

In other embodiments, the DRS may also include other information, such as paging, CSI-RS, or other downlink signals, etc.

S1203, the terminal receives one or more DRSs sent by the network device. Wherein, the terminal may receive the DRS at a preset location.

In a first manner, the DRS may be transmitted using a sixth pattern.

In one example, the sixth pattern may occupy M symbols for SS/PBCH block and RMSI CORESET in a frequency division multiplexing manner. And the second system information and other information occupy the symbols behind the M symbols in a time division multiplexing mode. When the network device sends the DRS according to the sixth pattern, the DRS may be implemented as follows: the SS/PBCH block and the RMSI CORESET adopt a frequency division multiplexing mode to occupy M symbols from the symbol to be transmitted. And the second system information and other information occupy the symbols behind the M symbols in a time division multiplexing mode.

The symbol to be transmitted may be determined according to an LBT result, and a time offset exists between the symbol to be transmitted and a first symbol of a slot. For example, if the network device passes before symbol 4 after LBT, the symbol to be transmitted may be symbol 4. The time offset may be carried in the synchronization signal, or the time offset may be carried in the control information.

The SS/PBCH block and the RMSI CORESET can occupy the whole bandwidth of N symbols in a frequency domain by adopting a frequency division multiplexing mode, and the SS/PBCH block and the RMSI CORESET are positioned in the same time unit in a time domain and continue for continuous N symbols. The second system information can be jointly transmitted with the SS/PBCH block and the RMSI CORESET in a time division multiplexing mode. Other information in the DRS can be jointly transmitted with the SS/PBCH block and the RMSICORESET in a frequency division multiplexing mode, and can also be jointly transmitted with second system information in a frequency division multiplexing or time division multiplexing mode.

Further, when the network device sends the second system information, if the number of symbols remaining in the slot after the SS/PBCH block and the RMSI CORESET are sent is not less than T, the second system information occupies T symbols behind the M symbols. That is, if the remaining symbols in the slot after the network device has sent the SS/PBCH block and the RMSI CORESET are sufficient, the second system information may be sent after the SS/PBCH block and the RMSI CORESET, as shown in fig. 13A. And if the number of the symbols left in the slot after the SS/PBCH block and the RMSI CORESET are sent is less than T, the second system information occupies P continuous symbols at any position of other slots. It should be noted that P may be greater than T, or smaller than T, or equal to T, and a value of P may be determined according to resource allocation conditions of other time slots and parameters such as a time interval between the other time slot and the current time slot. That is, if the remaining symbols in the slot after the network device has sent the SS/PBCH block and the RMSI core are not enough, the second system information may be sent in other slots, such as 4 consecutive symbols of the next slot, as shown in fig. 13B.

In the first mode, the RMSI CORESET and the SS/PBCH block occupy the same time unit in a frequency division multiplexing manner, and the RMSI CORESET and the SS/PBCH block continue for N symbols as well. RMSI CORESET and SS/PBCHLock can slide within the slot according to LBT results. Compared with the mode that the RMSI CORESET and the SS/PBCH block can only be sent at fixed positions, the network equipment can send the RMSI CORESET and the SS/PBCH block when waiting to reach the fixed positions, the mode of sending the time domain positions of the RMSI CORESET and the SS/PBCH block is more flexible, the RMSI CORESET and the SS/PBCH block can be sent when the LBT passes through, the waiting to reach the fixed positions is not needed, and the communication delay can be further reduced to a certain extent. In addition, because the current RMSI CORESET may not support the cross-slot scheduling system information, in the first mode, when the remaining symbols in the current slot are insufficient, the second system information is completely transmitted in the next slot, so that the problem that the second system information cannot be accurately demodulated because the RMSI CORESET does not support the cross-slot scheduling system information can be solved.

The second method comprises the following steps: the arbitrary one DRS may be transmitted using a seventh pattern. In the seventh pattern, N symbols occupied by the synchronization signal block are located after M symbols occupied by the control information, where N and M are integers greater than 0. Or, in the seventh pattern, N symbols occupied by the synchronization signal block are located before M symbols occupied by the control information.

The DRS at least comprises SS/PBCH block and RMSI CORESET, and the SS/PBCH block and the RMSICORESET cyclically occupy the continuous symbols. In one slot, one or two DRSs (different according to a starting symbol position at the time of transmission) may be transmitted. Further, when DRS is transmitted using the seventh pattern, N symbols occupied by the SS/pbcbhblock of the DRS are located behind M symbols occupied by the RMSI CORESET of the DRS. Or the N symbols occupied by the SS/PBCH block of the DRS are located before the M symbols occupied by the RMSI CORESET of the DRS.

In one example, the present application also provides two seventh patterns. Referring to the pattern shown in fig. 14A, in one slot, according to a start position (possibly caused by LBT) at the time of transmission, a maximum of two DRSs may be included. The structure of the DRS that may be transmitted includes the following situations:

DRS 1: "symbols 0-5", where RMSI CORESET occupies two symbols "0" and "1", SS/PBCHLock occupies four symbols "2-5", or,

DRS 2: symbols "2-7", where SS/PBCH block occupies four symbols "2-5", RMSI CORESET occupies two symbols "6" and "7", or,

DRS 3: the symbols "6-11", where RMSI CORESET occupies both symbols "6" and "7", SS/PBCHLock occupies both symbols "8-11", or,

DRS 4: the symbol "8-13", wherein the SS/PBCH block occupies four symbols of the symbol "8-11", and the RMSICORESET occupies two symbols of the symbol "12" and "13".

Wherein the actual time domain location of the RMSI CORESET may be indicated in the PBCH of the SS/PBCH block

Referring to the pattern shown in fig. 14B, in one slot, according to a start position (possibly caused by LBT) at the time of transmission, a maximum of two DRSs may be included. The structure of the DRS that may be transmitted includes the following situations:

DRS 5: "symbols 0-6", wherein the SS/PBCH block occupies four symbols "0-3", and the RMSI CORESET occupies three symbols "4-6"; alternatively, the first and second electrodes may be,

DRS 6: "symbols 4-10", wherein RMSI CORESET occupies three symbols "4-6", and SS/PBCH block occupies four symbols "7-10"; alternatively, the first and second electrodes may be,

DRS 7: "symbols 7-13", wherein SS/PBCH CORESET occupies four symbols "7-10" and SS/PBCHLock occupies three symbols "11-13".

Referring to the pattern shown in fig. 14C, in one slot, according to the starting position (possibly caused by LBT) at the time of transmission, at most two DRSs may be included. The structure of the DRS that may be transmitted includes the following situations:

DRS 8: "symbols 0-6", where SS/PBCH block occupies four symbols "3-6", and RMSI CORESET occupies three symbols "0-2"; alternatively, the first and second electrodes may be,

DRS 9: "symbols 3-9", wherein the RMSI CORESET occupies three symbols "3-6", and the SS/PBCH block occupies four symbols "7-9"; alternatively, the first and second electrodes may be,

DRS 10: "symbols 7-13", wherein SS/PBCH CORESET occupies four symbols "10-13", and SS/PBCHLock occupies three symbols "7-9".

Wherein the actual time domain location of the RMSI CORESET may be indicated in the PBCH of the SS/PBCH block.

Alternatively, in the above-mentioned pattern of the same slot, if there are remaining symbols after transmitting one or more DRSs according to the starting position, it may be used to transmit second system information and/or other information, etc., for example RMSI PDCCH. (see the description of FIG. 15).

In one example, N symbols occupied by the synchronization signal block are located in front of M symbols occupied by the control information, P symbols occupied by the second system information are located behind M symbols occupied by the control information, and P is an integer greater than 0. See fig. 15-15C.

Further, if the number of symbols behind the M symbols occupied by the control information is smaller than P, the second system information of any one DRS occupies a plurality of continuous symbols in other time slots, and the plurality of continuous symbols occupied by the second system information of any one DRS are in the same time slot. See fig. 15-15C.

It should be noted that a general network device may transmit one or more DRSs in 1 slot, for example, DRS1 and DRS3 in fig. 14A before continuous transmission, or DRS2 and DRS4 before continuous transmission. In some scenarios, a network device transmits only one DRS in 1 slot and transmits other information when there are still remaining symbols in the slot. Depending on the time at which the LBT succeeds, the network device may transmit the RMSI CORESET first or the SS/PBCH block first.

As shown in fig. 15A, when LBT succeeds before symbol 0, the network device transmits RMSI CORESET at symbols 0-1 and carries SS/PBCH block at symbols 2-5 (i.e., sends DRS1) using the pattern shown in fig. 14A. Alternatively, the network device may send the second system information, e.g., symbols 6-7, in the remaining symbols after the SS/PBCH block.

When LBT succeeds before symbol 2 (preferably after symbol 0 and before symbol 2), the network device may transmit the SS/PBCH block at symbols 2-5 and the RMSI CORESET at symbols 6-7 (i.e., transmit DRS2), and optionally the network device may transmit second system information at symbols after RMSI CORESET, e.g., symbols 8-13.

When LBT succeeds before symbol 6 (preferably after symbol 2 and before symbol 6), the network device may transmit RMSI CORESET at symbol 6-7 and SS/PBCH block at symbol 8-11 (i.e., transmit DRS3), and optionally the network device may transmit second system information at a symbol after the SS/PBCH block, e.g., symbols 12-13.

When the LBT succeeds before symbol 8 (preferably after symbol 6 and before symbol 8), the network device may transmit the SS/PBCH block at symbols 8-11 and the RMSI CORESET (i.e., send DRS3) at symbols 12-13, when the/slots have no remaining symbols, and the network device may perform a second system information transmission at the other slots. When the same slot has no residual symbol, the network device may transmit second system information in any slot behind the slot, where the second system information may occupy multiple continuous symbols at any position in other slots, for example, symbols 2 to 4 of the next slot. It should be noted that the symbols occupied by the second system information are in the same slot.

As shown in fig. 15B, when LBT succeeds before symbol 0, the network device transmits SS/PBCH block at symbols 0-3 and carries RMSI CORESET (i.e., sends DRS5) at symbols 4-6, using the pattern shown in fig. 14B. Alternatively, the network device may send the second system information, e.g., symbols 7-8, in the remaining symbols after RMSI CORESET.

When LBT succeeds before symbol 4 (preferably after symbol 0 and before symbol 4), the network device may transmit RMSI CORESET at symbols 4-6, and SS/PBCH block at symbols 7-10 (i.e., transmit DRS6), and optionally, the network device may transmit second system information at symbols after the SS/PBCH block, e.g., symbols 11-12.

When the LBT is successful before symbol 7 (preferably after symbol 4 and before symbol 7), the network device may transmit the SS/PBCH block at symbols 7-10 and the RMSI CORESET (i.e., send DRS7) at symbols 11-13, where the slot has no remaining symbols, and the network device may perform a second system information transmission at the other slots. When the same slot has no residual symbol, the network device may transmit second system information in any slot behind the slot, where the second system information may occupy multiple continuous symbols at any position in other slots, for example, symbols 2 to 4 of the next slot. It should be noted that the symbols occupied by the second system information are in the same slot.

As shown in fig. 15C, when LBT succeeds before symbol 0, the network device transmits RMSI CORESET at symbols 0-2 and carries SS/PBCH block at symbols 3-6 (i.e., sends DRS8) using the pattern shown in fig. 14C. Alternatively, the network device may send the second system information, e.g., symbols 8-9, in the remaining symbols after the SS/PBCH block.

When LBT succeeds before symbol 3 (preferably after symbol 2 and before symbol 6), the network device may transmit the SS/PBCH block at symbols 3-6 and the RMSI CORESET at symbols 7-9 (i.e., transmit DRS9), and optionally the network device may transmit second system information at symbols after the RMSI CORESET, e.g., symbols 10-11.

When the LBT succeeds before symbol 7, the network device may transmit RMSI CORESET at symbols 7-9 and SS/PBCH block at symbols 10-13 (i.e., send DRS10), where the i slots have no remaining symbols, and the network device may perform a second system information transmission at the other slots. When the same slot has no residual symbol, the network device may transmit second system information in any slot behind the slot, where the second system information may occupy multiple continuous symbols at any position in other slots, for example, symbols 2 to 4 of the next slot. It should be noted that the symbols occupied by the second system information are in the same slot.

In the second mode, when the network device sends the DRS, the network device may determine the position of sending the SS/PBCH block first, and may send the DRS before the SS/PBCH block or after the SS/PBCH block when sending the RMSI CORESET, and compared with the case where the RMSI CORESET is only sent before the SS/PBCH block, the second mode may select to send the DRS before the SS/PBCH block or after the SS/PBCH block according to the position of the symbol to be sent, so that the flexibility of sending the RMSI CORESET and the SS/PBCH block may be improved, the resource utilization rate may be provided, and the communication delay may be reduced to a certain extent. In addition, because the current RMSI CORESET may not support the cross-slot scheduling system information, in the first mode, when the remaining symbols in the current slot are insufficient, the second system information is completely transmitted in the next slot, so that the problem that the second system information cannot be accurately demodulated because the RMSI CORESET does not support the cross-slot scheduling system information can be solved.

In the first and second manners, if the remaining resources in the current slot are insufficient and the second system information is completely transmitted in the next slot, the bandwidth used for carrying the symbol of the synchronization signal may be filled with other downlink signals in the DRS, that is, the idle resource blocks in the symbol used for carrying the synchronization signal are filled with the other downlink signals in the DRS. Alternatively, the repeated SS/PBCH block may fill a bandwidth of the symbol used for carrying the synchronization signal, that is, the repeated SS/PBCH block fills a free resource block in the symbol used for carrying the synchronization signal.

The embodiment of the present application provides a communication apparatus based on the same inventive concept as the method embodiment. The communication apparatus may include a processing unit 1601 and a transceiver unit 1602 as shown in fig. 16.

In an embodiment, the apparatus may be specifically used to implement the method performed by the network device in the embodiments described in fig. 4 to fig. 15C, where the device may be the network device itself, or may be a chip or a chip set in the network device, or a part of the chip or the chip for performing the function of the related method. The processing unit may be configured to perform listen before talk, LBT, and then access to a channel. The transmitting unit may be configured to transmit one or more discovery reference signals DRSs to a terminal, where any one of the DRSs is carried on consecutive symbols.

The processing unit and the transceiver unit may also be configured to execute other steps corresponding to the network device in the foregoing method embodiment, which may specifically refer to the foregoing method embodiment, and details are not repeated here.

In another embodiment, the apparatus may be specifically used to implement the method performed by the terminal in the embodiments described in fig. 4 to fig. 15C, and the device may be the terminal itself, or may also be a chip or a chip set in the terminal, or a part of the chip or the chip for performing the function of the related method. The transceiver unit may be configured to receive one or more discovery reference signals DRSs from a network device under the control of the processing unit, where any one of the DRSs is carried on consecutive symbols.

The processing unit and the transceiver unit may also be configured to execute other steps corresponding to the terminal in the foregoing method embodiment, and reference may be specifically made to the foregoing method embodiment, which is not described herein again.

The division of the modules in the embodiments of the present application is schematic, and only one logical function division is provided, and in actual implementation, there may be another division manner, and in addition, each functional module in each embodiment of the present application may be integrated in one processor, may also exist alone physically, or may also be integrated in one module by two or more modules. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

When the integrated module can be implemented in the form of hardware, the communication device may be as shown in fig. 17, and the communication device may be a network device or a chip in the network device. The communication means may also be a terminal or a chip in a terminal. The communication device may include a processor 1701, a communication interface 1702, and a memory 1703. Among other things, the processing unit 1601 may be a processor 1701. The transmitting unit 1602 may be the communication interface 1702.

The processor 1701 may be a Central Processing Unit (CPU), or a digital processing module, etc. The communication interface 1702 may be a transceiver, an interface circuit such as a transceiver circuit, etc., a transceiver chip, etc. The communication device further includes: a memory 1703 for storing programs executed by the processor 1702. The memory 1703 may be a nonvolatile memory such as a Hard Disk Drive (HDD) or a solid-state drive (SSD), and may also be a volatile memory (RAM), for example, a random-access memory (RAM). The memory 1703 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such.

The processor 1701 is configured to execute the program codes stored in the memory 1703, and is specifically configured to execute the operations of the processing unit 1601, which are not described herein again.

The embodiment of the present application does not limit the specific connection medium among the communication interface 1701, the processor 1702 and the memory 1703. In the embodiment of the present application, the memory 1703, the processor 1702, and the communication interface 1701 are connected by the bus 1704 in fig. 17, the bus is indicated by a thick line in fig. 17, and the connection manner between other components is merely illustrative and not limited. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 17, but this does not mean only one bus or one type of bus.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.

Claims

1. A method for sending discovery reference signals, comprising:

the network equipment performs Listen Before Talk (LBT) and then accesses a channel;

the network equipment sends one or more Discovery Reference Signals (DRSs) to a terminal, wherein any one of the DRSs is carried on continuous symbols.

2. The method of claim 1, wherein the DRS includes at least a synchronization signal block and control information, the control information indicating a time-frequency resource where first system information is located, the first system information being system information indicated by primary system information in the synchronization signal block, the synchronization signal block and control information being carried at predetermined positions in the consecutive symbols.

3. The method of claim 2, wherein any one DRS is transmitted in a first pattern in which N symbols occupied by the synchronization signal block are located after M symbols occupied by the control information, where N and M are integers greater than 0.

4. The method of claim 2, wherein the any one DRS is transmitted in a first pattern in which N symbols occupied by the synchronization signal block precede M symbols occupied by the control information.

5. The method of claim 1, wherein the DRS comprises a synchronization signal block, control information and second system information, the control information indicating a time-frequency resource where first system information is located, the first system information being system information indicated by primary system information in the synchronization signal block, the second system information at least comprising the first system information.

6. The method of claim 5, wherein any one of the DRSs is transmitted using a second pattern in which N symbols occupied by the synchronization signal block are located behind M symbols occupied by the control information, P symbols occupied by the second system information are located behind N symbols occupied by the synchronization signal block, and N, M, and P are integers greater than 0.

7. The method of claim 6, wherein any one of the DRSs is transmitted using a second pattern in which N symbols occupied by the synchronization signal block are located before M symbols occupied by the control information, P symbols occupied by the second system information are located after M symbols occupied by the control information, and P is an integer greater than 0.

8. The method of claim 6 or 7, wherein if the number of symbols after M symbols occupied by the control information is less than P in the same slot, the second system information of any one DRS occupies multiple consecutive symbols in other slots, and the multiple consecutive symbols occupied by the second system information of any one DRS are in the same slot.

9. A method for sending discovery reference signals, comprising:

the terminal receives one or more Discovery Reference Signals (DRSs) from network equipment, wherein any one of the DRSs is carried on continuous symbols.

10. The method of claim 9, wherein the DRS includes at least a synchronization signal block and control information, the control information indicating a time-frequency resource where first system information is located, the first system information being system information indicated by primary system information in the synchronization signal block, the synchronization signal block and control information being carried at predetermined positions in the consecutive symbols.

11. The method of claim 10, wherein any one DRS is transmitted in a first pattern in which N symbols occupied by the synchronization signal block are located after M symbols occupied by the control information, where N and M are integers greater than 0.

12. The method of claim 10, wherein any one DRS is transmitted in a first pattern in which N symbols occupied by the synchronization signal block precede M symbols occupied by the control information.

13. The method of claim 9, wherein the DRS comprises a synchronization signal block, control information and second system information, the control information indicating a time-frequency resource where first system information is located, the first system information being system information indicated by primary system information in the synchronization signal block, the second system information at least comprising the first system information.

14. The method of claim 13, wherein any one DRS is transmitted using a second pattern, in which N symbols occupied by the synchronization signal block are located behind M symbols occupied by the control information, and P symbols occupied by the second system information are located behind N symbols occupied by the synchronization signal block, where N, M, and P are integers greater than 0.

15. The method of claim 14, wherein any one DRS is transmitted using a second pattern in which N symbols occupied by the synchronization signal block are located before M symbols occupied by the control information, P symbols occupied by the second system information are located after M symbols occupied by the control information, and P is an integer greater than 0.

16. The method of claim 14 or 15, wherein if the number of symbols after M symbols occupied by the control information is less than P in the same slot, the second system information of any one DRS occupies multiple consecutive symbols in other slots, and the multiple consecutive symbols occupied by the second system information of any one DRS are in the same slot.

17. A discovery reference signal transmission apparatus, comprising:

a processing unit, configured to perform listen before talk LBT and then access to a channel;

a transceiving unit, configured to send one or more discovery reference signals DRSs to a terminal, where any one of the DRSs is carried on consecutive symbols.

18. The method of claim 17, wherein the DRS comprises at least a synchronization signal block and control information, the control information indicating a time-frequency resource where first system information is located, the first system information being system information indicated by primary system information in the synchronization signal block, the synchronization signal block and control information being carried at predetermined positions in the consecutive symbols.

19. The method of claim 18, wherein any one DRS is transmitted in a first pattern in which N symbols occupied by the synchronization signal block are located after M symbols occupied by the control information, where N and M are integers greater than 0.

20. The method of claim 18, wherein any one DRS is transmitted in a first pattern in which N symbols occupied by the synchronization signal block precede M symbols occupied by the control information.

21. The method of claim 17, wherein the DRS comprises a synchronization signal block, control information and second system information, the control information indicating a time-frequency resource where first system information is located, the first system information being system information indicated by primary system information in the synchronization signal block, the second system information comprising at least the first system information.

22. The method of claim 21, wherein any one DRS is transmitted using a second pattern in which N symbols occupied by the synchronization signal block are located after M symbols occupied by the control information, P symbols occupied by the second system information are located after N symbols occupied by the synchronization signal block, and N, M, and P are integers greater than 0.

23. The method of claim 22, wherein any one DRS is transmitted using a second pattern in which N symbols occupied by the synchronization signal block are located before M symbols occupied by the control information, P symbols occupied by the second system information are located after M symbols occupied by the control information, and P is an integer greater than 0.

24. The method of claim 22 or 23, wherein if the number of symbols after M symbols occupied by the control information is less than P in the same slot, the second system information of any one DRS occupies multiple consecutive symbols in other slots, and the multiple consecutive symbols occupied by the second system information of any one DRS are in the same slot.

25. A method for sending discovery reference signals, comprising: a processing unit and a transceiver unit;

the transceiver unit is configured to receive, under control of the processing unit, one or more discovery reference signals DRSs from a network device, where any one of the DRSs is carried on consecutive symbols.

26. The method of claim 25, wherein the DRS comprises at least a synchronization signal block and control information, the control information indicating a time-frequency resource where first system information is located, the first system information being system information indicated by primary system information in the synchronization signal block, the synchronization signal block and control information being carried at predetermined positions in the consecutive symbols.

27. The method of claim 26, wherein any one DRS is transmitted in a first pattern in which N symbols occupied by the synchronization signal block are located after M symbols occupied by the control information, where N and M are integers greater than 0.

28. The method of claim 26, wherein any one DRS is transmitted in a first pattern in which N symbols occupied by the synchronization signal block precede M symbols occupied by the control information.

29. The method of claim 25, wherein the DRS comprises a synchronization signal block, control information and second system information, the control information indicating a time-frequency resource where first system information is located, the first system information being system information indicated by primary system information in the synchronization signal block, the second system information comprising at least the first system information.

30. The method of claim 29, wherein any one DRS is transmitted using a second pattern in which N symbols occupied by the synchronization signal block are located after M symbols occupied by the control information, P symbols occupied by the second system information are located after N symbols occupied by the synchronization signal block, and N, M, and P are integers greater than 0.

31. The method of claim 30, wherein any one DRS is transmitted using a second pattern in which N symbols occupied by the synchronization signal block are located before M symbols occupied by the control information, P symbols occupied by the second system information are located after M symbols occupied by the control information, and P is an integer greater than 0.

32. The method of claim 30 or 31, wherein if the number of symbols after M symbols occupied by the control information is less than P in the same slot, the second system information of any one DRS occupies multiple consecutive symbols in other slots, and the multiple consecutive symbols occupied by the second system information of any one DRS are in the same slot.

33. A computer-readable storage medium, in which a program is stored, which when read and executed by one or more processors, implements the method of any one of claims 1 to 8;

alternatively, the program when read and executed by one or more processors may implement the method of any one of claims 9 to 16.