CN110969684A

CN110969684A - Multi-phase architecture for multi-rate pixel shading

Info

Publication number: CN110969684A
Application number: CN201910795166.XA
Authority: CN
Inventors: S.迈于兰; P.瑟蒂; A.R.阿普; E.霍克斯特拉
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2018-09-27
Filing date: 2019-08-27
Publication date: 2020-04-07
Also published as: DE102019124705A1; US20200104967A1; US10621689B1

Abstract

Embodiments are generally directed to a multi-phase architecture for multi-rate pixel shading. An embodiment of an apparatus includes one or more processor cores including a graphics pipeline and a memory to store data for graphics processing, the data including pixel data. The graphics pipeline includes a multi-phase shader for processing pixel data, the multi-phase shader including a plurality of rendering stages, the rendering stages including at least a first stage for a first granularity and a second stage for a second, different granularity, the second rendering granularity being a finer granularity than the first rendering granularity. The multi-phase shader is configured to provide a hierarchy for image rendering, where pixel data is received at a rendering stage having a coarsest rendering granularity, where remaining pixel data is provided through the hierarchy to one or more rendering stages having finer rendering granularities.

Description

Multi-phase architecture for multi-rate pixel shading

Technical Field

Embodiments described herein relate generally to the field of electronic devices, and more particularly, to a multi-phase architecture for multi-rate pixel shading.

Background

In computer graphics, the trend toward higher resolution rendering of graphical images may provide users with an improved experience in various types of systems, including advanced games and virtual reality. There is a need to provide high resolution rendering in a system with limited performance and power budget to achieve reasonable frame rates.

Multi-rate coloring of pixel data is an option that helps address performance and power limitations for high-resolution rendering by enabling coloring at different granularities of pixel data. In multi-rate rendering, it is possible to maintain rendering at a lower rate and limit the higher resolution to areas where higher resolution is needed.

However, it is challenging to provide efficient multi-rate resolution for the shading operation. In particular, a single monolithic shader (shader) may provide support for the looping of certain inlcles in operation, but such inlcles are separated according to a particular granularity for rendering, which thus limits the efficiency of the shader.

Drawings

The embodiments described herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

FIG. 1 is a block diagram of a processing system according to some embodiments;

FIG. 2 is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor;

FIG. 3 is a block diagram of a graphics processor according to some embodiments;

FIG. 4 is a block diagram of a graphics processing engine of a graphics processor, according to some embodiments;

FIG. 5 is a block diagram of hardware logic of a graphics processor core, according to some embodiments;

6A-6B illustrate thread execution logic including an array of processing elements employed in a graphics processor core in accordance with some embodiments;

FIG. 7 is a block diagram illustrating a graphics processor instruction format, according to some embodiments;

FIG. 8 is a block diagram of another embodiment of a graphics processor;

FIG. 9A is a block diagram illustrating a graphics processor command format, according to some embodiments;

FIG. 9B is a block diagram illustrating a graphics processor command sequence, according to an embodiment;

FIG. 10 illustrates an exemplary graphics software architecture for a data processing system, in accordance with some embodiments;

FIG. 11A is a block diagram illustrating an IP core development system that may be used to fabricate integrated circuits to perform operations according to an embodiment;

figure 11B illustrates a cross-sectional side view of an integrated circuit package assembly, in accordance with some embodiments;

FIG. 12 is a block diagram illustrating an exemplary system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment;

FIG. 13A illustrates an exemplary graphics processor of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment;

FIG. 13B illustrates an additional exemplary graphics processor of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment;

FIG. 14A illustrates a graphics core that may be included within a graphics processor, in accordance with some embodiments;

FIG. 14B illustrates a highly parallel general purpose graphics processing unit suitable for deployment on a multi-chip module, in accordance with some embodiments;

FIG. 15 is an illustration of a processing system including a multi-phase shader to provide improved operating efficiency, according to some embodiments;

FIG. 16 is an illustration of a multi-phase shader, according to some embodiments;

FIG. 17 is a diagram of a device or system including a multi-phase shader;

FIG. 18 is an illustration of pixel granularity in a system to provide multi-phase shading according to some embodiments; and

FIG. 19 is a flow diagram to illustrate a process for multi-phase shading for image rendering, according to some embodiments.

Detailed Description

Embodiments described herein are generally directed to a multi-phase architecture for multi-rate pixel rendering.

In multi-rate rendering of pixel data, there are a number of different rates or granularities at which screen space segments may be rendered. For example, a particular system may include three shading rates, where each shading rate has a particular granularity. In this example, the shading granularity for the pixel data may be coarse pixels (which may also be referred to herein as "coarse"), pixels, and samples. Multi-rate shading allows shading to be maintained for specific purposes, typically at the coarsest allowable granularity (such as coarse pixels), and only increased to finer levels of granularity (such as to pixel or sample granularity) when such improved quality is required. For example, for image rendering inside a triangle, a coarse pixel or pixel rate may generally be applied, while at the edges of the triangle, where a greater resolution would be preferred due to the visual impact of the coarse resolution in that area, a pixel or sample rate may instead be applied.

In conventional systems, the multi-rate shader may be implemented as a single monolithic shader, providing each of the supported granularities. However, monolithic shader architectures for pixel data shading limit the operating efficiency of the shader. In such monolithic architectures, the shader does not allow the inner loop to be assembled across instances of calls. As such, monolithic multi-rate shaders will generally not allow efficient packing for SIMD (single instruction multiple data) computations.

In some embodiments, multi-rate shading is applied in a device, system, or process utilizing a multi-phase shader architecture. In some embodiments, a multi-phase shader architecture provides a hierarchy of pixel shading in multiple rendering stages (stages), where data is received at the stage for the coarsest rendering granularity and the remaining data is passed to one or more stages that utilize finer rendering granularity. In contrast to previous implementations of monolithic shaders, the multi-phase architecture may provide improved efficiency by allowing pixel data to be redistributed between phases (phases) for packing (pack) lines (lanes) for SIMD computations, allowing for increased efficiency in SIMD computing operations.

Conventional monolithic shaders are not able to combine efficiently across granularity. In an example, SIMD16 (SIMD with 16 data lanes (lines)) coarse rate dispatch from a monolithic shader would only be allowed inner loops from those groups of 16 coarse pixels. In some embodiments, the multi-phase shader instead allows the reassembly of pixels and samples to efficiently utilize SIMD width and thereby increase shading efficiency in a device or system.

Overview of the System

Fig. 1 is a block diagram of a processing system 100 according to an embodiment. In various embodiments, system 100 includes one or more processors 102 and one or more graphics processors 108, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

In one embodiment, the system 100 may comprise or be incorporated within a server-based gaming platform, gaming console, including a gaming and media console, mobile gaming console, handheld gaming console, or online gaming console. In some embodiments, system 100 is a mobile phone, smart phone, tablet computing device, or mobile internet device. The processing system 100 may also include, be coupled with, or integrated within a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In some embodiments, processing system 100 is a television or set-top box device having one or more processors 102 and a graphical interface generated by one or more graphics processors 108.

In some embodiments, the one or more processors 102 each include one or more processor cores 107 to process instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 107 is configured to process a particular instruction set 109. In some embodiments, the instruction set 109 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via Very Long Instruction Words (VLIW). The multiple processor cores 107 may each process a different instruction set 109, which different instruction set 109 may include instructions to facilitate emulation of other instruction sets. Processor core 107 may also include other processing devices such as a Digital Signal Processor (DSP).

In some embodiments, processor 102 includes cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a level 3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among the processor cores 107 using known cache coherency techniques. The register file 106 is additionally included in the processor 102, which processor 102 may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

In some embodiments, processor(s) 102 are coupled to one or more interface buses 110 to transmit communication signals, such as address, data, or control signals, between processor 102 and other components in system 100. In one embodiment, interface bus 110 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus, and may include one or more peripheral component interconnect buses (e.g., PCI Express), a memory bus, or other types of interface buses. In one embodiment, processor(s) 102 include an integrated memory controller 116 and a platform controller hub (hub) 130. The memory controller 116 facilitates communication between the memory devices and other components of the system 100, while the Platform Controller Hub (PCH) 130 provides a connection to I/O devices via a local I/O bus.

Memory device 120 may be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable capabilities to act as a process memory. In one embodiment, the memory device 120 may operate as a system memory for the system 100 to store data 122 and instructions 121 for use when the one or more processors 102 execute an application or process. The memory controller 116 is also coupled with an optional external graphics processor 112, which external graphics processor 112 may communicate with the one or more graphics processors 108 in the processor 102 to perform graphics and media operations. In some embodiments, a display device 111 may be connected to the processor(s) 102. Display device 111 may be one or more of an internal display device (as in a mobile electronic device or laptop) or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, display device 111 may be a Head Mounted Display (HMD), such as a stereoscopic display device for use in Virtual Reality (VR) applications or Augmented Reality (AR) applications.

In some embodiments, platform controller hub 130 enables peripherals to connect to memory device 120 and processor 102 via a high speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, a data storage device 124 (e.g., hard drive, flash memory, etc.). Data storage device 124 may be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI express). The touch sensor 125 may include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 may be a Wi-Fi transceiver, a bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. The firmware interface 128 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). Network controller 134 may enable a network connection to a wired network. In some embodiments, a high performance network controller (not shown) is coupled to interface bus 110. In one embodiment, audio controller 146 is a multi-channel high definition audio controller. In one embodiment, system 100 includes an optional legacy I/O controller 140 for coupling legacy (e.g., personal System 2 (PS/2)) devices to the system. The platform controller hub 130 may also be connected to one or more Universal Serial Bus (USB) controllers 142 that connect input devices, such as a keyboard and mouse 143 combination, a camera 144, or other USB input devices.

It will be appreciated that the system 100 shown is exemplary and not limiting, as other types of data processing systems configured differently may also be used. For example, the instances of memory controller 116 and platform controller hub 130 may be integrated into a separate external graphics processor (such as external graphics processor 112). In one embodiment, platform controller hub 130 and/or memory controller 116 may be external to the one or more processors 102. For example, system 100 may include external memory controller 116 and platform controller hub 130, which external memory controller 116 and platform controller hub 130 may be configured as a memory controller hub and a peripheral controller hub within a system chipset in communication with processor(s) 102.

FIG. 2 is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. Those elements of fig. 2 having the same reference numbers (or names) as the elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Processor 200 may include additional cores up to and including additional core 202N, represented by the dashed box. Each of the processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core is also capable of accessing one or more shared cache units 206.

Internal cache units 204A-204N and shared cache unit 206 represent cache memory levels within processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, with the highest level of cache preceding the external memory being classified as an LLC. In some embodiments, cache coherency logic maintains coherency between the various cache molecules 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI buses or PCI express buses. The system agent core 210 provides management functionality for various processor components. In some embodiments, the system proxy core 210 includes one or more integrated memory controllers 214 to manage access to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 202A-202N include support for simultaneous multithreading. In such an embodiment, the system proxy core 210 includes components for coordinating and operating the cores 202A-202N during multi-threaded processing. The system proxy core 210 may additionally include a Power Control Unit (PCU) that includes logic and components to regulate the power states of the processor cores 202A-202N and the graphics processor 208.

In some embodiments, the processor 200 additionally includes a graphics processor 208 to perform graphics processing operations. In some embodiments, the graphics processor 208 is coupled with the set of shared cache units 206 and a system proxy core 210 that includes the one or more integrated memory controllers 214. In some embodiments, the system agent core 210 also includes a display controller 211 to drive graphics processor output to one or more coupled displays. In some embodiments, the display controller 211 may also be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor 208.

In some embodiments, ring-based interconnect unit 212 is used to couple internal components of processor 200. However, alternative interconnect elements may be used, such as point-to-point interconnects, switched interconnects, or other techniques, including techniques known in the art. In some embodiments, the graphics processor 208 is coupled with the ring interconnect 212 via an I/O link 213.

The exemplary I/O link 213 represents at least one of a variety of I/O interconnects, including on-package I/O interconnects that facilitate communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and the graphics processor 208 use the embedded memory module 218 as a shared last level cache.

In some embodiments, processor cores 202A-202N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 202A-202N are heterogeneous in Instruction Set Architecture (ISA), wherein one or more of processor cores 202A-202N execute a first instruction set and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 202A-202N are heterogeneous in micro-architecture, with one or more cores having relatively higher power consumption coupled with one or more power cores having lower power consumption. Further, processor 200 may be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, among other components.

Fig. 3 is a block diagram of a graphics processor 300, which graphics processor 300 may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores. In some embodiments, a graphics processor communicates via a memory-mapped I/O interface to registers on the graphics processor and with commands placed into processor memory. In some embodiments, graphics processor 300 includes a memory interface 314 to access memory. Memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and/or system memory.

In some embodiments, graphics processor 300 also includes a display controller 302 to drive display output data to a display device 320. The display controller 302 includes hardware for one or more overlay planes for display and composition of multi-layer video or user interface elements. The display device 320 may be an internal or external display device. In one embodiment, display device 320 is a head mounted display device, such as a Virtual Reality (VR) display device or an Augmented Reality (AR) display device. In some embodiments, graphics processor 300 includes a video codec engine 306 to encode, decode, or transcode media into, from, or between one or more media encoding formats, including but not limited to: motion Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, and Society of Motion Picture and Television Engineers (SMPTE) 421M/VC-1, as well as Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 to perform two-dimensional (2D) rasterization operations, including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a Graphics Processing Engine (GPE) 310. In some embodiments, GPE 310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

In some embodiments, the GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive (primary) shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 312 includes programmable and fixed function elements that perform various tasks within the elements and/or spawn (spawn) execution threads to the 3D/media subsystem 315. Although the 3D pipeline 312 may be used to perform media operations, embodiments of the GPE 310 also include a media pipeline 316 that is particularly used to perform media operations, such as video post-processing and image enhancement.

In some embodiments, the media pipeline 316 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video de-interlacing, and video encoding acceleration, in place of or on behalf of the video codec engine 306. In some embodiments, media pipeline 316 additionally includes a thread generation unit to generate threads for execution on 3D/media subsystem 315. The spawned threads perform computations for media operations on one or more graphics execution units included in 3D/media subsystem 315.

In some embodiments, 3D/media subsystem 315 includes logic for executing threads produced by 3D pipeline 312 and media pipeline 316. In one embodiment, the pipeline sends thread execution requests to the 3D/media subsystem 315, and the 3D/media subsystem 315 includes thread dispatch logic for arbitrating various requests and dispatching them to available thread execution resources. The execution resources include an array of graphics execution units to process 3D and media threads. In some embodiments, 3D/media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem further includes a shared memory including registers and addressable memory to share data between the threads and to store output data.

Graphics processing engine

FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor, according to some embodiments. In one embodiment, Graphics Processing Engine (GPE) 410 is a version of GPE 310 shown in FIG. 3. Elements of fig. 4 having the same reference numbers (or names) as elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline 312 and the media pipeline 316 of fig. 3 are illustrated. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, and in at least one embodiment, a separate media and/or image processor is coupled to GPE 410.

In some embodiments, GPE 410 is coupled with a command streamer 403 or includes command streamer 403, which command streamer 403 provides a command stream to 3D pipeline 312 and/or media pipeline 316. In some embodiments, command streamer 403 is coupled with a memory, which may be a system memory, or one or more of an internal cache and a shared cache. In some embodiments, command streamer 403 receives commands from memory and sends the commands to 3D pipeline 312 and/or media pipeline 316. The commands are instructions fetched from a ring buffer that stores the commands for the 3D pipeline 312 and the media pipeline 316. In one embodiment, the ring buffer may additionally include a batch command buffer that stores multiple batches of multiple commands. The commands for 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 312 and/or image data and memory objects for media pipeline 316. The 3D pipeline 312 and the media pipeline 316 process the commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 414. In one embodiment, graphics core array 414 includes one or more blocks of graphics cores (e.g., graphics core(s) 415A, graphics core(s) 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources including general purpose and graphics specific execution logic to perform graphics and computational operations, and fixed function texture processing and/or machine learning and artificial intelligence acceleration logic.

In various embodiments, 3D pipeline 312 includes fixed function and programmable logic to process one or more shader programs, such as a vertex shader, a geometry shader, a pixel shader, a fragment shader, a compute shader, or other shader programs, by processing instructions and dispatching execution threads to graphics core array 414. Graphics core array 414 provides a uniform block of execution resources for use in processing these shader programs. Multipurpose execution logic (e.g., execution units) within graphics core(s) 415A-415B of graphics core array 414 includes support for various 3D API shader languages and may execute multiple simultaneous execution threads associated with multiple shaders.

In some embodiments, graphics core array 414 also includes execution logic to perform media functions, such as video and/or image processing. In one embodiment, the execution unit additionally includes general purpose logic that is programmable to perform parallel general purpose computing operations in addition to graphics processing operations. The general purpose logic may perform processing operations in parallel or in conjunction with the processor core(s) 107 of FIG. 1 or general purpose logic within cores 202A-202N in FIG. 2.

Output data generated by threads executing on graphics core array 414 may output the data to memory in Unified Return Buffer (URB) 418. The URB 418 may store data for multiple threads. In some embodiments, the URB 418 may be used to send data between different threads executing on the graphics core array 414. In some embodiments, the URB 418 may additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic 420.

In some embodiments, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 410. In one embodiment, the execution resources are dynamically extensible such that the execution resources may be enabled or disabled as needed.

Graphics core array 414 is coupled to shared function logic 420, where shared function logic 420 includes a plurality of resources shared between graphics cores in the graphics core array. The shared function within shared function logic 420 is a hardware logic unit that provides specialized supplemental functionality to graphics core array 414. In various embodiments, shared function logic 420 includes, but is not limited to, sampler 421, math 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 within shared function logic 420.

Shared functionality is implemented where the need for a given specialized functionality is insufficient to be included within graphics core array 414. Instead, a single instantiation of the specialized function is implemented as a separate entity in the shared function logic 420 and is shared between execution resources within the graphics core array 414. The exact set of functions shared between graphics core array 414 and included within graphics core array 414 varies across embodiments. In some embodiments, a particular shared function within shared function logic 420 that is widely used by graphics core array 414 may be included within shared function logic 416 within graphics core array 414. In various embodiments, shared function logic 416 within graphics core array 414 may include some or all of the logic within shared function logic 420. In one embodiment, all logic elements within shared function logic 420 may be replicated within shared function logic 416 of graphics core array 414. In one embodiment, shared function logic 420 is not included in support of shared function logic 416 within graphics core array 414.

Figure 5 is a block diagram of hardware logic of graphics processor core 500 according to some embodiments described herein. Elements of fig. 5 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. In some embodiments, the illustrated graphics processor core 500 is included within the graphics core array 414 of fig. 4. Graphics processor core 500 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. Graphics processor core 500 is an example of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on a target power and performance envelope. Each graphics core 500 may include a fixed function block 530 coupled to a plurality of sub-cores 501A-501F (also referred to as sub-slices), the plurality of sub-cores 501A-501F comprising modular blocks of general and fixed function logic.

In some embodiments, the fixed function block 530 includes a geometry/fixed function pipeline 536, such as in lower performance and/or lower power graphics processor implementations, the geometry/fixed function pipeline 536 may be shared by all of the sub-cores in the graphics processor 500. In various embodiments, geometry/fixed function pipeline 536 includes a 3D fixed function pipeline (e.g., 3D pipeline 312 as in fig. 3 and 4), a video front end unit, a thread producer and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer such as unified return buffer 418 of fig. 4.

In one embodiment, fixed function block 530 also includes a graphics SoC interface 537, a graphics microcontroller 538, and a media pipeline 539. Graphics SoC interface 537 provides an interface between graphics core 500 and other processor cores within the system-on-a-chip integrated circuit. The graphics microcontroller 538 is a programmable sub-processor that is configurable to manage various functions of the graphics processor 500, including thread dispatch, scheduling, and preemption. Media pipeline 539 (e.g., media pipeline 316 of fig. 3 and 4) includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. The media pipeline 539 implements media operations via requests to compute or sample logic within the sub-cores 501A-501F.

In one embodiment, SoC interface 537 enables graphics core 500 to communicate with a general-purpose application processor core (e.g., CPU) and/or other components within the SoC, including memory hierarchy elements such as a shared last level cache, system RAM, and/or embedded on-chip or on-package DRAM. SoC interface 537 may also enable communication with fixed-function devices within the SoC (such as camera imaging pipelines), and enable use and/or implementation of global memory atoms that may be shared between graphics core 500 and CPUs within the SoC. SoC interface 537 may also implement power management control for graphics core 500 and enable interfaces between the clock domain of graphics core 500 and other clock domains within the SoC. In one embodiment, SoC interface 537 enables receipt of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. The commands and instructions may be dispatched to the media pipeline 539 when media operations are to be performed, or to the geometry and fixed function pipelines (e.g., the geometry and fixed function pipeline 536, the geometry and fixed function pipeline 514) when graphics processing operations are to be performed.

Graphics microcontroller 538 may be configured to perform various scheduling and management tasks for graphics core 500. In one embodiment, the graphics microcontroller 538 may perform graphics and/or compute workload scheduling on various graphics parallel engines within the Execution Unit (EU) arrays 502A-502F, 504A-504F within the sub-cores 501A-501F. In this scheduling model, host software executing on a CPU core of an SoC including graphics core 500 may submit a workload of one of a plurality of graphics processor doorbell invoking a scheduled operation on an appropriate graphics engine. The scheduling operation includes determining which workload to run next, submitting the workload to a command streamer, preempting an existing workload running on an engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In one embodiment, graphics microcontroller 538 may also facilitate a low power or idle state for graphics core 500, providing graphics core 500 with the ability to save and restore registers within graphics core 500 across low power state transitions independent of the operating system and/or graphics driver software on the system.

Graphics core 500 may have more or fewer sub-cores than the illustrated sub-cores 501A-501F, up toNA modular sub-core. For each groupNThe graphics core 500 may also include shared function logic 510, shared and/or cache memory 512, geometry/fixed function pipeline 514, and additional fixed function logic 516 to accelerate various graphics and computing processing operations. Shared function logic 510 may include logic units associated with shared function logic 420 of FIG. 4 (e.g., samplers, math and/or inter-thread communication logic), which may be provided by each of graphics cores 500NAnd sharing the sub-cores. Shared and/or cache memory 512 may be for the set within graphics core 500NThe last level cache of the individual sub-cores 501A-501F and may also serve as a shared memory accessible by multiple sub-cores. The geometry/fixed function pipeline 514 may be included in place of the geometry/fixed function pipeline 536 within the fixed function block 530 and may include the same or similar logic elements.

In one embodiment, graphics core 500 includes additional fixed function logic 516, which additional fixed function logic 516 may include various fixed function acceleration logic for use by graphics core 500. In one embodiment, the additional fixed function logic 516 includes an additional geometry pipeline for use in location-only shading. In position-only shading, there are two geometry pipelines — a full geometry pipeline within the geometry/

fixed function pipelines

516, 536, and a culling (fill) pipeline, which is an additional geometry pipeline that may be included within the additional fixed function logic 516. In one embodiment, the culling pipeline is a pruned version of the full geometry pipeline. The full pipeline and the culling pipeline may execute different instances of the same application, each instance having a separate context. Location-only shading may hide long culling runs of discarded triangles so that shading can be done earlier in some instances. For example, and in one embodiment, the culling pipeline logic within the additional fixed function logic 516 may execute the position shader in parallel with the host application and generally generate critical results faster than a full pipeline, because the culling pipeline only fetches and colors the position attributes of vertices, and does not perform pixel-to-frame buffer rasterization and rendering. The culling pipeline may use the generated key results to calculate visibility information for all triangles regardless of whether those triangles were culled. The full pipeline (which may be referred to as a playback pipeline in this example) may consume visibility information to skip culled triangles to render only visible triangles that are ultimately passed to the rasterization stage.

In one embodiment, the additional fixed function logic 516 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementations that include optimization for machine learning training or reasoning.

Within each graphics sub-core 501A-501F is included a set of execution resources that may be used to perform graphics, media, and computational operations in response to requests by a graphics pipeline, media pipeline, or shader program. The graphics sub-cores 501A-501F include a plurality of EU arrays 502A-502F, 504A-504F, thread dispatch and inter-thread communication (TD/IC) logic 503A-503F, 3D (e.g., texture) samplers 505A-505F, media samplers 506A-506F, shader processors 507A-507F, and Shared Local Memories (SLM) 508A-508F. The EU arrays 502A-502F, 504A-504F each include a plurality of execution units, which are general purpose graphics processing units capable of performing floating point and integer/fixed point logic operations in the services of graphics, media, or computational operations, including graphics, media, or compute shader programs. The TD/IC logic 503A-503F performs local thread dispatch and thread control operations for execution units within the sub-cores and facilitates communication between threads executing on execution units within the sub-cores. The 3D samplers 505A-505F may read texture or other 3D graphics related data into memory. The 3D sampler may read texture data differently based on the configured sample states and texture formats associated with a given texture. Media samplers 506A-506F may perform similar read operations based on the type and format associated with the media data. In one embodiment, each graphics sub-core 501A-501F may instead include a unified 3D and media sampler. Threads executing on execution units within each of the sub-cores 501A-501F may utilize shared local memory 508A-508F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

Execution unit

6A-6B illustrate thread execution logic 600 including an array of processing elements employed in a graphics processor core according to embodiments described herein. Elements of fig. 6A-6B having the same reference numbers (or names) as elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Fig. 6A illustrates an overview of thread execution logic 600, which thread execution logic 600 may include variations of the hardware logic illustrated with each of the sub-cores 501A-501F of fig. 5. FIG. 6B illustrates exemplary internal details of an execution unit.

As illustrated in fig. 6A, in some embodiments, thread execution logic 600 includes shader processor 602, thread dispatcher 604, instruction cache 606, an extensible execution unit array including a plurality of execution units 608A-608N, sampler 610, data cache 612, and data port 614. In one embodiment, the scalable execution unit array may be dynamically scalable by enabling or disabling one or more execution units (e.g., any of

execution units

608A, 608B, 608C, 608D through 608N-1, and 608N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect fabric that is linked to each of the components. In some embodiments, the thread execution logic 600 includes one or more connections to memory, such as system memory or cache memory, through one or more of the instruction cache 606, data port 614, sampler 610, and execution units 608A-608N. In some embodiments, each execution unit (e.g., 608A) is an independent programmable general purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 608A-608N may be expanded to include any number of individual execution units.

In some embodiments, the execution units 608A-608N are primarily used to execute shader programs. Shader processor 602 can process various shader programs and dispatch threads of execution associated with the shader programs via thread dispatcher 604. In one embodiment, the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and to instantiate the requested thread on one or more of the execution units 608A-608N. For example, a geometry pipeline may assign vertices, tessellations (tessellation), or geometry shaders to thread execution logic for processing. In some embodiments, the thread dispatcher 604 may also process runtime thread generation requests from executing shader programs.

In some embodiments, the execution units 608A-608N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct3D and OpenGL) are executed with minimal translation. Execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general purpose processing (e.g., compute and media shaders). Each of the execution units 608A-608N is capable of multi-issue (multi-issue) Single Instruction Multiple Data (SIMD) execution, and multi-threading enables an efficient execution environment when faced with higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high bandwidth register file and associated independent thread state. Execution is multiple issue per clock for pipelines capable of integer, single precision and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations and other miscellaneous operations. While waiting for data from one of the memory or shared functions, dependency logic within the execution units 608A-608N causes the waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, the hardware resources may be devoted to processing other threads. For example, during a delay associated with vertex shader operations, the execution unit may perform the operations for a pixel shader, a fragment shader, or another type of shader program that includes a different vertex shader.

Each of the execution units 608A-608N operates on an array of data elements. The number of data elements is the "execution size" or number of lanes for the instruction. An execution channel is a logical execution unit for data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) used for a particular graphics processor. In some embodiments, execution units 608A-608N support both integer and floating point data types.

The execution unit instruction set includes SIMD instructions. Various data elements may be stored in registers as packed data types, and execution units will process the various elements based on their data sizes. For example, when operating on a 256-bit wide vector, 256 bits of the vector are stored in a register, and the execution unit operates on the vector as four separate 64-bit packed data elements (four word (QW) size data elements), eight separate 32-bit packed data elements (double word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

In one embodiment, one or more execution units may be combined into a fused execution unit 609A-609N, the fused execution unit 609A-609N having thread control logic (607A-607N) common to the fused EUs. Multiple EUs can be fused into EU groups. Each EU in the fused EU set may be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group may vary according to the embodiment. In addition, various SIMD widths may be performed per EU, including but not limited to SIMD8, SIMD16, and SIMD 32. Each fused graphics execution unit 609A-609N includes at least two execution units. For example, the fused execution block 609A includes a first EU 608A, a second EU608B, and thread control logic 607A common to the first EU 608A and the second EU 608B. The thread control logic 607A controls the threads executing on the fused graphics execution unit 609A, allowing each EU within the fused execution units 609A-609N to execute using a common instruction pointer register.

One or more internal instruction caches (e.g., 606) are included in the thread execution logic 600 to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 612) are included to cache thread data during thread execution. In some embodiments, sampler 610 is included to provide texture samples for 3D operations and media samples for media operations. In some embodiments, sampler 610 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 600 via the thread spawn and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 602 is invoked to further compute output information and cause the results to be written to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In some embodiments, a pixel shader or fragment shader computes values for various vertex attributes to be interpolated across rasterized objects. In some embodiments, pixel processor logic within shader processor 602 then executes an Application Programming Interface (API) supplied pixel or fragment shader program. To execute the shader program, shader processor 602 dispatches threads to execution units (e.g., 608A) via thread dispatcher 604. In some embodiments, shader processor 602 uses texture sampling logic in sampler 610 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and the input geometry data calculate pixel color data for each geometric segment, or discard one or more pixels without further processing.

In some embodiments, data port 614 provides a memory access mechanism for thread execution logic 600 to output processed data to memory for further processing on a graphics processor output pipeline. In some embodiments, data port 614 includes or is coupled to one or more cache memories (e.g., data cache 612) to cache data for memory access via the data port.

As illustrated in fig. 6B, the graphics execution unit 608 may include an instruction fetch unit 637, a general register file array (GRF) 624, an architecture register file Array (ARF) 626, a thread arbiter 622, a send unit 630, a branch unit 632, a set of SIMD Floating Point Units (FPUs) 634, and in one embodiment, a set of dedicated integer SIMD ALUs 635. The GRF 624 and ARF 626 include a set of general purpose register files and architectural register files associated with each simultaneous hardware thread that may be active in the graphics execution unit 608. In one embodiment, per-thread architecture state is maintained in the ARF 626, while data used during thread execution is stored in the GRF 624. The execution state of each thread, including the instruction pointer for each thread, may be maintained in thread specific registers in the ARF 626.

In one embodiment, the graphics execution unit 608 has an architecture that is a combination of Simultaneous Multithreading (SMT) and fine-grained Interleaved Multithreading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and a number of registers per execution unit, where execution unit resources are partitioned across logic for executing multiple simultaneous threads.

In one embodiment, the graphics execution unit 608 may issue (co-issue) multiple instructions in conjunction, which may each be a different instruction. The thread arbiter 622 of the graphics execution unit thread 608 may dispatch the instruction to one of the issue unit 630, branch unit 642, or SIMD FPU(s) 634 for execution. Each execution thread may access 128 general purpose registers within the GRF 624, where each register may store 32 bytes, which may be accessed as a SIMD8 element vector of 32-bit data elements. In one embodiment, each execution unit thread is able to access 4 kilobytes within the GRF 624, although embodiments are not so limited and in other embodiments more or less register resources may be provided. In one embodiment, up to seven threads may be executed simultaneously, but the number of threads per execution unit may also vary depending on the embodiment. In an embodiment where seven threads may access 4 kilobytes, the GRF 624 may store a total of 28 kilobytes. The flexible addressing mode may allow registers to be addressed together to efficiently build wider registers or (striped) rectangular block data structures representing strides.

In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via a "send" instruction executed by messaging transmit unit 630. In one embodiment, branch instructions are dispatched to a dedicated branch unit 632 to facilitate SIMD divergence and eventual convergence.

In one embodiment, graphics execution unit 608 includes one or more SIMD floating-point units (FPUs) 634 to perform floating-point operations. In one embodiment, the FPU(s) 634 also support integer computations. In one embodiment, FPU(s) 634 may execute up to SIMDMNumber of 32-bit floating-point (or integer) operations, or SIMD performs up to 2MA 16-bit integer or 16-bit floating point operation. In one embodiment, at least one of the FPU(s) provides extended mathematical capabilities to support high throughput transcendental mathematical functions and double precision 64-bit floating point. In some embodiments, a groupAn 8-bit integer SIMD ALU 635 is also present and may be specifically optimized to perform operations associated with machine learning computations.

In one embodiment, an array of multiple instances of the graphics execution unit 608 may be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, a product architect may select the exact number of execution units per sub-core group. In one embodiment, the execution unit 608 may execute instructions across multiple execution lanes. In another embodiment, each thread executing on the graphics execution unit 608 is executed on a different channel.

FIG. 7 is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in a plurality of formats. The solid box illustrates components typically included in an execution unit instruction, while the dashed line includes components that are optional or included only in a subset of instructions. In some embodiments, the instruction format 700 described and illustrated is a macro-instruction in that they are instructions supplied to the execution units, as opposed to micro-operations that result from instruction decoding once the instruction is processed.

In some embodiments, the graphics processor execution unit natively supports instructions in the 128-bit instruction format 710. Based on the selected instruction, instruction options, and number of operands, a 64-bit packed instruction format 730 may be used for some instructions. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted to being in a 64-bit format 730. The native instructions available in the 64-bit format 730 vary from embodiment to embodiment. In some embodiments, instructions are partially compressed using a set of index values in the index field 713. The execution unit hardware references a set of compression tables based on the index values and uses the compression table outputs to reconstruct native instructions in the 128-bit instruction format 710.

For each format, instruction opcode 712 defines the operation to be performed by the execution unit. An execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texel or a picture element. By default, the execution unit executes each instruction across all data lanes of operands. In some embodiments, instruction control field 714 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel order (e.g., swizzling). For instructions in the 128-bit instruction format 710, the execution size (exec-size) field 716 limits the number of data lanes to be executed in parallel. In some embodiments, the execution size field 716 is not available in the 64-bit compressed instruction format 730.

Some execution unit instructions have up to three operands, including two source operands, src 0720, src 1722, and one destination 718. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implied. The data manipulation instruction may have a third source operand (e.g., SRC 2724), where the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

In some embodiments, 128-bit instruction format 710 includes an access/address mode field 726, the access/address mode field 726 specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When the direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

In some embodiments, 128-bit instruction format 710 includes an access/address mode field 726, the access/address mode field 726 specifying an address mode and/or an access mode for the instruction. In one embodiment, an access pattern is used to define data access alignment for an instruction. Some embodiments support access patterns that include 16 byte aligned access patterns and 1 byte aligned access patterns, where the byte alignment of the access patterns determines the access alignment of instruction operands. For example, when in the first mode, the instruction may use byte aligned addressing for the source and destination operands, and when in the second mode, the instruction may use 16 byte aligned addressing for all of the source and destination operands.

In one embodiment, the address mode portion of the access/address mode field 726 determines whether the instruction is to use direct addressing or indirect addressing. When using the direct register addressing mode, bits in the instruction directly provide the register address of one or more operands. When using the indirect register addressing mode, register addresses for one or more operands may be calculated based on address register values and address immediate fields in the instruction.

In some embodiments, instructions are grouped based on opcode 712 bit fields to simplify opcode decoding 740. For an 8-bit opcode,

bits

4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode packet shown is merely an example. In some embodiments, the move and logic operation group 742 comprises data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic group 742 shares the five Most Significant Bits (MSBs), with the move (mov) instruction in the form of 0000 xxxxxxb and the logic instruction in the form 0001 xxxxb. Flow control instruction set 744 (e.g., call, jump (jmp)) includes instructions in the form 0010 xxxxxxb (e.g., 0x 20). The miscellaneous (miscella) instruction group 746 includes a mix of instructions including synchronous instructions (e.g., wait, send) in the form of 0011 xxxxxxb (e.g., 0x 30). The parallel math instruction group 748 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form 0100 xxxxxxb (e.g., 0x 40). The parallel math group 748 performs arithmetic operations in parallel across the data channels. Vector math group 750 includes arithmetic instructions (e.g., dp 4) in the form 0101xxxxb (e.g., 0x 50). The vector math group performs arithmetic such as dot product calculations on vector operands.

Graphics pipeline

Fig. 8 is a block diagram of another embodiment of a graphics processor 800. Elements of fig. 8 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

In some embodiments, graphics processor 800 includes geometry pipeline 820, media pipeline 830, display engine 840, thread execution logic 850, and render output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor within a multi-core processing system that includes one or more general purpose processing cores. The graphics processor 800 is controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor over the ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general purpose processors. Commands from the ring interconnect 802 are interpreted by a command streamer 803, which command streamer 803 supplies instructions to individual components of either the geometry pipeline 820 or the media pipeline 830.

In some embodiments, command streamer 803 directs the operation of vertex fetcher 805, which vertex fetcher 805 reads vertex data from memory and executes vertex processing commands provided by command streamer 803. In some embodiments, vertex fetcher 805 provides vertex data to vertex shader 807, which vertex shader 807 performs coordinate space transformation and lighting (lighting) operations on each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute vertex processing instructions by dispatching execution threads to execution units 852A-852B via thread dispatcher 831.

In some embodiments, execution units 852A-852B are an array of vector processors having sets of instructions for performing graphics and media operations. In some embodiments, execution units 852A-852B have an attachment L1 cache 851 specific to each array or shared between arrays. The cache may be configured as a data cache, an instruction cache, or a single cache partitioned to contain data and instructions in different partitions.

In some embodiments, geometry pipeline 820 includes a tessellation component to perform hardware accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures tessellation operations. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellator 813 operates in the direction of the hull shader 811 and contains dedicated logic to generate a set of detailed geometric objects based on a coarse geometric model provided as input to the geometry pipeline 820. In some embodiments, if tessellation is not used, tessellation components (e.g., hull shader 811, tessellator 813, and domain shader 817) may be bypassed.

In some embodiments, a complete geometry object may be processed by the geometry shader 819 via one or more threads assigned to the execution units 852A-852B, or may proceed directly to the clipper 829. In some embodiments, the geometry shader operates on all geometry objects rather than vertices or patches of vertices (patches) as in previous stages of the graphics pipeline. If tessellation is disabled, geometry shader 819 receives input from vertex shader 807. In some embodiments, the geometry shader 819 may be programmed by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

Prior to rasterization, the clipper 829 processes the vertex data. The clipper 829 may be a fixed-function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component 873 in the render output pipeline 870 dispatches pixel shaders to convert the geometric objects into a per-pixel representation. In some embodiments, pixel shader logic is included in thread execution logic 850. In some embodiments, the application may bypass the rasterizer and depth test component 873 and access the un-rasterized vertex data via the stream output unit 823.

Graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, the execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) are interconnected via data ports 856 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, sampler 854,

caches

851, 858 and execution units 852A-852B each have separate memory access paths. In one embodiment, texture cache 858 may also be configured as a sampler cache.

In some embodiments, the rendering output pipeline 870 includes a rasterizer and depth test component 873 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower (window)/masker unit to perform fixed function triangle and line rasterization. In some embodiments, an associated render cache 878 and depth cache 879 are also available. The pixel operations component 877 performs pixel-based operations on the data, but in some instances, pixel operations associated with 2D operations (e.g., with blended bit-block image transfers) are performed by the 2D engine 841 or replaced by the display controller 843 when displaying with an overlaid display plane. In some embodiments, shared L3 cache 875 is available to all graphics components, allowing sharing of data without using main system memory.

In some embodiments, graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, video front end 834 receives pipeline commands from command streamer 803. In some embodiments, media pipeline 830 includes a separate command streamer. In some embodiments, the video front end 834 processes media commands before sending the commands to the media engine 837. In some embodiments, media engine 837 includes thread spawning functionality to spawn threads for dispatch to thread execution logic 850 via thread dispatcher 831.

In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, the display engine 840 is external to the processor 800 and is coupled with the graphics processor via the ring interconnect 802 or some other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, the display engine 840 contains dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 843 is coupled with a display device (not shown), which may be a system integrated display device as in a laptop computer or an external display device attached via a display device connector.

In some embodiments, geometry pipeline 820 and media pipeline 830 may be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one Application Programming Interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for an open graphics library (OpenGL), open computing language (OpenCL), and/or Vulkan graphics and computing APIs, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from microsoft corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for an open source computer vision library (OpenCV). If a mapping can be made from the pipeline of a future API having a compatible 3D pipeline to the pipeline of the graphics processor, the future API will also be supported.

Graphics pipeline programming

FIG. 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. FIG. 9B is a block diagram illustrating a graphics processor command sequence 910, according to an embodiment. The solid box in FIG. 9A illustrates components that are typically included in graphics commands, while the dashed lines include components that are optional or included only in a subset of graphics commands. The exemplary graphics processor command format 900 of FIG. 9A includes data fields to identify the client 902, a command operation code (opcode) 904, and data 906 for the command. Subopcode 905 and command size 908 are also included in some commands.

In some embodiments, the client 902 specifies a client unit of the graphics device that processes command data. In some embodiments, the graphics processor command parser examines the client field of each command to adjust the further processing of the command and to route the command data to the appropriate client unit. In some embodiments, a graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes commands. Once the command is received by the client unit, the client unit reads the operation code 904 and, if present, the sub-operation code 905 to determine the operation to be performed. The client unit uses the information in data field 906 to execute the command. For some commands, an explicit command size 908 is desired to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, the commands are aligned via multiples of a doubleword.

The flowchart in FIG. 9B illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to create, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for purposes of example only, as embodiments are not limited to these particular commands or to this command sequence. Further, the commands may be issued as a batch of commands in a sequence of commands such that the graphics processor will process the sequence of commands at least partially simultaneously.

In some embodiments, the graphics processor command sequence 910 may begin with a pipeline flush (flush) command 912 to cause any active graphics pipelines to complete the currently pending commands for that pipeline. In some embodiments, 3D pipeline 922 and media pipeline 924 do not operate at the same time. A pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, a command parser for a graphics processor will halt command processing until the active drawing engine completes pending operations and the associated read cache is invalid. Alternatively, any data in the render cache marked as "dirty" may be flushed to memory. In some embodiments, the pipeline flush command 912 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

In some embodiments, the pipeline select command 913 is used when the command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 913 is only required once within the execution context before issuing the pipeline command, unless the context is to issue commands for both pipelines. In some embodiments, pipeline switch via pipeline select command 913 occurs immediately after pipeline flush command 912 is needed.

In some embodiments, pipeline control commands 914 configure a graphics pipeline for operation and are used to program 3D pipeline 922 and media pipeline 924. In some embodiments, the pipeline control commands 914 configure the pipeline state for the active pipeline. In one embodiment, the pipeline control command 914 is used for pipeline synchronization and to flush data from one or more caches within the active pipeline before processing a batch of commands.

In some embodiments, the return buffer status command 916 is used to configure a set of return buffers for the respective pipeline to write data. Some pipelining requires the allocation, selection, or configuration of one or more return buffers into which an operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communications. In some embodiments, the return buffer status 916 includes the size and number of select return buffers for a set of pipelining operations.

The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on the pipeline determination 920, the command sequence is customized to either a 3D pipeline 922 starting with a 3D pipeline state 930 or a media pipeline 924 starting with a media pipeline state 940.

The commands used to configure the 3D pipeline state 930 include 3D state set commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing the 3D primitive commands. The values of these commands are determined based at least in part on the particular 3D API in use. In some embodiments, the 3D pipeline state 930 command can also selectively disable or bypass certain pipeline elements if those elements are not to be used.

In some embodiments, the 3D primitive 932 command is used to submit a 3D primitive to be processed by the 3D pipeline. Commands and associated parameters passed to the graphics processor via the 3D primitive 932 commands are forwarded to a vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 932 command is for performing a vertex operation on the 3D primitive via a vertex shader. To process the vertex shader, 3D pipeline 922 dispatches shader execution threads to the graphics processor execution unit.

In some embodiments, the 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, the register write triggers the command execution. In some embodiments, execution is triggered via a "go" or "kick" command in the command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to flush a sequence of commands through a graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once the operation is complete, the resulting geometric object is rasterized and the pixel engine paints the resulting pixels. Additional commands to control pixel shading and pixel back-end operations may also be included for those operations.

In some embodiments, graphics processor command sequence 910 follows the media pipeline 924 path when performing media operations. In general, the particular use and manner of programming for media pipeline 924 depends on the media or computing operation to be performed. During media decoding, certain media decoding operations may be offloaded to a media pipeline. In some embodiments, the media pipeline may also be bypassed and media decoding may be performed in whole or in part using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline further includes elements for General Purpose Graphics Processor Unit (GPGPU) operations, wherein the graphics processor is to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similar manner as 3D pipeline 922. A set of commands to configure the media pipeline state 940 are dispatched or placed into a command queue prior to the media object command 942. In some embodiments, the commands for the media pipeline state 940 include data to configure the media pipeline elements to be used to process the media object. This includes data, such as encoding or decoding formats, used to configure the video decoding and video encoding logic within the media pipeline. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements that contain a collection of state settings.

In some embodiments, the media object commands 942 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all of the media pipeline state must be valid before issuing the media object command 942. Once the pipeline state is configured and the media object commands 942 are queued, the media pipeline 924 is triggered via an execution command 944 or equivalent execution event (e.g., a register write). The output from media pipeline 924 may then be post-processed by operations provided by 3D pipeline 922 or media pipeline 924. In some embodiments, GPGPU operations are configured and performed in a similar manner as media operations.

Graphics software architecture

FIG. 10 illustrates an exemplary graphics software architecture for data processing system 1000 in accordance with some embodiments. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, processor 1030 includes a graphics processor 1032 and one or more general purpose processor cores 1034. Graphics application 1010 and operating system 1020 each execute in the system memory 1050 of the data processing system.

In some embodiments, 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions can be in a high level shader language, such as High Level Shader Language (HLSL) or OpenGL shader language (GLSL). The application program also includes executable instructions 1014 in machine language suitable for execution by the general purpose processor core 1034. The application also includes a graphical object 1016 defined by the vertex data.

In some embodiments, the operating system 1020 is Microsoft Windows ® operating system from Microsoft corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating system 1020 may support a graphics API 1022, such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system 1020 compiles any shader instructions 1012 with HLSL into a lower-level shader language using a front-end shader compiler 1024. The compilation may be a just-in-time (JIT) compilation, or the application may perform shader precompilation. In some embodiments, the high-level shaders are compiled into low-level shaders during compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 includes a back-end shader compiler 1027 to convert shader instructions 1012 into a hardware specific representation. When the OpenGL API is in use, shader instructions 1012 in the GLSL high-level language are passed to user-mode graphics driver 1026 for compilation. In some embodiments, the user mode graphics driver 1026 uses operating system kernel mode functionality 1028 to communicate with the kernel mode graphics driver 1029. In some embodiments, the kernel mode graphics driver 1029 communicates with the graphics processor 1032 to dispatch commands and instructions.

IP check cash-in mode

One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and/or defines logic within an integrated circuit such as a processor. For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such a representation, referred to as an "IP core," is a reusable logic unit for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities that load the hardware model on the manufacturing machines that manufacture the integrated circuits. An integrated circuit may be fabricated such that the circuit performs the operations described in association with any of the embodiments described herein.

Fig. 11A is a block diagram illustrating an IP core development system 1100 that may be used to fabricate an integrated circuit to perform operations, according to an embodiment. The IP core development system 1100 may be used to generate modular reusable designs that may be incorporated into a larger design or used to build an entire integrated circuit (e.g., an SOC integrated circuit). Design facility 1130 may generate software simulation 1110 of an IP core design in a high-level programming language (e.g., C/C + +). Software simulation 1110 may be used to design, test, and verify the behavior of an IP core using simulation model 1112. Simulation model 1112 may include functional, behavioral, and/or timing simulations. A Register Transfer Level (RTL) design 1115 may then be created or synthesized from simulation model 1112. RTL design 1115 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including associated logic that is executed using the modeled digital signals. In addition to RTL design 1115, lower level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by the design facility into a hardware model 1120, which hardware model 1120 may be in a Hardware Description Language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to validate the IP core design. The IP core design may be stored for delivery to a third party manufacturing facility 1165 using non-volatile memory 1140 (e.g., a hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design may be transmitted over a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). Manufacturing facility 1165 may then fabricate integrated circuits based at least in part on the IP core design. The integrated circuit fabricated may be configured to perform operations in accordance with at least one embodiment described herein.

Figure 11B illustrates a cross-sectional side view of an integrated circuit package assembly 1170 according to some embodiments described herein. The integrated circuit package assembly 1170 illustrates an implementation of one or more processor or accelerator devices as described herein. The packaging assembly 1170 includes multiple units of hardware logic 1172, 1174 connected to a substrate 1180. The logic 1172, 1174 may be implemented at least partially in configurable logic or fixed functionality logic hardware, and may include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator device described herein. Each unit of logic 1172, 1174 may be implemented within a semiconductor die and coupled with a substrate 1180 via an interconnect 1173. The interconnect structures 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180, and may include interconnects such as, but not limited to, bumps (bump) or pillars (pilar). In some embodiments, the interconnect fabric 1173 may be configured to route electrical signals, such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, substrate 1180 is an epoxy-based laminate substrate. In other embodiments, the package substrate 1180 may include other suitable types of substrates. The package assembly 1170 may be connected to other electrical devices via a package interconnect 1183. Package interconnect 1183 may be coupled to a surface of substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipset, or a multi-chip module.

In some embodiments, the units of logic 1172, 1174 are electrically coupled with a bridge 1182 configured to route electrical signals between logic 1172, 1174. Bridge 1182 may be a dense interconnect structure that provides a route for electrical signals. The bridge 1182 may include a bridge substrate constructed of glass or a suitable semiconductor material. Electrical routing features may be formed on the bridge substrate to provide chip-to-chip connections between the logics 1172, 1174.

Although two units of logic 1172, 1174 and bridge 1182 are illustrated, embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as bridge 1182 may not be included when the logic is included on a single die. Alternatively, multiple dies or logic units may be connected by one or more bridges. Additionally, multiple logic cells, dies, and bridges may be connected together in other possible configurations, including three-dimensional configurations.

Exemplary System-on-chip Integrated Circuit

Fig. 12-14 illustrate an example integrated circuit and associated graphics processor that may be fabricated using one or more IP cores, according to various embodiments described herein. Other logic and circuitry may be included in addition to that illustrated, including additional graphics processor/cores, peripheral interface controllers, or general purpose processor cores.

Fig. 12 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1200 that may be fabricated using one or more IP cores, according to an embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., CPUs), at least one graphics processor 1210, and may additionally include an image processor 1215 and/or a video processor 1220, any of which may be modular IP cores from the same or multiple different design facilities. Integrated circuit 1200 includes peripheral or bus logic that includes USB controller 1225, UART controller 1230, SPI/SDIO controller 1235, and I²S/I²C controller 1240. In addition, integrated electricityThe interface may include a display device 1245 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1250 and a Mobile Industry Processor Interface (MIPI) display interface 1255. Storage may be provided by a flash subsystem 1260 including flash memory and a flash controller. A memory interface may be provided via the memory controller 1265 for accessing SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270.

Fig. 13A-13B are block diagrams illustrating an exemplary graphics processor for use within a SoC, according to embodiments described herein. FIG. 13A illustrates an example graphics processor 1310 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. FIG. 13B illustrates an additional exemplary graphics processor 1340 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. Graphics processor 1310 of FIG. 13A is an example of a low power graphics processor core. Graphics processor 1340 of fig. 13B is an example of a higher performance graphics processor core. Each of the

graphics processors

1310, 1340 may be a variation of the graphics processor 1210 of fig. 12.

As shown in FIG. 13A, graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D through 1315N-1, and 1315N). Graphics processor 1310 may execute different shader programs via separate logic, such that vertex processor 1305 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 1315A-1315N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. Vertex processor 1305 executes the vertex processing stages of the 3D graphics pipeline and generates primitive and vertex data. The fragment processor(s) 1315A-1315N use the primitives and vertex data generated by the vertex processor 1305 to produce a frame buffer for display on a display device. In one embodiment, fragment processor(s) 1315A-1315N are optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform similar operations as pixel shader programs as provided in the Direct3D API.

Graphics processor 1310 additionally includes one or more Memory Management Units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B. The one or more MMUs 1320A-1320B provide virtualization of physical address mapping for a graphics processor 1310 (including for a vertex processor 1305 and/or fragment processor(s) 1315A-1315N), the vertex processor 1305 and/or fragment processor(s) 1315A-1315N may reference vertex or image/texture data stored in memory in addition to vertex or image/texture data stored in the one or more caches 1325A-1325B. In one embodiment, the one or more MMUs 1320A-1320B may be synchronized with other MMUs within the system, including one or more MMUs associated with one or more of the application processors 1205, image processors 1215, and/or video processors 1220 of FIG. 12, such that each processor 1205A-1220 may participate in a shared or unified virtual memory system. According to an embodiment, the one or more circuit interconnects 1330A-1330B enable graphics processor 1310 to interface with other IP cores within the SoC, either via the SoC's internal bus or via a direct connection.

As shown in FIG. 13B, graphics processor 1340 includes the one or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of graphics processor 1310 of FIG. 13A. Graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F through 1355N-1, and 1355N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. The exact number of shader cores present may vary between embodiments and implementations. In addition, the graphics processor 1340 includes an inter-core task manager 1345 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1355A-1355N and a tiling (tiling) unit 1358 to accelerate tiling operations for tile-based rendering, where rendering operations for a scene are subdivided in image space, e.g., to exploit local spatial coherence within the scene or to optimize use of internal caches.

14A-14B illustrate additional exemplary graphics processor logic, according to embodiments described herein. FIG. 14A illustrates a graphics core 1400 that may be included within graphics processor 1210 of FIG. 12, and may be a unified shader core 1355A-1355N as in FIG. 13B. FIG. 14B illustrates a highly parallel general purpose graphics processing unit 1430 suitable for deployment on a multi-chip module.

As shown in fig. 14A, graphics core 1400 includes a shared instruction cache 1402, a texture unit 1418, and a cache/shared memory 1420, which are common to the execution resources within graphics core 1400. Graphics core 1400 may include multiple slices 1401A-1401N or partitions for each core, and a graphics processor may include multiple instances of graphics core 1400. The slices 1401A-1401N may include support logic that includes a local instruction cache 1404A-1404N, a thread scheduler 1406A-1406N, a thread dispatcher 1408A-1408N, and a set of registers 1410A. To perform logical operations, slices 1401A-1401N may include a set of additional functional units (AFUs 1412A-1412N), floating point units (FPUs 1414A-1414N), integer arithmetic logic units (ALUs 1416A-1416N), address calculation units (ACUs 1413A-1413N), double precision floating point units (DPFPUs 1415A-1415N), and matrix processing units (MPUs 1417A-1417N).

Some of the calculation units operate with a certain precision. For example, FPUs 1414A-1414N may perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while DPFPUs 1415A-1415N perform double-precision (64-bit) floating-point operations. The ALUs 1416A-1416N may perform variable precision integer operations with 8-bit, 16-bit, and 32-bit precision and may be configured for mixed precision operations. The MPUs 1417A-1417N may also be configured for mixed precision matrix operations, including half precision floating point operations and 8-bit integer operations. The MPUs 1417A-1417N may perform a variety of matrix operations to accelerate the machine learning application framework, including generic matrix-to-matrix multiplication (GEMM) to enable support for acceleration. AFUs 1412A-1412N can perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

As shown in FIG. 14B, general purpose processing unit (GPGPU) 1430 may be configured to enable an array of graphics processing units to perform highly parallel computing operations. Additionally, the GPGPU 1430 may be directly linked to other instances of gpgpgpus to create multiple GPU clusters to improve training speed for a particular deep neural network. The GPGPU 1430 includes a host interface 1432 to enable connection with a host processor. In one embodiment, host interface 1432 is a PCI Express interface. However, the host interface may also be a vendor specific communication interface or communication structure. The GPGPU 1430 receives commands from host processors and uses a global scheduler 1434 to assign execution threads associated with those commands to a set of compute clusters 1436A-1436H. Compute clusters 1436A-1436H share cache 1438. The cache 1438 may serve as a higher level cache for caches within the compute clusters 1436A-1436H.

GPGPU 1430 includes a memory 1444A-1444B coupled to compute cluster 1436A-1436H via a set of memory controllers 1442A-1442B. In various embodiments, memories 1444A-1444B may comprise various types of memory devices, including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory.

In one embodiment, compute clusters 1436A-1436H each include a set of graphics cores, such as graphics core 1400 of fig. 14A, which may include multiple types of integer and floating point logic units that may perform compute operations at a range of precisions including suitable for machine learning computations. For example, and in one embodiment, at least a subset of the floating point units in each of the compute clusters 1436A-1436H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

Multiple instances of the GPGPU 1430 may be configured to operate as a compute cluster. The communication mechanisms used by the computing clusters for synchronization and data exchange vary across embodiments. In one embodiment, the multiple instances of GPGPU 1430 communicate through host interface 1432. In one embodiment, GPGPU 1430 includes an I/O hub 1439 that couples GPGPU 1430 with a GPU link 1440 that enables direct connections to other instances of the GPGPU, 1439. In one embodiment, GPU link 1440 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1430. In one embodiment, GPU link 1440 is coupled with a high speed interconnect to transmit and receive data to other GPGPGPUs or parallel processors. In one embodiment, the multiple instances of GPGPU 1430 are located in separate data processing systems and communicate via a network device accessible via host interface 1432. In one embodiment, GPU link 1440 may be configured to enable a connection to a host processor in addition to or instead of host interface 1432.

While the illustrated configuration of the GPGPU 1430 may be configured to train a neural network, one embodiment provides an alternative configuration of the GPGPU 1430 that may be configured for deployment within a high performance or low power inference platform. In the inference configuration, the GPGPU 1430 includes fewer compute clusters 1436A-1436H relative to the training configuration. Additionally, the memory technology associated with memories 1434A-1434B may differ between inference and training configurations, with higher bandwidth memory technologies addressing training configurations. In one embodiment, the inference configuration of the GPGPU 1430 may support inference specific instructions. For example, the inference configuration may provide support for one or more 8-bit integer dot-product instructions that are typically used during inference operations for deployed neural networks.

Multi-phase shader for multi-rate pixel shading

In some embodiments, a device, system, or process will provide multi-rate shading of pixel data with a multi-phase shader. The multi-phase architecture provides pixel shading at a level of rendering granularity and allows for improved efficiency, including allowing pixel data to be redistributed in the packing of SIMD lanes. A multi-phase shader may be implemented to provide improved efficiency, for example, in SIMD computing operations.

In some embodiments, a multi-phase shader, such as the multi-phase shader 1535 illustrated in fig. 15, the multi-phase shader 1600 in fig. 16, and the multi-phase shader 1705 in fig. 17, will provide multiple rendering phases (which may also be referred to herein as shader phases or as phases), where each phase provides a certain rate and rendering granularity for image rendering. For example, shader periods may include, but are not limited to, Coarse Pixel (CP) shader periods, pixel (P) shader periods, and sample (S) periods. Such shader times are illustrated in fig. 18.

In some embodiments, each of a plurality of shader periods (such as CP, P, and S shader periods) of a multi-phase shader is compiled into a separate kernel with separate kernel state pointers and SIMDs. In some embodiments, the implementation of a multi-phase shader in an API (application programming interface) allows each of the shader phases to be exposed to the API, and thus enables a user to control the operation of each shader phase as needed in image rendering. In some embodiments, the user's control over the API includes controls as to which of the multiple rendering stages are active in the hierarchy of stages, and thus the user can select which of the multiple rendering stages will be active in operation. In contrast to monolithic shaders that are limited to nested loops within a particular rendering epoch, multi-epoch shaders are operable to support inner loops between different rendering granularities (such as between CP, P, and S shader epochs).

Fig. 15 is an illustration of a processing system including a multi-phase shader to provide improved operating efficiency, according to some embodiments. In some embodiments, processing system 1500 (such as processing system 100 illustrated in fig. 1) includes one or more processor cores. In some embodiments, the processing system 1500 is structured to include one or more processors 1510 (which may include one or more CPUs (central processing units)), such as the processor 102 illustrated in fig. 1, having one or more processor cores, and further includes one or more GPUs 1520, such as the graphics processor 108 illustrated in fig. 1, having one or more graphics processor cores, where the GPU 1520 may be included within the one or more processors 1510 or separate from the one or more processors 1510. However, embodiments are not limited to this particular processing architecture. The one or more processors 1510 may include elements as illustrated for processor 200 in fig. 2, and the one or more GPUs 1520 may include elements as illustrated for graphics processor 300 in fig. 3. The processing system further includes a memory 1540 for storing data, including data for processing by the one or more GPUs 1520.

In some embodiments, the one or more GPUs 1520 include a graphics pipeline 1530, such as the 3D pipeline 312 illustrated in fig. 3, where the graphics pipeline 1530 includes a multi-phase shader 1535 to provide shading with a hierarchy of different rendering granularities (from coarsest to finest of the rendering granularity hierarchy). The multi-phase shader 1535 includes multiple phases (or phases), where each of the multiple phases will support one of multiple rendering granularities. The multi-phase shader 1535 may, for example, include multiple phases as illustrated in the multi-phase shader 1600 in fig. 16 or the multi-phase shader 1705 in fig. 17. In some embodiments, the structure of the shader may be used to support inner loops between the rendering stages 1610 and 1630.

FIG. 16 is an illustration of a multi-phase shader, according to some embodiments. In some embodiments, the multi-phase shader 1600 includes a hierarchy of multiple rendering phases or phases to support each of multiple different rendering granularities. As illustrated in fig. 16, the multiple phases active in a hierarchy of rendering periods or phases may include, for example: a first stage, rendering stage-11610, for rendering with the coarsest granularity of the image, Coarse Pixels (CP); second, render stage-21620, render to medium granularity, pixel (P); and a third stage, rendering stage-31630, for rendering, sample (S), with the finest granularity of the image. In this illustration, rendering stage-11610 may be referred to as being adjacent to rendering stage-21620 in the hierarchy of rendering stages, and rendering stage-2 is adjacent to rendering stage-31630 in the hierarchy. In some embodiments, adjacent stages in the hierarchy of rendering stages are communicatively coupled with each other. As illustrated in fig. 16, rendering stage-11610 is communicatively coupled with rendering stage-21620, and rendering stage-21620 is communicatively coupled with rendering stage-31630. Embodiments, however, are not limited to the illustrated stages and may include different granularities, different numbers of stages, or both.

In some embodiments, the following rationale is applied in the multi-phase shader 1600 to achieve multi-phase shading:

(1) the multiple rendering stages, illustrated as CP rendering stage 1610, P rendering stage 1620, and S rendering stage 1630, are each compiled into separate cores, each having separate core state pointers and SIMDs.

(2) After dispatching the coarse pixels or pixel renderings (coarser granularity), the data by the coarse pixels will be written out to local on-chip memory, and then the pixel and/or sample shader times will be invoked by combining the available pixels and/or samples, which use the same set of states (i.e., are part of the same graph (draw)).

(3) As long as there are fragments in the polygon in flight, all interpolations are made available via the pull model and on-chip storage for the attributes is maintained.

FIG. 17 is a diagram of a device or system including a multi-phase shader. In some embodiments, system 1700 (such as processing system 100 as illustrated in fig. 1) includes a multi-phase shader 1705, the multi-phase shader 1705 including multiple rendering stages, where each stage addresses rendering for a particular granularity of an image.

As illustrated in fig. 17, the multi-phase shader 1705 includes a Coarse Pixel (CP) phase 1710, a pixel (P) phase 1720, and a sample (S) phase 1730. However, embodiments are not limited to this particular configuration and may include a different number of stages, different types of stages, or both. In some embodiments, the multi-phase shader 1705 provides a hierarchical shading structure in which shading proceeds from coarsest granularity (least fine granularity), such as coarse pixels in the CP stage 1710, to finest granularity, such as samples in the S stage 1730. In some embodiments, the remaining pixel data at the stage may be transferred to a finer granularity stage, such as transferring the remaining data from the CP stage 1710 to the P stage 1720, and transferring the remaining data from the P stage 1720 to the S stage 1730. Each of the stages 1710-1730 may include buffers (shown as BUF1 and BUF 2) for buffering data transferred between the stages; a local memory (local Mem) for storing data; and a dispatching component. The dispatch elements in each stage 1710-; the P phase 1720 includes a P + BC + dispatch; and S stage 1730 includes S + BC + assignment.

In some embodiments, the implementation of the multi-phase shader 1705 allows each of the phases 1710-1730 to be exposed to the API, and thus enables a user to control the operation of each phase as needed in the image rendering. In a particular example of pixel data for a triangular region in an image, the granularity required for each portion of the region, such as the fine granularity (samples) required for the edges of the triangle and the coarser granularity (coarse pixels or pixels) applied to other portions of the triangle, may be controlled by the user through an API.

In some embodiments, the multi-phase shader 1705 receives data at the coarsest stage (CP stage 1710 in fig. 17), shown as receipt of pixel data 1735 in fig. 17. The multi-phase shader 1705 provides a hierarchy for pixel shading based on the received data. In operation, the multi-phase shader 1705 provides for the transfer of data between stages, illustrated as CP data from CP stage 1710 to P stage 1720 and Dref (reference) CP data from P stage 1720 to CP stage 1710, according to the granularity for imaging; and P data from P phase 1720 to S phase 1730 and Dref P data from S phase 1730 to P phase 1720.

In some embodiments, the stages 1710-1730 are thus structured to allow for inlining of the stages 1710-1730 across multi-phase shaders in addition to any inlining within the stages at any particular granularity. In particular, inter-cycling is enabled between adjacent stages, such as between CP and P granularity (CP stage 1710 and P stage 1720) and between P and S granularity (P stage 1720 and S stage 1730).

In some embodiments, the multi-phase shader architecture allows for increased efficiency in the packing of SIMD lanes. As illustrated in FIG. 17, dispatch data from each of stages 1710-1730 is provided to a P-thread (pixel thread) arbiter 1740 to arbitrate between thread-initiated requests, with the resulting thread data being provided to a local Thread Dispatcher (TDL) 1745. TDL 1745 will dispatch execution threads associated with multi-phase shader 1705 for processing by SIMD computation 1750, which SIMD computation 1750 is illustrated as including multiple Execution Units (EUs), illustrated as EUs 0, EU1, EU2, EU3, and EU 4. The EUs may be as illustrated, for example, in EUs within the EU arrays 502A-502F illustrated in FIG. 5 and EUs 608A-608B illustrated in FIG. 6A. The output of the SIMD computation is then provided to a data port 1755 to direct the data to a memory, such as the illustrated Unified Return Buffer (URB) 1760, which may include the URB 418 illustrated in fig. 4, which includes buffer space for CP, P, and S data.

Fig. 18 is an illustration of pixel granularity in a system to provide multi-phase shading according to some embodiments. As illustrated in fig. 18, for the example of 4 xmaa (multisampling antialiasing), each S1810 is a sample. The 2x2 sample set 1820 represents pixels, and the 2x2 pixel set (or 4x4 sample set) 1830 represents coarse pixels.

Thus, fig. 18 illustrates a total set of 2x2 coarse pixels, or a total set of 4x4 pixels. In FIG. 18, two triangles (as divided by the dashed line) cover the 2x2 coarse set of pixels, the triangles being denoted as triangle-11840 and triangle-21845. When CP rate assignment with monolithic multi-rate coloring occurs in the conventional architecture, each call has 2x2 CPs, such as illustrated in fig. 18, with half of the pixels relaxing (fade) under the helper CP. Thus, 8 pixels are lit and the other 8 are unlit. If the pixel ring is SIMD16, there are only half as many pixels.

In some embodiments, an apparatus, system, or process that provides multi-phase shading (such as illustrated in one or more of fig. 15-17) allows for the shading of all pixels with SIMD16 instructions, as two CP calls will be allowed to buffer 16 pixels and process them in the P-phase, as opposed to single-chip multi-rate shading.

FIG. 19 is a flow diagram to illustrate a process for multi-phase shading for image rendering, according to some embodiments. In some embodiments, in a process for image rendering, data is directed to a multi-phase shader 1902, such as the multi-phase shader 1600 illustrated in fig. 16 or the multi-phase shader 1700 illustrated in fig. 17. The multi-phase shader may include a Coarse Pixel (CP) rendering stage 1910, a pixel (P) rendering stage 1930, and a sample (S) rendering stage 1950. However, embodiments are not limited to the illustrated stages and may include different granularities, different numbers of rendering stages, or both. In some embodiments, the process provides hierarchical shading in a plurality of different rendering shading stages, from the coarsest granularity provided by the rendering stage to the finest granularity of the rendering stage. In some embodiments, the process further supports inner loops between different granularities supported by the rendering phase 1910-.

In some embodiments, the pixel data is directed to the first rendering stage of the multi-phase shader, which is the CP stage (or generally the stage in the hierarchy of shading stages with the coarsest granularity for imaging) 1910. The received data is directed to processing at CP stage 1912. Upon completion of CP rendering, the CP data is directed to an arbiter 1916, such as pixel thread arbiter 1740 illustrated in fig. 17. Further presence determination 1918: whether there is remaining data to be provided to a finer granularity in the hierarchy of the rendering phase (which in the illustrated example is the P phase 1918), shown as CP data 1924 directed to the P phase 1930. If there is no remaining data to be directed to the P phase, the process may continue with other data processing, including any remaining processing in other periods of the multi-phase shader.

In some embodiments, data received at the P-phase 1930 is directed to processing at the P-phase 1932. Upon completion of the P rendering, the P data is directed to arbiter 1936. Further presence determination 1938: whether there is data to be provided to the CP phase 1930 (providing cycles in processing between the CP phase 1910 and the P phase 1930), and a determination 1942: whether there is remaining data to be provided to a finer granularity in the hierarchy of the shading phase (which in the illustrated example is the S phase 1950) is shown as P data 1944 directed to the S phase 1950. If there is no remaining data to be directed to the S phase, the process may continue with other data processing, including any remaining processing in other periods of the multi-phase shader.

In some embodiments, the data received at S phase 1950 is directed to processing at S phase 1952. Upon completion of the S rendering, the S data is directed to arbiter 1956. Further there is a determination 1958: whether there is data to be provided to the P phase 1930. If there is no data to be directed to the P phase, the process may continue with other data processing, including any remaining processing in other phases of the multi-phase shader.

In some embodiments, an apparatus includes one or more processor cores including a graphics pipeline and a memory to store data for graphics processing, the data including pixel data. In some embodiments, the graphics pipeline includes a multi-phase shader for processing pixel data, the multi-phase shader including a plurality of rendering phases including at least a first phase for a first rendering granularity and a second phase for a second, different rendering granularity, the second rendering granularity being a finer granularity than the first rendering granularity. In some embodiments, the multi-phase shader is configured to provide a hierarchy for image rendering, wherein pixel data is received at a rendering stage of the plurality of rendering stages having a coarsest rendering granularity, wherein remaining pixel data is provided through the hierarchy to one or more rendering stages having a finer rendering granularity.

In some embodiments, the plurality of rendering stages includes at least a Coarse Pixel (CP) stage for CP data, a P stage for pixel (P) data, and an S stage for sample (S) data.

In some embodiments, wherein the first stage is adjacent to the second stage in the hierarchy for image rendering, and wherein the first stage is communicatively coupled with the second stage.

In some embodiments, the multi-phase shader enables cycling of pixel data between the multiple rendering phases.

In some embodiments, each of the plurality of rendering stages will provide processed data to the pixel thread arbiter as needed.

In some embodiments, each of the plurality of rendering stages is compiled into a separate kernel.

In some embodiments, each of the plurality of rendering stages is exposed to an Application Programming Interface (API), and each rendering stage is controllable by a user through the API.

In some embodiments, wherein the control by the user through the API includes control as to which of the plurality of rendering stages are active.

In some embodiments, the apparatus is to utilize the multiple rendering stages of the multi-phase shader to redistribute pixel data between the rendering stages for packing lines for SIMD (single instruction multiple data) computations.

In some embodiments, a non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising receiving pixel data at a first stage of a multi-phase shader, the shader comprising a plurality of rendering stages in a hierarchy for imaging rendering, the plurality of rendering stages including at least the first stage for a first rendering granularity and a second stage for a second, different rendering granularity, the second rendering granularity being a finer granularity than the first rendering granularity; processing the pixel data in the plurality of rendering stages, wherein processing includes providing remaining pixel data from a rendering stage of the plurality of rendering stages to one or more rendering stages having a finer rendering granularity; and outputting the processed pixel data from each of the plurality of rendering stages according to the rendering granularity of each rendering stage.

In some embodiments, the first stage is adjacent to the second stage in the hierarchy for image rendering, and wherein the first stage is communicatively coupled with the second stage.

In some embodiments, the instructions include instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising cycling pixel data between the plurality of rendering phases.

In some embodiments, the instructions further include instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising providing processed data from each of the plurality of rendering stages to a pixel thread arbiter as needed.

In some embodiments, the instructions include instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising activating a set of rendering stages of the plurality of rendering stages in response to the instructions received through the API.

In some embodiments, the instructions further include instructions that, when executed by the one or more processors, cause the one or more processors to perform operations including reallocating pixel data among the plurality of rendering stages for packing lines for SIMD (single instruction multiple data) computations.

In some embodiments, a processing system includes a plurality of processors including one or more graphics processing units including a multi-phase shader for processing pixel data, the multi-phase shader including a plurality of rendering phases including at least a Coarse Pixel (CP) phase for CP data, a P phase for pixel (P) data, and an S phase for sample (S) data. In some embodiments, the multi-phase shader is configured to provide a hierarchy for image rendering, wherein pixel data is received at a rendering stage of the plurality of rendering stages having a coarsest rendering granularity, wherein remaining pixel data is provided through the hierarchy to one or more rendering stages having a finer rendering granularity.

In some embodiments, the processing system further comprises a pixel thread arbiter to arbitrate between pixel threads, wherein each of the plurality of rendering stages is to provide processed data to the pixel thread arbiter as needed.

In some embodiments, the processing system further comprises a local thread dispatcher coupled with the pixel thread arbiter, and further comprises a plurality of execution units to receive dispatched threads for SIMD computations from the local thread dispatcher, wherein the multi-phase shader allows packing of lines for the SIMD computations.

The control by the user through the API includes control as to which of the plurality of rendering stages are active.

In some embodiments, a method includes receiving pixel data at a first stage of a multi-phase shader, the shader including a plurality of rendering stages in a hierarchy for imaging rendering, the plurality of rendering stages including at least a first stage for a first rendering granularity and a second stage for a second, different rendering granularity, the second rendering granularity being a finer granularity than the first rendering granularity; processing the pixel data in the plurality of rendering stages, wherein processing includes providing remaining pixel data from a rendering stage of the plurality of rendering stages to one or more rendering stages having a finer rendering granularity; and outputting the processed pixel data from each of the plurality of rendering stages according to the rendering granularity of each rendering stage.

In some embodiments, the method further comprises cycling pixel data between the plurality of rendering stages.

In some embodiments, the method further comprises providing the processed data from each of the plurality of rendering stages to a pixel thread arbiter as needed.

In some embodiments, the method further comprises activating a set of rendering stages of the plurality of rendering stages in response to instructions received through the API.

In some embodiments, the method further comprises reallocating pixel data among the plurality of rendering stages for packing lines for SIMD (single instruction multiple data) computations.

In some embodiments, an apparatus includes means for receiving pixel data at a first stage of a multi-phase shader, the shader including a plurality of rendering stages in a hierarchy for imaging rendering, the plurality of rendering stages including at least the first stage for a first rendering granularity and a second stage for a second, different rendering granularity, the second rendering granularity being a finer granularity than the first rendering granularity; means for processing the pixel data in the plurality of rendering stages, wherein processing includes providing remaining pixel data from a rendering stage of the plurality of rendering stages to one or more rendering stages having a finer rendering granularity; and means for outputting processed pixel data from each of the plurality of rendering stages according to the rendering granularity of each rendering stage.

In some embodiments, the apparatus further comprises means for cycling pixel data between the plurality of rendering phases.

In some embodiments, the apparatus further comprises means for providing the processed data from each of the plurality of rendering stages to a pixel thread arbiter as needed.

In some embodiments, the apparatus further comprises means for activating a set of rendering stages of the plurality of rendering stages in response to instructions received through the API.

In some embodiments, the apparatus further comprises means for reallocating pixel data among the plurality of rendering stages for packing lines for SIMD (single instruction multiple data) computations.

In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the described embodiments. It will be apparent, however, to one skilled in the art that the embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form. Intermediate structures may exist between the illustrated components. Components described or illustrated herein may have additional inputs or outputs not illustrated or described.

Various embodiments may include various processes. These processes may be performed by hardware components or may be embodied in computer programs or machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the processes. Alternatively, the process may be performed by a combination of hardware and software.

Portions of various embodiments may be provided as a computer program product which may include a computer-readable medium having stored thereon computer program instructions which may be used to program a computer (or other electronic devices) for execution by one or more processors to perform a process according to some embodiments. The computer-readable medium may include, but is not limited to, magnetic disks, optical disks, read-only memories (ROMs), Random Access Memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or other type of computer-readable media suitable for storing electronic instructions. Moreover, embodiments may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer to a requesting computer. In some embodiments, a non-transitory computer-readable storage medium has stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform certain operations.

Most methods are described in their most basic form, but processes can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of embodiments of the present invention. It will be apparent to those skilled in the art that many further modifications and adaptations can be made. The specific embodiments are not provided to limit the concepts but to illustrate them. The scope of the embodiments is not to be determined by the specific examples provided above but only by the claims below.

If it is said that element "A" is coupled to or with element "B", element A may be directly coupled to element B or indirectly coupled through, for example, element C. When the specification or claims state that a component, feature, structure, process, or characteristic a "causes" a component, feature, structure, process, or characteristic B, it means that "a" is at least part of "B," but there may be at least one other component, feature, structure, process, or characteristic that helps cause "B. If the specification states a component, feature, structure, process, or characteristic "may", "might", or "could" be included, that particular component, feature, structure, process, or characteristic is not required to be included. If the specification or claims refer to "a" or "an" element, that does not mean there is only one of the element so described.

An embodiment is an implementation or example. Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. It should be appreciated that in the foregoing description of exemplary embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various novel aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, novel aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the following claims are hereby expressly incorporated into this description, with each claim standing on its own as a separate embodiment.

Claims

1. An apparatus, comprising:

one or more processor cores, the one or more processing cores comprising a graphics pipeline; and

a memory to store data for graphics processing, the data comprising pixel data;

wherein the graphics pipeline includes a multi-phase shader for processing pixel data, the multi-phase shader including a plurality of rendering phases including at least a first phase for a first rendering granularity and a second phase for a second, different rendering granularity, the second rendering granularity being a finer granularity than the first rendering granularity; and is

Wherein the multi-phase shader is configured to provide a hierarchy for image rendering, wherein pixel data is received at a rendering stage of the plurality of rendering stages having a coarsest rendering granularity, wherein remaining pixel data is provided by the hierarchy to one or more rendering stages having a finer rendering granularity.

2. The apparatus of claim 1, wherein the plurality of rendering stages includes at least a Coarse Pixel (CP) stage for CP data, a P stage for pixel (P) data, and an S stage for sample (S) data.

3. The apparatus of claim 1, wherein the first stage is adjacent to the second stage in the hierarchy for image rendering, and wherein the first stage is communicatively coupled with the second stage.

4. The apparatus of claim 1, wherein the multi-phase shader enables cycling of pixel data between the plurality of rendering phases.

5. The apparatus of claim 1, wherein each of the plurality of rendering stages is to provide processed data to a pixel thread arbiter as needed.

6. The apparatus of claim 1, wherein each of the plurality of rendering stages is compiled into a separate kernel.

7. The apparatus of claim 1, wherein each of the plurality of rendering stages is exposed in an Application Programming Interface (API), and each rendering stage is controllable by a user through the API.

8. The apparatus of claim 7, wherein the control by the user through the API includes control on which of the plurality of rendering stages are active.

9. The apparatus of claim 1, wherein the apparatus is to utilize the multiple rendering stages of the multi-phase shader to redistribute pixel data between the rendering stages for packing lines for SIMD (single instruction multiple data) computations.

10. An apparatus, comprising:

means for receiving pixel data at a first stage of a multi-phase shader, the shader including a plurality of rendering stages in a hierarchy for imaging rendering, the plurality of rendering stages including at least the first stage for a first rendering granularity and a second stage for a second, different rendering granularity, the second rendering granularity being a finer granularity than the first rendering granularity;

means for processing the pixel data in the plurality of rendering stages, wherein processing includes providing remaining pixel data from a rendering stage of the plurality of rendering stages to one or more rendering stages having a finer rendering granularity; and

means for outputting processed pixel data from each of the plurality of rendering stages according to a rendering granularity of each rendering stage.

11. The apparatus of claim 10, wherein the plurality of rendering stages includes at least a Coarse Pixel (CP) stage for CP data, a P stage for pixel (P) data, and an S stage for sample (S) data.

12. The apparatus of claim 10, wherein the first stage is adjacent to the second stage in the hierarchy for image rendering, and wherein the first stage is communicatively coupled with the second stage.

13. The apparatus of claim 10, further comprising:

means for cycling pixel data between the plurality of rendering phases.

14. The apparatus of claim 10, further comprising:

means for providing the processed data from each of the plurality of rendering stages to a pixel thread arbiter as needed.

15. The apparatus of claim 10, wherein each of the plurality of rendering stages is compiled into a separate kernel.

16. The apparatus of claim 10, wherein each of the plurality of rendering stages is exposed in an Application Programming Interface (API), and each rendering stage is controllable by a user through the API.

17. The apparatus of claim 16, further comprising:

means for activating a set of rendering stages of the plurality of rendering stages in response to instructions received through the API.

18. The apparatus of claim 10, further comprising:

means for reallocating pixel data among the plurality of rendering stages for packing lines for SIMD (single instruction multiple data) computations.

19. A processing system, comprising:

a plurality of processors including one or more graphics processing units, the one or more graphics processing units comprising:

a multi-phase shader for processing pixel data, the multi-phase shader including a plurality of rendering phases including at least a Coarse Pixel (CP) phase for CP data, a P phase for pixel (P) data, and an S phase for sample (S) data;

20. The processing system of claim 19, wherein the multi-phase shader enables looping of pixel data between the plurality of rendering phases.

21. The processing system of claim 19, further comprising a pixel thread arbiter to arbitrate between pixel threads, wherein each of the plurality of rendering stages is to provide processed data to the pixel thread arbiter as needed.

22. The processing system of claim 21, further comprising a local thread dispatcher coupled with the pixel thread arbiter, and further comprising a plurality of execution units to receive dispatched threads for SIMD computations from the local thread dispatcher, wherein the multi-phase shader allows packing of lines for the SIMD computations.

23. The processing system of claim 19, wherein each of the plurality of rendering stages is exposed in an Application Programming Interface (API), and each rendering stage is controllable by a user through the API.

24. The processing system of claim 23, wherein the control by the user through the API includes control as to which of the plurality of rendering stages are active.