CN110958503B - Bandwidth distribution device and method - Google Patents
Bandwidth distribution device and method Download PDFInfo
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- CN110958503B CN110958503B CN201911221520.4A CN201911221520A CN110958503B CN 110958503 B CN110958503 B CN 110958503B CN 201911221520 A CN201911221520 A CN 201911221520A CN 110958503 B CN110958503 B CN 110958503B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/70—Admission control; Resource allocation
- H04L47/80—Actions related to the user profile or the type of traffic
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/70—Admission control; Resource allocation
- H04L47/82—Miscellaneous aspects
- H04L47/822—Collecting or measuring resource availability data
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
- H04Q2011/0086—Network resource allocation, dimensioning or optimisation
Abstract
The embodiment of the invention provides a bandwidth allocation device and a bandwidth allocation method, which are used for realizing a port giving consideration to both 100G bandwidth output and 400G bandwidth output, improving the bandwidth utilization rate of the port and reducing the design cost. The device comprises a Media Access Controller (MAC), a first physical interface (PHY), a second PHY and a Central Processing Unit (CPU), wherein the first PHY and the second PHY are of the same type; the CPU is connected with the MAC; the MAC is used for outputting the bandwidth to be allocated; the CPU is used for controlling the working modes of the first PHY and the second PHY; the first PHY and the second PHY are used for allocating the bandwidth to be allocated and outputting.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a bandwidth allocation apparatus and method.
Background
For example, when a 400G bandwidth needs to be transmitted in 4 bandwidths of 100G, a Media Access Controller (MAC) in the core switch is connected to a Physical interface transceiver (PHY), each of 8 channels connected between the MAC and the PHY can maximally pass through a 50G bandwidth, so that the PHY can maximally receive the 400G bandwidth, and then the four output ports of the PHY respectively transmit the 100G bandwidth.
With the continuous development of communication technology, the requirement for the network is higher and higher, the core switch may have ports of 100G and 400G, and to meet the requirement, in the prior art, the first is to design a type of PHY, which has ports of both 100G and 400G; the second is to design two types of PHYs, one PHY is all 100G ports, and the other is all 400G ports.
Although the first solution considers both 100G and 400G ports, when the output requirements of the core switch ports are all 100G, the 400G port must be reduced to 100G for increasing the port utilization rate, which results in a huge waste of 300G bandwidth. The second method, although meeting the 100G and 400G port requirements of the core switch, increases the design and manufacturing cost and also increases the board management cost because 2 types of boards need to be designed.
Therefore, when the port design in the prior art considers both 100G and 400G bandwidth output, high bandwidth utilization rate and low design cost cannot be ensured at the same time.
Disclosure of Invention
The embodiment of the invention provides a bandwidth allocation device and a bandwidth allocation method, which are used for improving the bandwidth utilization rate of a port and reducing the design cost when both 100G bandwidth output and 400G bandwidth output are considered.
In a first aspect, an embodiment of the present invention provides a bandwidth distribution apparatus, where the apparatus includes: the system comprises a Media Access Controller (MAC), a first physical interface (PHY), a second PHY and a Central Processing Unit (CPU), wherein the first PHY and the second PHY are of the same type; the CPU is connected with the MAC;
the output interfaces H0-H7 of the MAC are respectively connected with host-side serial bus channels H0-H7 of the first PHY in a one-to-one correspondence manner; the line-side serial bus channels L8-L15 of the first PHY are connected with the host-side serial bus channels H0-H7 of the second PHY in a one-to-one correspondence manner;
the line side serial bus channels L0-L3 of the first PHY are packaged as a first port compatible with a four channel optical module; the line side serial bus channels L4-L7 of the first PHY are packaged into a second port that is compatible with a four channel optical module; the line side serial bus channels L0-L3 of the second PHY are packaged into a third port that is compatible with a four channel optical module; the line side serial bus channels L8-L15 of the second PHY are packaged into a fourth port compatible with the quad small pluggable dual density optical module and the quad optical module;
the MAC is used for outputting the bandwidth to be allocated;
the CPU is used for controlling the working modes of the first PHY and the second PHY;
the first PHY and the second PHY are used for allocating the bandwidth to be allocated and outputting.
In the above scheme, after the same bandwidth to be allocated is allocated by the apparatus, at least two bandwidths with different allocation modes can be output, and compared with a scheme in the prior art in which two different bandwidths are output by losing the bandwidth or two different bandwidths are output by using two different boards, the scheme can simultaneously ensure high bandwidth utilization rate and low design cost of the port.
Optionally, the CPU is specifically configured to: controlling the working mode of the first PHY to be a first working mode and the working mode of the second PHY to be a second working mode; the first working mode is any one of non-return-to-zero code NRZ-NRZ, pulse amplitude modulation PAM4to PAM4 or PAM4-NRZ, and the second working mode is any one of NRZ-NRZ, PAM4to PAM4 or PAM 4-NRZ.
In the above scheme, the CPU controls the operating modes of the first PHY and the second PHY to output different bandwidths, thereby realizing flexible adjustment of the bandwidth output mode.
Optionally, the bandwidth to be allocated is 400G; the first operating mode of the first PHY is: PAM4to PAM 4; the second operating mode of the second PHY is: PAM4to PAM 4; the output bandwidth of the first port is 0G, the output bandwidth of the second port is 0G, the output bandwidth of the third port is 0G, and the output bandwidth of the fourth port is 400G.
In the scheme, the port output of the 400G bandwidth is realized through the two same types of board cards, so that the bandwidth utilization rate is improved and the design cost is reduced compared with the prior art.
Optionally, the bandwidth to be allocated is 400G; the first operating mode of the first PHY is: PAM4to NRZ; the second operating mode of the second PHY is: NRZ to NRZ; the output bandwidth of the first port is 100G, the output bandwidth of the second port is 100G, the output bandwidth of the third port is 100G, and the output bandwidth of the fourth port is 100G.
In the above scheme, the port output of 4 100G bandwidths is realized through two boards of the same type, so that compared with the prior art, the bandwidth utilization rate is improved, and the design cost is reduced.
In a second aspect, an embodiment of the present invention provides a switch, including the bandwidth allocation apparatus described in the first aspect or any optional implementation manner of the first aspect.
In a third aspect, an embodiment of the present invention provides a bandwidth allocation method, which is applied to a bandwidth allocation apparatus, where the bandwidth allocation apparatus includes an MAC, a PHY, and a second PHY, and types of the first PHY and the second PHY are the same; the CPU is connected with the MAC; the output interfaces H0-H7 of the MAC are respectively connected with host-side serial bus channels H0-H7 of the first PHY in a one-to-one correspondence manner; the line-side serial bus channels L8-L15 of the first PHY are connected with the host-side serial bus channels H0-H7 of the second PHY in a one-to-one correspondence manner; the line side serial bus channels L0-L3 of the first PHY are packaged as a first port compatible with a four channel optical module; the line side serial bus channels L4-L7 of the first PHY are packaged into a second port that is compatible with a four channel optical module; the line side serial bus channels L0-L3 of the second PHY are packaged into a third port that is compatible with a four channel optical module; the line side serial bus channels L8-L15 of the second PHY are packaged into a fourth port compatible with the quad small pluggable dual density optical module and the quad optical module;
the method comprises the following steps:
controlling the MAC to output the bandwidth to be allocated;
controlling, by the CPU, operating modes of the first PHY and the second PHY;
and controlling the first PHY and the second PHY to be used for allocating the bandwidth to be allocated and outputting.
Optionally, controlling the operating modes of the first PHY and the second PHY by the CPU includes: controlling the working mode of the first PHY to be a first working mode and the working mode of the second PHY to be a second working mode by the CPU; the first work mode is any one of non-return-to-zero code NRZ-NRZ, pulse amplitude modulation PAM4to PAM4 or PAM4-NRZ, and the second PHY work mode is any one of NRZ-NRZ, PAM4to PAM4 or PAM 4-NRZ.
Optionally, controlling the MAC to output the bandwidth to be allocated includes: controlling the MAC to output 400G bandwidth to be allocated; controlling, by the CPU, a working mode of the first PHY to be a first working mode and a working mode of the second PHY to be a second working mode, including: by controlling the first operating mode of the first PHY to be PAM4to PAM4 and the second operating mode of the second PHY to be PAM4to PAM4, the output bandwidth of the first port is 0G, the output bandwidth of the second port is 0G, the output bandwidth of the third port is 0G, and the output bandwidth of the fourth port is 400G.
Optionally, controlling the MAC to output the bandwidth to be allocated includes: controlling the MAC to output 400G bandwidth to be allocated; controlling, by the CPU, a working mode of the first PHY to be a first working mode and a working mode of the second PHY to be a second working mode, including: by controlling the first operating mode of the first PHY to be PAM4to NRZ and the second operating mode of the second PHY to be NRZ to NRZ, the output bandwidth of the first port is 100G, the output bandwidth of the second port is 100G, the output bandwidth of the third port is 100G, and the output bandwidth of the fourth port is 100G.
The beneficial effects brought by the embodiments in the second aspect to the third aspect may be referred to the beneficial effects brought by the corresponding embodiments in the first aspect, and are not described in detail.
The invention has the following beneficial effects:
after the same bandwidth to be allocated is allocated by the device provided by the invention, at least two bandwidths with different allocation modes can be output, and compared with the scheme of outputting two different bandwidths by losing the bandwidth or outputting two different bandwidths by using two different board cards in the prior art, the scheme can simultaneously ensure the high bandwidth utilization rate and the low design cost of the port by using two same PHYs.
Drawings
Fig. 1 is a schematic structural diagram of a possible bandwidth allocation apparatus according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating the operation modes of a PHY according to an embodiment of the present invention;
fig. 3 is a device for implementing a bandwidth allocation method according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a bandwidth allocation device, which is used for realizing a port giving consideration to both 100G bandwidth output and 400G bandwidth output, improving the bandwidth utilization rate of the port and reducing the design cost.
The technical solutions of the present invention are described in detail below with reference to the drawings and the specific embodiments, and it should be understood that the specific features in the embodiments and the embodiments of the present invention are not intended to limit the technical solutions of the present invention, but may be combined with each other without conflict.
It is to be understood that the terms first, second, and the like in the description of the embodiments of the invention are used for distinguishing between the descriptions and not necessarily for describing a sequential or chronological order. "plurality" in the description of the embodiments of the present invention means two or more.
The term "and/or" in the embodiment of the present invention is only one kind of association relationship describing an associated object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
Referring now to fig. 1, a bandwidth distribution apparatus provided in an embodiment of the present application is described, the apparatus including: MAC101, first PHY102, second PHY103, and central processing unit CPU 113; the MAC101 is configured to output a bandwidth to be allocated, the first PHY102 and the second PHY103 are configured to allocate and output the bandwidth to be allocated, and the CPU113 is connected to the MAC 101.
The specific configuration of the above components and the connection relationship therebetween will be described below.
As shown in FIG. 1, MAC101 includes 8 output ports, namely H0-H7; the first PHY102 includes host-side serial bus lanes H0-H7 and line-side serial bus lanes L0-L15; the second PHY103 includes host-side serial bus lanes H0-H7 and line-side serial bus lanes L0-L15. Output ports H0-H7 of the MAC101 are respectively connected with host-side serial bus channels H0-H7 of the first PHY102 in a one-to-one correspondence manner; the line-side serial bus lanes L8-L15 of the first PHY102 are connected to the host-side serial bus lanes H0-H7 of the second PHY103 in a one-to-one correspondence. The first PHY102 and the second PHY103 are configured to allocate a bandwidth to be allocated and output the bandwidth.
MAC101 also includes a first control interface a1 and a second control interface B1; the first PHY102 also includes a first slave port a2 coupled to the first control interface; the second PHY103 also includes a second slave port B2 coupled to the second control interface; the first control interface, the second control interface, the first controlled port and the second controlled port may be Serial Management Interface (SMI) interfaces. Where MAC101 is used to output the bandwidth to be allocated. The CPU113 may transmit control instructions to the first PHY102 and the second PHY103 through the MAC101 to control the first PHY102 to be in the first operating mode and to control the second PHY103 to be in the second operating mode. Specifically, after the MAC101 receives a control instruction sent to the first PHY102 by the CPU112, the MAC101 forwards the control instruction to the first PHY102 through a channel between the first control interface a1 and the first controlled interface B1; after the MAC101 receives the control instruction sent by the CPU113 to the second PHY103, the MAC101 forwards the control instruction to the second PHY103 through a channel between the second control interface a2 and the second controlled interface B2.
With continued reference to FIG. 1, the line side serial bus channels L0-L3 of the first PHY102 are packaged into a first port 104 that is compatible with the first four-channel optical module 108; the line side serial bus channels L4-L7 of the first PHY102 are packaged into a second port 105 that mates with a second four-channel optical module 109; the line side serial bus channels L0-L3 of the second PHY103 are packaged into a third port 106 that is compatible with a third four-channel optical module 110; the line side serial bus channels L8-L5 of the second PHY103 are packaged to be compatible with the fourth ports 107 of the first and fourth quad small form-factor pluggable dual density optical modules 111 and 112. A first port 104, a second port 105, a third port 106, and a fourth port 107 for outputting the allocated bandwidth. In an embodiment of the present invention, the first PHY102 and the second PHY103 are of the same type. Wherein, the meaning of the type may include that the model and configuration (e.g., supported operation mode) of the first PHY102 and the second PHY103 are the same. The first PHY102 and the second PHY103 may differ only in the connection and encapsulation of the ports.
Further, the method for implementing bandwidth allocation based on the device includes: the CPU113 controls the operating mode of the first PHY to be the first operating mode, and controls the operating mode of the second PHY to be the second operating mode, so that the first port 104, the second port 105, the third port 106, or the fourth port 107 outputs bandwidths of different sizes under the condition that the bandwidth to be allocated input by the MAC101 is not changed.
In the above scheme, after the same bandwidth to be allocated is allocated by the apparatus, at least two bandwidths with different allocation modes can be output, and compared with a scheme in the prior art in which two different bandwidths are output by losing the bandwidth or two different bandwidths are output by using two different boards, the scheme can simultaneously ensure the bandwidth utilization rate of the port and low design cost.
Optionally, in an implementation of the present invention, referring to fig. 2, the operating modes supported by the PHY in this embodiment of the present invention include three types, i.e., 4pulse amplitude modulation (PAM 4) -PAM4, non-return to zero (NRZ) -NRZ, and PAM 4-NRZ.
The operation mode of the first PHY102 may be any one of the three operation modes, and the operation mode of the second PHY103 may be any one of the three operation modes, which will be explained below with reference to the operation mode of the PHY shown in fig. 2.
PAM4 is a modulation mode for 50G bandwidth signals, which will make the host side serial bus channel or line side serial bus channel of PHY pass 50G bandwidth; NRZ is the modulation mode for a 25G bandwidth signal that will cause the host-side serial bus channel or the line-side serial bus channel of the PHY to pass 25G of bandwidth.
When the PHY operating mode is PAM4-PAM4, host-side serial bus channels H0-H7 on the PHY perform bandwidth input, and line-side serial bus channels L8-L15 perform bandwidth output as one output port.
When the PHY operating mode is NRZ-NRZ, the host-side serial bus lanes H0-H7 on the PHY perform bandwidth input, the line-side serial bus lanes L0-L3 perform bandwidth output as one output port, and the line-side serial bus lanes L8-L11 perform bandwidth output as the other output port.
When the PHY operating mode is PAM4-NRZ, host-side serial bus channels H0-H7 on the PHY perform bandwidth input, line-side serial bus channels L0-L3 perform bandwidth output as one output port, line-side serial bus channels L4-L7 perform bandwidth output as one output port, line-side serial bus channels L8-L11 perform bandwidth output as another output port, and line-side serial bus channels L12-L15 perform bandwidth output as one output port.
In the following, taking the bandwidth to be allocated as 400G as an example, the scheme for allocating the bandwidth to the above apparatus is further explained with reference to a specific example. It should be noted that, the MAC101 actually outputs 8 bandwidths of 50G, so the total bandwidth to be allocated is 400G.
Example 1
The CPU113 sends a first control command to the first slave interface B1 of the first PHY102 through the first control interface a1, so that the first PHY102 operates in the first operating mode (PAM4to PAM4), and sends a second control command to the second slave interface B2 of the second PHY103 through the second control interface a2, so that the second PHY103 operates in the second operating mode (PAM4to PAM 4). The host-side serial bus channels H0 to H7 of the first PHY respectively input 50G bandwidths to be allocated, which are respectively output by 8 output interfaces of the MAC.
Based on the above description of fig. 2, when the PHY operates in PAM4to PAM4, the line-side serial bus channels L8 to L15 of the PHY operate. Therefore, the first port 104 and the second port 105 of the line-side serial bus channel of the first PHY102 do not output, which corresponds to the first port 104 and the second port 105 outputting 0G, and each of the line-side serial bus channels L8 through L15 of the first PHY102 outputs 50G of bandwidth, which is input to the host-side serial bus channels H0 through H7 of the second PHY103, and then outputs a total of 400G of bandwidth from the line-side serial bus channels L8 through L15 of the second PHY103, which corresponds to the second PHY103 line-side serial bus channel L0 through L3 which does not output, which corresponds to the output bandwidth of 0G. Therefore, the optical signal transmission with the bandwidth of 400G of one port can be performed by packaging the optical signal into the fourth port 107 compatible with the first four-channel small-sized pluggable dual-density optical module 111 and the fourth four-channel optical module 112 through L8-L15, and finally inserting the fourth four-channel small-sized pluggable dual-density optical module 111 into the port.
Thus, a 400G bandwidth port output is realized.
Example 2
The CPU113 transmits a third control command to the first controlled interface B1 of the first PHY102 through the first control interface a1 to operate the first PHY102 in the first operation mode (PAM4to NRZ), and transmits a fourth control command to the second controlled interface B2 of the second PHY103 through the second control interface a2 to operate the second PHY103 in the second operation mode (NRZ to NRZ). The host-side serial bus lanes H0 to H7 of the first PHY102 respectively input 50G bandwidths output by the 8 output interfaces of the MAC 101.
Based on the above description of fig. 2, when the PHY operates at PAM4to NRZ, the line-side serial bus channels L0 to L15 of the PHY all operate, and when the PHY operates at NRZ to NRZ, the line-side serial bus channels L0 to L3 and L8 to L11 of the PHY operate. Therefore, by encapsulating the line-side serial bus channels L0-L3 of the first PHY102 into the first port 104 adapted to the first four-channel optical module 108, encapsulating the line-side serial bus channels L4-L7 of the first PHY102 into the second port 109 adapted to the second four-channel optical module 105, and inserting the first four-channel optical module 108 and the second four-channel optical module 109 into the first port 104 and the second port 109, respectively, both the first port 104 and the second port 105 can perform 100G bandwidth optical signal transmission.
Further, L8-L15 of the line-side serial bus channel of the first PHY102 is connected to the host-side serial bus channels H0 to H7 of the second PHY103 one by one, and by encapsulating the line-side serial bus channels L0 to L3 of the second PHY103 into the third port 106 adapted to the third four-channel optical module 110 and inserting the third four-channel optical module 110 into the third port, the third port 106 can perform optical signal transmission with a bandwidth of 100G. The port-side serial bus channels L8-L15 of the second PHY103 are packaged into the fourth port 107 compatible with the first four-channel small pluggable dual-density optical module 111 and the fourth four-channel optical module 112, and the four-channel optical module 112 is inserted into the port, so that the optical signal transmission with the bandwidth of 100G can be performed.
Thus, four 100G bandwidth port outputs can be realized.
As can be seen from the two examples above: the output 400G bandwidth of the MAC101 may be allocated differently by the CPU113 through inputting different instructions, for example, output by 4 ports of 100G or output by 1 port of 400G, which ensures 100% utilization of the port bandwidth and saves the design cost of the board card.
It should be noted that, the foregoing embodiment of the present invention mainly takes 400G bandwidth allocation as an example, and when the present invention is applied specifically, bandwidth allocation of bandwidths to be allocated in other sizes, such as 800G bandwidth, 1600G bandwidth, and the like, may also be implemented, which is not limited herein. To meet such requirements, the PHY may have some variation, e.g., in model, configuration, supported modes, etc. However, it is also within the scope of the present invention to combine at least two identical PHYs and to control the change of the operating modes of at least two identical PHYs to implement bandwidth allocation in different ways to obtain the output effect of different port bandwidths.
Based on the same inventive concept, an embodiment of the present invention further provides an apparatus 300 for implementing a bandwidth allocation method, as shown in fig. 3, including:
a control module 301, configured to control the MAC to output a bandwidth to be allocated; controlling, by the CPU, operating modes of the first PHY and the second PHY; and controlling the first PHY and the second PHY to be used for allocating the bandwidth to be allocated and outputting.
Optionally, when the CPU controls the working modes of the first PHY and the second PHY, the control module 301 is specifically configured to: controlling the working mode of the first PHY to be a first working mode and the working mode of the second PHY to be a second working mode; the first working mode is any one of non-return-to-zero code NRZ-NRZ, pulse amplitude modulation PAM4to PAM4 or PAM4-NRZ, and the second working mode is any one of NRZ-NRZ, PAM4to PAM4 or PAM 4-NRZ.
Optionally, the control module 301 controls the MAC to output a bandwidth to be allocated, which is specifically configured to: controlling the MAC to output 400G bandwidth to be allocated; controlling a first operating mode of the first PHY to be PAM4to PAM 4; and controlling a second operation mode of the second PHY to be PAM4to PAM4, so that the output of the first port is 0G, the output of the second port is 0G, the output of the third port is 0G, and the output of the fourth port is 400G.
Optionally, the control module 301 controls the MAC to output a bandwidth to be allocated, which is specifically configured to: controlling the MAC to output 400G bandwidth to be allocated; controlling a first operating mode of the first PHY to be PAM4to NRZ; controlling a second operation mode of the second PHY to be NRZ to NRZ, and finally making an output of the first port to be 100G, an output of the second port to be 100G, an output of the third port to be 100G, and an output of the fourth port to be 100G.
Based on the same inventive concept, embodiments of the present invention further provide a computer-readable storage medium, where computer instructions are stored, and when the computer instructions are executed on a computer, the computer is caused to execute the bandwidth allocation method according to the embodiments of the present invention.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (9)
1. A bandwidth allocation device is characterized by comprising a Media Access Controller (MAC), a first physical interface (PHY) transceiver, a second PHY and a Central Processing Unit (CPU), wherein the first PHY and the second PHY are of the same type; the CPU is connected with the MAC;
the output interfaces H0-H7 of the MAC are respectively connected with host-side serial bus channels H0-H7 of the first PHY in a one-to-one correspondence manner; the line-side serial bus channels L8-L15 of the first PHY are connected with the host-side serial bus channels H0-H7 of the second PHY in a one-to-one correspondence manner;
the line side serial bus channels L0-L3 of the first PHY are packaged as a first port compatible with a four channel optical module; the line side serial bus channels L4-L7 of the first PHY are packaged into a second port that is compatible with a four channel optical module; the line side serial bus channels L0-L3 of the second PHY are packaged into a third port that is compatible with a four channel optical module; the line side serial bus channels L8-L15 of the second PHY are packaged into a fourth port compatible with the quad small pluggable dual density optical module and the quad optical module;
the MAC is used for outputting the bandwidth to be allocated;
the CPU is used for controlling the working modes of the first PHY and the second PHY;
the first PHY and the second PHY are used for allocating the bandwidth to be allocated and outputting.
2. The apparatus of claim 1, wherein the CPU is specifically configured to:
controlling the working mode of the first PHY to be a first working mode and the working mode of the second PHY to be a second working mode;
the first working mode is any one of non-return-to-zero code NRZ-NRZ, pulse amplitude modulation PAM4to PAM4 or PAM4-NRZ, and the second working mode is any one of NRZ-NRZ, PAM4to PAM4 or PAM 4-NRZ.
3. The apparatus of claim 2, wherein the bandwidth to be allocated is 400G;
the first operating mode of the first PHY is: PAM4to PAM 4;
the second operating mode of the second PHY is: PAM4to PAM 4;
the output bandwidth of the first port is 0G, the output bandwidth of the second port is 0G, the output bandwidth of the third port is 0G, and the output bandwidth of the fourth port is 400G.
4. The apparatus of claim 2, wherein the bandwidth to be allocated is 400G;
the first operating mode of the first PHY is: PAM4to NRZ;
the second operating mode of the second PHY is: NRZ to NRZ; the output bandwidth of the first port is 100G, the output bandwidth of the second port is 100G, the output bandwidth of the third port is 100G, and the output bandwidth of the fourth port is 100G.
5. A switch, characterized in that it comprises a bandwidth allocation arrangement according to any one of claims 1-4.
6. A bandwidth allocation method is applied to a bandwidth allocation device, and is characterized in that the bandwidth allocation device comprises an MAC, a first PHY, a second PHY and a CPU, and the first PHY and the second PHY are of the same type; the CPU is connected with the MAC; the output interfaces H0-H7 of the MAC are respectively connected with host-side serial bus channels H0-H7 of the first PHY in a one-to-one correspondence manner; the line-side serial bus channels L8-L15 of the first PHY are connected with the host-side serial bus channels H0-H7 of the second PHY in a one-to-one correspondence manner; the line side serial bus channels L0-L3 of the first PHY are packaged as a first port compatible with a four channel optical module; the line side serial bus channels L4-L7 of the first PHY are packaged into a second port that is compatible with a four channel optical module; the line side serial bus channels L0-L3 of the second PHY are packaged into a third port that is compatible with a four channel optical module; the line side serial bus channels L8-L15 of the second PHY are packaged into a fourth port compatible with the quad small pluggable dual density optical module and the quad optical module;
the method comprises the following steps:
controlling the MAC to output the bandwidth to be allocated;
controlling, by the CPU, operating modes of the first PHY and the second PHY;
and controlling the first PHY and the second PHY to be used for allocating the bandwidth to be allocated and outputting.
7. The method of claim 6, wherein controlling, by the CPU, the operating modes of the first PHY and the second PHY comprises:
controlling the working mode of the first PHY to be a first working mode and the working mode of the second PHY to be a second working mode by the CPU; the first operation mode is any one of non-return-to-zero code NRZ-NRZ, pulse amplitude modulation PAM4to PAM4 or PAM4-NRZ, and the second PHY operation mode is any one of NRZ-NRZ, PAM4to PAM4 or PAM 4-NRZ.
8. The method of claim 7, wherein controlling the MAC to output the bandwidth to be allocated comprises:
controlling the MAC to output 400G bandwidth to be allocated;
controlling, by the CPU, a working mode of the first PHY to be a first working mode and a working mode of the second PHY to be a second working mode, including:
the first operation mode of the first PHY is controlled to be PAM4to PAM4, and the second operation mode of the second PHY is controlled to be PAM4to PAM4, so that the output bandwidth of the first port is 0G, the output bandwidth of the second port is 0G, the output bandwidth of the third port is 0G, and the output bandwidth of the fourth port is 400G.
9. The method of claim 7, wherein controlling the MAC to output the bandwidth to be allocated comprises:
controlling the MAC to output 400G bandwidth to be allocated;
controlling, by the CPU, a working mode of the first PHY to be a first working mode and a working mode of the second PHY to be a second working mode, including:
by controlling the first operating mode of the first PHY to be PAM4to NRZ and the second operating mode of the second PHY to be NRZ to NRZ, the output bandwidth of the first port is 100G, the output bandwidth of the second port is 100G, the output bandwidth of the third port is 100G, and the output bandwidth of the fourth port is 100G.
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| EP2111055A1 (en) * | 2008-04-17 | 2009-10-21 | Nokia Siemens Networks Oy | Extended queue polling mechanism for ITU G.984 GPON system |
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| US20030163593A1 (en) * | 2002-02-25 | 2003-08-28 | William March Rice University | Method and system for implementing a fair, high-performance protocol for resilient packet ring networks |
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| CN1356012A (en) * | 1999-05-21 | 2002-06-26 | 通信集合公司 | Method and apparatus for bandwidth allocation |
| WO2001063855A1 (en) * | 2000-02-25 | 2001-08-30 | Telefonaktiebolaget Lm Ericsson (Publ) | Packet scheduling in umts using several calculated transfer rates |
| CN101127721A (en) * | 2007-09-13 | 2008-02-20 | 杭州华三通信技术有限公司 | Bandwidth control method and bandwidth control device |
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