CN110956996A

CN110956996A - Semiconductor device with a plurality of semiconductor chips

Info

Publication number: CN110956996A
Application number: CN201811122609.0A
Authority: CN
Inventors: 冈部翔
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2018-09-26
Filing date: 2018-09-26
Publication date: 2020-04-03
Anticipated expiration: 2038-09-26
Also published as: CN110956996B

Abstract

The present invention provides a semiconductor device having a function of generating intrinsic data by a new method. The NAND flash memory of the present invention comprises: a NAND flash memory includes a memory cell array, a page buffer/sense circuit, and a differential sense amplifier for detecting a potential difference between a bit line pair of a dummy array when the dummy array of the memory cell array is read out, wherein the NAND flash memory outputs data unique to a semiconductor device based on a detection result of the differential sense amplifier. The invention can maintain the reproducibility and reliability of the semiconductor device and ensure the randomness of the inherent data.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

The present invention relates to a semiconductor device having a function of generating intrinsic data, and more particularly to a semiconductor device for generating intrinsic data using a NAND flash memory.

Background

With the enhancement of electronic devices or the security of electronic devices, there is a need for a solution to prevent counterfeiting or forgery of semiconductor devices that are physically mounted on the devices. In either method, when the unique data is given to the semiconductor device and the unique data is verified, the semiconductor device can be regarded as a genuine product and allowed to be used. The unique data can be stored in, for example, a nonvolatile memory of the semiconductor device, but this method involves a risk of analyzing the semiconductor device and reading the unique data, or of unauthorized access to the semiconductor device from the outside and reading the unique data.

In recent years, physically uncloneable pufs (physical Unclonable functions) have attracted considerable attention. A PUF is a technique that uses physical data that is unpredictable, highly confidential, and persistent as intrinsic data. For example, PUFs using an arbiter circuit, PUFs using a ring oscillator, PUFs using a static random-Access Memory (SRAM), and the like have been proposed. Further, a PUF using erase verification (patent document 1), a PUF using a voltage adjustment unit (patent document 2), or the like is disclosed in a NAND (NAND) flash memory.

Documents of the prior art

Patent document 1: U.S. Pat. No. 2015/0007337A1

Patent document 2: U.S. Pat. No. 2015/0055417A1

In designing and manufacturing a semiconductor device, a semiconductor device having high reproducibility and reliability is provided by suppressing unevenness (variation) of circuit elements, wirings, and the like or minimizing the unevenness. On the other hand, minimizing the nonuniformity of circuit elements, wirings, and the like may bring uniformity to the circuit elements or the wirings, and may reduce the randomness (unpredictability) of the PUF or intrinsic data. Therefore, a PUF technique is desired that can ensure randomness of unique data while maintaining reproducibility and reliability.

An object of the present invention is to provide a semiconductor device having a function of generating intrinsic data by a new method.

Disclosure of Invention

The semiconductor device of the present invention includes: a memory array comprising NAND type strings; a selection means for selecting a specific region of the memory array; a reading means for reading the specific region selected by the selecting means; a detecting means for detecting a potential difference of the bit line pair in the specific region read by the reading means; and a generating means for generating the data specific to the semiconductor device based on the detection result of the detecting means.

According to the present invention, since the unique data is outputted based on the detection result of the potential difference of the bit line pair in the specific region read out from the memory cell array, the randomness of the unique data can be maintained while the reproducibility or reliability of the semiconductor device is maintained.

Drawings

Fig. 1 shows the structure of a NAND flash memory according to an embodiment of the present invention.

FIG. 2 shows an architecture of NAND strings of a memory cell array according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a bit line selection circuit according to an embodiment of the present invention.

Fig. 4 is a diagram illustrating an example of a page buffer/sensing circuit according to an embodiment of the present invention.

Fig. 5 is an example of an intrinsic data generation circuit according to an embodiment of the present invention.

FIG. 6 is a table showing bias voltages applied during the operation of a NAND flash memory according to one embodiment of the present invention.

FIG. 7 is a flowchart of the actions of intrinsic data generation provided by an embodiment of the present invention.

Fig. 8 is a diagram illustrating an example of a virtual array according to an embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of word line voltages applied to a dummy array according to an embodiment of the present invention.

Fig. 10 is a modification of the unique data generating circuit according to the embodiment of the present invention.

Description of the symbols:

100 flash memory BLK memory block

110 memory cell array BLS bit line select transistor

120 output/input buffer BLCD transistor

130 address register BLCLAMP transistor

140 controller BLPRE transistor

150 word line selection circuit Dout _ i intrinsic data

160 paging buffer/sensing circuit GBL _ e even bit line

170 row selection circuit GBL _ o odd bit line

180 internal voltage generating circuit MCi memory cell

200 bit line selection circuit SEL _ e even number selection transistor

300 inherent data generating circuit SEL _ o odd number selecting transistor

310 differential sense amplifier LAT latch circuit

320 compute circuit NU NAND string

Drain side bit line selection transistor of PB _ i page buffer TR1

SGD select gate line TR2 source side bit line select transistor

SGS select gate line WLi word line

SNS sensing node YSEL _ e even-numbered bias selection transistor

SL source line YSEL _ o odd-biased selection transistor

VPRE virtual potential

Detailed Description

Next, embodiments of the present invention are described with reference to the drawings. The semiconductor device of the present invention has a function of generating unique data unique to the semiconductor device and outputting the data to the outside. In one embodiment, the semiconductor device of the present invention includes a NAND flash memory, and data inherent to the NAND flash memory is generated and output to the outside. The semiconductor device of the present invention may be a NAND flash memory itself, or may be a semiconductor circuit having other functions.

[ examples ]

Fig. 1 shows the structure of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 of the present embodiment includes: a memory cell array 110 formed of a plurality of memory cells arranged in rows and columns; an input/output buffer 120 connected to the external input/output terminal I/O and holding input/output data; an address register 130 for receiving address data from the input/output buffer 120; a controller 140 for controlling each unit based on command data from the i/o buffer 120 and an external control signal (CLE, address latch, ALE, or the like); a word line selection circuit 150 for selecting a block and a page based on row address data Ax from the address register 130; a page buffer/sensor 160 holding data read out from the selected page and holding data to be programmed to the selected page; a column selection circuit 170 for selecting data in the page buffer/sensing circuit 160 based on column address data Ay from the address register 130; the internal voltage generation circuit 180 generates voltages (a write voltage Vpgm, a pass voltage Vpass, an erase voltage Vers, a read voltage Vread, and the like) necessary for reading, programming, erasing, and the like of data.

The memory cell array 110 has m memory blocks BLK (0), BLK (1), …, and BLK (m-1) in the row direction, and one memory block is formed with a plurality of NAND strings as shown in fig. 2. One NAND string includes a plurality of memory cells MCi (i ═ 0, 1, …, 62, 63) connected in series, a bit line selection transistor TR1 connected to the drain side of the memory cell MC63, and a source line selection transistor TR2 connected to the source side of the memory cell MC 0. The control gates of the memory cells MCi are connected to the corresponding word line WLi, the gates of the bit line side select transistors TR1 are connected to the select gate line SGD, and the gate of the source line side select transistor TR2 is connected to the select gate line SGS. In each operating state, the word line selection circuit 150 selectively drives the select gate transistors TR1 and TR2 in response to the select gate signals SGD and SGS based on the column address data Ax.

The NAND string may be in a 2-dimensional array formed on the surface of the substrate or in a 3-dimensional array using a semiconductor layer formed on the surface of the substrate. Also, one memory cell may be in the form of a Single Level Cell (SLC) storing one bit (binary data) or in the form of a multi-level cell (MLC) storing a plurality of bits.

Each NAND string of each block is connected to global bit lines GBL0, GBL1, … GBLn through bit line select transistor TR1, and global bit lines GBL0, GBL1, … GBLn are connected to page buffer/sense circuit 160. Each of the global bit lines is formed of, for example, a metal wiring, and extends from memory block BLK (0) of memory cell array 110 toward memory block BLK (m-1).

Next, the page buffer 160 will be described. The page buffer 160 includes a bit line selection circuit 200 for selecting an even-numbered general bit line or an odd-numbered general bit line, as shown in fig. 3. Fig. 3 shows a pair of general bit lines including an even bit line GBL _ e connected to one NAND string NU and an odd bit line GBL _ o connected to one NAND string NU. The bit line selection circuit 200 selects the even bit line GBL _ e or the odd bit line GBL _ o during reading or programming, and electrically connects the selected even bit line GBL _ e or the selected odd bit line GBL _ o to the sensing circuit (sensing node SNS) of the page buffer/sensing circuit 160. That is, although the page buffer/sensing circuit 160 corresponds to one page, one page buffer/sensing circuit 160 is shared by a pair of even bit line GBL _ e and odd bit line GBL _ o.

The bit line selection circuit 200 includes: a bit line selection transistor BLS electrically connected to the sense node SNS at the time of readout; an even selection transistor SEL _ e connected in series between the node N1 of the bit line selection transistor BLS and the even bit line GBL _ e; an odd select transistor SEL _ o connected in series between the node N1 of the bit line select transistor BLS and the odd bit line GBL _ o; an even-numbered bias selection transistor YSEL _ e connected between the even-numbered bit line GBL _ e and the virtual potential VPRE; and an odd-numbered bias selection transistor YSEL _ o connected between the odd-numbered bit line GBL _ o and the virtual potential VPRE.

The bit line select transistor BLS, the even select transistor SEL _ e, the odd select transistor SEL _ o, the even bias select transistor YSEL _ e, and the odd bias select transistor YSEL _ o are formed of NMOS transistors, and control signals from the connector 140 are applied to the gates thereof. The virtual potential VPRE is supplied with various bias voltages or precharge voltages according to the operation state by the internal voltage generating circuit 180 under the control of the controller 140.

For example, in the read operation, when reading an even page, the even select transistor SEL _ e and the bit line select transistor BLS are turned on, the odd select transistor SEL _ o is turned off, the even bit line GBL _ e is selected, and the odd bit line GBL _ o is not selected. Further, the even bias selection transistor YSEL _ e is turned off, the odd bias selection transistor YSEL _ o is turned on, and the unselected odd bit line GBL _ o is supplied from the supply virtual potential VPRE to the ground terminal. On the other hand, when reading an odd page, the odd select transistor SEL _ o and the bit line select transistor BLS are turned on, the even select transistor SEL _ e is turned off, the odd bit line GBL _ o is selected, and the even bit line GBL _ e is not selected. Further, odd-numbered bias selection transistor YSEL _ o is turned off, even-numbered bias selection transistor YSEL _ e is turned on, and unselected even-numbered bit line GBL _ e is supplied from the supply virtual potential VPRE to the ground terminal. In this way, the bit line mask read for the even page and the odd page is performed.

In addition, during programming, even page and odd page are alternately programmed, and the unselected page is supplied with voltage for suppressing program disturb by virtual potential VPRE.

Fig. 4 shows an example of a page buffer/sensing circuit 160 according to an embodiment of the present invention. The construction of the page buffer/sensing circuit 160 includes: a transistor BLPRE for precharging the voltage supplied from the voltage supply section V1 to the bit line; a transistor BLCLAMP for clamping the bit line; a sense node SNS; a transistor BLCD for transferring charge between the sensing node SNS and the latch node N2; and a latch circuit connected to the latch node N2. The transistor BLCLAMP is connected to a bit line select transistor BLS of the bit line select circuit 200.

In the read operation, the precharge voltage supplied from voltage supply unit V1 is applied to even bit line GBL _ e or odd bit line GBL _ o selected by bit line selection circuit 200 via transistors BLPRE and BLCLAMP. Then, when the memory cell of the selected word line is turned on by applying the read voltage to the selected word line and applying the read pass voltage to the unselected word line, the precharge voltage of the global bit line is discharged to the source line SL, and the sense node SNS becomes the ground level. When the memory cell is turned off, the bit line is isolated from the source line SL, and the sense node SNS is maintained at the precharge voltage. The charge of the sensing node SNS is transferred to the node N2 through the transistor BLCD, and the latch circuit LAT is maintained at a high or low level by the potential of the node N2.

Fig. 5 shows an example of the unique data generating circuit according to the present embodiment. The unique data generating circuit 300 is connected to the page buffer/sense circuit 160, and when a specific region of the memory cell array 110 is read out, detects a potential difference of the sense node connected to the adjacent pair of the common bit lines, and generates and outputs unique data using the detection result.

Specifically, the intrinsic data generating circuit 300 includes a differential sense amplifier 310_0 connected to adjacent page buffers PB _0 and PB _1, differential sense amplifiers 310_1 and … connected to adjacent page buffers PB _2 and PB _3, and differential sense amplifiers 310_ n-1/2 (collectively, differential amplifiers are referred to as differential amplifiers 310) connected to adjacent page buffers PB _ n-1 and PB _ n. If the number of page buffer/sense circuits 160 is one page, the number of differential sense amplifiers 310 is 1/2 pages.

The differential sense amplifier 310_0 detects a potential difference between the sense node SNS _0 of the page buffer PB _0 and the sense node SNS _1 of the adjacent page buffer PB _1, and outputs data Dout _0 indicating the detection result. Similarly, the other differential sense amplifiers 310 detect the potential difference between the sense nodes of the adjacent page buffers, and output data Dout _1, …, Dout _ n-1/2 indicating the detection results. When an even bit line is selected by the bit line selection circuit 200, the differential sense amplifier 310 detects a potential difference of a sense node connected to an adjacent even bit line, and when an odd bit line is selected by the bit line selection circuit 200, the differential sense amplifier 310 detects a potential difference of a sense node connected to an adjacent odd bit line. The differential sense amplifier 310 is activated by the controller 140 when intrinsic data is generated.

Fig. 6 is a table showing an example of bias voltages applied in each operation of the flash memory. In the read operation, a positive voltage is applied to the bit line, a read voltage (e.g., 0V) is applied to the selected word line, a read pass voltage Vpass (e.g., 4.5V) is applied to the unselected word line, a positive voltage (e.g., 4.5V) is applied to the select gate lines SGD and SGS, the bit line side select transistor and the source line side select transistor of the NAND string are turned on, and 0V is applied to the common source line. In the programming (writing) operation, a high-voltage programming voltage Vpgm (15-20V) is applied to a selected word line, an intermediate potential (e.g., 10V) is applied to an unselected word line, a bit line side selection transistor is turned on, a source line side selection transistor is turned off, and a potential corresponding to data of "0" or "1" is supplied to a bit line. In the erase operation, 0V is applied to the selected word line in the block, and a high voltage (e.g., 20V) is applied to the P-well to extract electrons from the floating gate onto the substrate, thereby erasing data in units of blocks. The bias voltage when the intrinsic data is generated will be described later.

Next, the operation of generating the unique data of the NAND flash memory of the present embodiment will be described. FIG. 7 is a flowchart for explaining the operation of generating intrinsic data. The controller 140 is composed of a microcomputer or a state machine capable of executing a software program, for example. The controller 140 controls the generation of unique data in addition to the control of the general read operation, program operation, and erase operation in accordance with an external control signal or an external command.

In a certain embodiment, the controller 140 has a function of determining whether generation of intrinsic data is to be performed (S100). For example, when the controller 140 receives an instruction from the outside to generate the unique data, the unique data is generated. Alternatively, the controller 140 may generate the unique data when executing a boot program during power loading or when executing a predetermined operation.

When the controller 140 determines that the generation of the unique data is to be performed, the read of the dummy array of the memory cell array 110 is started by the word line selection circuit 150 (S110). The dummy array is a specific area of the memory cell array suitable for generating intrinsic data, and address data for selecting the dummy array in advance is stored in a memory of the controller 140. In one embodiment, the dummy array is set at or near the block BLK (m-1) farthest from the page buffer/sense circuit 160 as shown in fig. 8. In other words, the dummy array DA is a region in which the wiring length of the universal bit line connecting the block to the page buffer/sense circuit 160 is the longest. The virtual array DA may be a region that cannot be accessed by the user, or may be a region that uses a memory that can be accessed by the user.

Since the wiring length of the global bit line is longer in the farthest block BLK (m-1) than in the other blocks, the wiring unevenness (for example, the line width, film thickness, pitch, etc.) greatly affects the wiring time constant RC (resistance-capacitance). Therefore, a large difference in charge/discharge characteristics is likely to occur between adjacent bit lines.

In the readout of the dummy array DA, as in the general readout, the even bit lines or the odd bit lines selected by the bit line selection circuit 200 are precharged, and the odd bit lines or the even bit lines not selected are supplied to the ground. After the precharge, the word line selection circuit 150 applies a pass voltage Vpuf, which does not depend on the memory state of the memory cell and turns on the memory cell, to all the word lines of the block selected as the dummy array DA. That is, the pass voltage Vpuf is, as shown in fig. 9, much higher than the threshold value when the erase memory cell (data "1") and the Program (PGM) memory cell (data "0") are turned on. The pass voltage Vpuf may be at the same level as the pass voltage applied to the word line not to be selected in the read operation (see fig. 6).

The pass voltage Vpuf is applied to the dummy array DA, so that all the memory cells of the dummy array DA are turned on, and the precharge voltage of the global bit lines, i.e., the voltage of the sense node SNS is discharged to the source line SL at the ground level through the NAND strings. Simultaneously with the sensing, the potential difference of the adjacent bit line pair is detected by the differential sense amplifier 300 connected to the sense node SNS (S120). For example, when SNSk > SNSk +1, the differential sense amplifier 300 outputs "0" as Dout _ k; when SNSk ≦ SNSk +1, the differential sense amplifier 300 outputs "1" as Dout _ k.

The controller 140 detects a potential difference between the bit line pair by reading the dummy array DA, and outputs unique data to the outside based on the detection result (S130). When the unique data is generated, the dummy array DA may be read by either the even bit lines or the odd bit lines, or by both the even bit lines and the odd bit lines. The method of outputting the unique data is arbitrary, and for example, all the detected data may be output, or the data of the bit line or the number of bits predetermined by the row selection circuit 170 may be output. In addition, the number of bits of the unique data to be outputted may be adjusted in accordance with the input/output terminal of the NAND flash memory. In addition, the NAND flash memory has an spi (serial Peripheral interface) function. The intrinsic data can be output in synchronization with the external sequence clock.

According to the present embodiment, since the potential difference of the bit line pair is detected at the time of reading the dummy array and the intrinsic data of the semiconductor device is generated, the unpredicted intrinsic data with high reproducibility can be obtained by a relatively simple structure.

Next, another embodiment of the present invention will be described. Fig. 10 shows a configuration of an intrinsic data generating circuit 300A according to another embodiment. In this embodiment, the intrinsic data generating circuit 300A includes a calculating circuit 320 for receiving the output data Dout _0, Dout _1, …, Dout _ n-1/2 of the plurality of differential sense amplifiers 310_0, 310_1, …, 300_ n-1/2 and calculating the data. The calculation circuit 320 may, for example, mask (mask) a part of the output data of the differential sense amplifier 310, encode (compress) the output data, or logically operate the output data of the even bits and the output data of the odd bits and output the result as the intrinsic data Dout _ x.

In the above embodiment, when the unique data is generated, the pass voltage is applied to all word lines of the dummy array DA to perform reading, but only a specific page of the dummy array DA may be read. Any page of WL0 to WL63 can be set for a specific page, and the same read voltage (e.g., 0V) as that in normal reading is applied to the selected word line of the specific page, and the pass voltage Vpuf (e.g., 4.5V) is applied to the unselected word lines. In this case, the memory cells of a particular page need to be set as erased memory cells storing data "1". Therefore, the reading for generating the unique data can be performed under the same bias condition as the general reading operation.

In the above embodiment, the differential sense amplifier 310 detects the potential difference between the adjacent bit lines at the time of reading, but this is merely an example, and other embodiments are possible. For example, the differential sense amplifier 310 may detect the potential difference between each sensing node of the even-numbered page buffers/sensing circuits and each sensing node of the odd-numbered page buffers/sensing circuits, or may detect the potential difference between each sensing node of the selected page buffers/sensing circuits according to a predetermined rule.

In the above embodiment, the page buffer/sense circuit 160 corresponds to 1 page, and the differential sense amplifier 310 corresponds to 1/2 pages, but the number of the differential sense amplifiers 310 is arbitrary, and may be a number smaller than 1/2 pages as long as non-predictability (randomness) as intrinsic data can be obtained.

In the above embodiment, the example of the mask reading of the even bit line or the odd bit line selected by the bit line selection circuit is shown, but the mask reading is not essential in the present invention. In this case, the page is selected and read out on all the bit lines, and the differential sense amplifier can detect the potential difference between the physically adjacent even bit line and odd bit line.

In the above embodiment, the memory cells are exemplified as the cells connected to the word lines of the dummy array DA, but in the present invention, general MOS transistors may be used instead of the memory cells. That is, a part or all of the memory cells constituting the NAND strings of the dummy array DA may be replaced with general MOS transistors. Here, the general MOS transistor refers to a MOS transistor whose threshold value does not vary when turned on due to programming or erasing. Representative MOS transistors include a drawing type, an enhancement type, and an intrinsic type, and readout for generating intrinsic data can be performed by using any MOS transistor instead of a memory cell.

Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various changes and modifications can be made within the scope of the gist of the present invention described in the claims.

Claims

1. A semiconductor device, comprising:

a memory array comprising NAND type strings;

a selection means for selecting a specific region of the memory array;

a reading means for reading the specific region selected by the selecting means;

a detecting means for detecting a potential difference of the bit line pair in the specific region read by the reading means; and

and a generating means for generating the data specific to the semiconductor device based on the detection result of the detecting means.

2. The semiconductor device of claim 1, wherein the specific area is a block physically farthest from the readout member.

3. The semiconductor device of claim 1, wherein the specific area is a page included in a block physically farthest from the sensing means.

4. The semiconductor device of claim 1, wherein the specific domain is a domain that is inaccessible to a user.

5. The semiconductor device according to claim 1, wherein the specific field is a MOS transistor connected to a NAND-type string.

6. A semiconductor device as claimed in claim 2 or 3, wherein the selection means applies a voltage to all word lines within the selected block that is independent of the memory state of the memory cell and turns on the memory cell.

7. The semiconductor device as claimed in any one of claims 1 to 5, wherein the detecting means is electrically connected to a sensing node of the sensing means, the detecting means comprising a differential sense amplifier for detecting a potential difference of the sensing node.

8. The semiconductor device according to any one of claims 1 to 5, wherein the bit line pair is a bit line adjacent to each other in a read operation.

9. The semiconductor device according to any one of claims 1 to 5, wherein the pair of bit lines is adjacent even bit lines or odd bit lines when the sensing means performs sensing of even bit lines or odd bit lines.

10. The semiconductor device according to any one of claims 1 to 5, wherein the bit line pair is a bit line selected according to a predetermined rule.

11. The semiconductor device according to any one of claims 1 to 5, wherein the generating means includes a calculating circuit for calculating data indicating a detection result of the detecting means, and the generating means outputs the calculation result of the calculating circuit as inherent data.

12. The semiconductor device according to any one of claims 1 to 5, further comprising:

a control means for controlling generation of the unique data;

wherein the control means controls the selection means, the readout means, the detection means and the generation means to generate the intrinsic data at the time of a boot-up procedure or in response to an external request.