CN110943824B - Key circuit based on single bus protocol - Google Patents
Key circuit based on single bus protocol Download PDFInfo
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- CN110943824B CN110943824B CN201911123995.XA CN201911123995A CN110943824B CN 110943824 B CN110943824 B CN 110943824B CN 201911123995 A CN201911123995 A CN 201911123995A CN 110943824 B CN110943824 B CN 110943824B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
The invention discloses a key circuit based on a single bus protocol, which comprises: the single bus port is connected with the single bus and used for inputting a control instruction and code matching data; the key control unit comprises a data processing module preset with a key; an exclusive OR unit which performs bitwise exclusive OR operation on the pair code data and the key; the input end of the RS trigger is connected with the XOR unit, and the output end of the RS trigger controls the read-write permission of the key control unit according to the operation result of the XOR unit; and/or the input of the timer unit is connected with the output of the RS trigger, and the output of the timer unit is fed back to the RS trigger. The key circuit based on the single bus protocol is realized based on the single bus, and the key circuit with a simple interface is designed, is easy to integrate with other memory circuits, and ensures the safety of stored data.
Description
Technical Field
The invention relates to the field of integrated circuits and data security, in particular to a secret key circuit based on a single bus protocol.
Background
With the development of science and technology, data leakage events are endlessly developed, and the situation of data security is severe day by day. In the field of integrated circuits, data encryption chips have been developed to prevent external intrusion. However, the integration of the memory and the encryption chip has difficulties at present. Firstly, the encryption chip generally adopts a cryptographic algorithm for encryption, and has a complex circuit structure and large power consumption. And secondly, the control interfaces of the encryption chip are multiple, and the integration is difficult.
Disclosure of Invention
In view of the above-mentioned disadvantages, the present invention provides a key circuit based on a single bus protocol to at least partially solve the above-mentioned problems.
In view of the above, the present invention provides a key circuit based on a single bus protocol, including:
and the single bus port is connected with the single bus, and the control instruction and the code matching data are input through the single bus port.
And the key control unit comprises a data processing module preset with a key.
In some embodiments, the number of bits of the pair code data and the number of bits of the key are the same;
in some embodiments, the data processing module is a memory.
An exclusive-or unit that performs a bitwise exclusive-or operation on the code data and the key, in some embodiments, the exclusive-or unit includes:
the exclusive-OR logic module is used for realizing exclusive-OR operation;
the first latch is arranged between the single bus port and the exclusive-OR logic module;
the second latch is arranged between the key control unit and the XOR logic module;
the processor module is arranged between the key control unit and the second latch and used for realizing the bitwise output of the key; and
and the frequency divider receives the result of the bitwise exclusive-OR operation and outputs a feedback signal.
Further, wherein the processor module comprises:
the processor is internally provided with N NMOS tubes and an N-to-1 circuit, wherein N is the bit number of the key;
the PMOS tube is externally connected with the processor;
the decoder is externally connected with the processor and controls the processor to realize the bitwise output of the key by combining the action of the frequency divider; and
and the instruction register is arranged between the single bus port and the frequency divider, and receives the control instruction and transmits the control instruction to the frequency divider.
Furthermore, the first latch, the second latch, the frequency divider and the instruction register are all connected with a reset signal.
And the input end of the RS trigger is connected with the XOR unit, and the output end of the RS trigger controls the read-write permission of the key control unit according to the operation result of the XOR unit.
In some embodiments, the input terminal of the RS flip-flop is connected to the frequency divider and receives the feedback signal output by the frequency divider.
And/or the input of the timer unit is connected with the output of the RS trigger, and the output of the timer unit is fed back to the RS trigger.
In some embodiments, the timer unit comprises:
the timer presets a set time length, and the input of the timer is the output of the RS trigger; and
and logic module, its output feeds back to RS flip-flop, and the input of the logic module of this AND includes the output of the operation result and timer of the control unit of the cipher key.
Further, the and logic module is also connected with a reset signal.
The key circuit based on the single bus protocol provided by the invention has the following remarkable advantages:
the invention adopts single bus interface communication, designs a key circuit with simple interface, the key is stored in EEPROM (electrically erasable programmable read only memory), the circuit structure is relatively simple, the power consumption is low, and the invention is easy to integrate with other memory circuits.
Drawings
FIG. 1 is a diagram of a key circuit architecture based on a single bus protocol according to an embodiment of the present invention;
FIG. 2 is an internal block diagram of the processor Core of FIG. 1;
FIG. 3 is a timing diagram illustrating the success of code matching when a memory has been operated according to an embodiment of the present invention;
FIG. 4 is a timing diagram illustrating the success of code checking when there is no operation in the memory according to the embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, specific details are set forth in order to provide a thorough understanding of embodiments of the invention. However, it will be apparent to one of ordinary skill in the art that: these specific details need not be employed to practice embodiments of the present invention. In other instances, well-known structures, materials, or methods are not specifically described in order to avoid obscuring embodiments of the present invention.
Throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, as used herein, the term "and/or" will be understood by those of ordinary skill in the art to include any and all combinations of one or more of the associated listed items.
The single bus is a peripheral serial expansion bus technology, and adopts a single signal to complete data transmission between a chip and an external controller. The invention aims to design a key circuit with a simple interface based on a single bus, which is easy to integrate with other memory circuits and ensures the safety of stored data.
In view of the above, the present invention discloses a key circuit based on a single bus protocol, which generally includes:
the single bus port is connected with the single bus and used for inputting a control instruction and code matching data;
the key control unit comprises a data processing module preset with a key;
an exclusive OR unit which performs bitwise exclusive OR operation on the pair code data and the key;
the input end of the RS trigger is connected with the XOR unit, and the output end of the RS trigger controls the read-write permission of the key control unit according to the operation result of the XOR unit;
and/or, a timer unit, wherein the input of the timer unit is connected with the output of the RS trigger, and the output of the timer unit is fed back to the RS trigger;
the bit number of the pair code data is the same as the bit number of the key, and in some embodiments, the data processing module is a memory.
Preferably, in some embodiments, the xor unit of the key circuit based on the single bus protocol further includes:
the exclusive-OR logic module is used for realizing exclusive-OR operation;
the first latch is arranged between the single bus port and the exclusive-OR logic module;
the second latch is arranged between the key control unit and the XOR logic module;
the processor module is arranged between the key control unit and the second latch and used for realizing the bitwise output of the key; and
and the frequency divider receives the result of the bitwise exclusive-OR operation and outputs a feedback signal.
Further, wherein the processor module further comprises:
the processor is internally provided with N NMOS tubes and an N-to-1 circuit, wherein N is the bit number of the key;
the PMOS tube is externally connected with the processor;
the decoder is externally connected with the processor and controls the processor to realize the bitwise output of the key by combining the action of the frequency divider; and
and the instruction register is arranged between the single bus port and the frequency divider, and receives the control instruction and transmits the control instruction to the frequency divider.
And the first latch, the second latch, the frequency divider and the instruction register are all connected with an RST signal (power-on reset signal).
Based on the above preferred implementation, in some embodiments, the input terminal of the RS flip-flop is connected to the frequency divider and receives the feedback signal output by the frequency divider.
Preferably, in some other embodiments, the timer unit of the key circuit based on the single bus protocol further includes:
the timer presets a set time length, and the input of the timer is the output of the RS trigger; and
and the output of the AND logic module is fed back to the RS flip-flop, the input of the AND logic module comprises the operation result of the key control unit and the output of the timer, and the AND logic module is also connected with an RST signal.
In the following, with reference to a specific embodiment, the cryptographic key circuit based on the single bus protocol and the memory of the present invention are integrated to implement an encryption function, and the implementation principle and the circuit structure thereof are shown in fig. 1 and fig. 2. In this embodiment, the key circuit based on the single bus protocol includes: the circuit comprises an instruction register, a frequency divider, a decoder, a first Latch (Latch1), a second Latch (Latch2), an exclusive-or logic module, a PMOS (P-channel metal oxide semiconductor) tube (MP0), a processor (Core), an RS flip-flop, an AND logic module and a timer, wherein in the embodiment, the key control unit is a memory with a preset key. In detail, in the present embodiment, first, referring to fig. 1, a circuit connection structure is described as follows:
the instruction register is connected with the single bus through a single bus port and is connected with the counter and the RST signal, and the instruction register is used for generating a control time sequence of a key pair code in the memory;
the input of the frequency divider is connected with the instruction register, the single bus port, the exclusive-or logic module and the RST signal, and the output of the frequency divider is connected with the decoder and the RS trigger;
the input of the decoder is connected with a frequency divider (counter), and the output of the decoder is connected with a Core circuit;
the Latch1 has its input connected to RST signal and single bus port and its output connected to XOR logic module;
the input of the Latch2 is connected with RST signal, PMOS tube MP0 and Core, and the output is connected with exclusive-or logic module;
the inputs of the exclusive-or logic block are connected to latches Latch1 and Latch2, and the outputs are connected to the counter;
the drain end of the PMOS pipe MP0 is connected with Core and Latch 2;
the Core is connected with the decoder, the MP0 and the key output in the memory;
the input of the RS trigger is connected with the counter and the logic module, and the output of the RS trigger is used for controlling an enabling port of the operation of the memory;
the input of the AND logic module is connected with a timer, a power-on reset signal RST and a mark signal for finishing the operation of the memory, and the output of the AND logic module is connected with an RS trigger;
the input of the timer is connected with the RS trigger, and the output of the timer is connected with the logic module.
Next, referring to fig. 2, a structural diagram of the Core circuit is shown, in which N NMOS transistors are connected in parallel to an N-out-of-one circuit (in this embodiment, N is 128), inputs of the N-out-of-one circuit are connected to the decoder and also connected to the PMOS transistor MP0, and inputs of the N NMOS transistors are connected to the memory to receive the N-bit key thereof.
Based on the circuit structure, the working principle of the circuit structure is further described with reference to the specific embodiment as follows:
in this embodiment, the key is stored in the memory, and a 128-bit key is taken as an example for description.
After the chip is powered on, the RST signal resets the modules such as the instruction register, the Latch (Latch1 and Latch2), and the divider inside the key circuit. At this time, the frequency divider in the reset state causes the signal EN which is sent by the RS flip-flop and used for controlling the memory read-write enable to be reset to a low level, and the memory is prohibited from read-write operation.
If the memory needs to be operated, code matching is firstly carried out, 128-bit data input from a single bus port are compared with 128-bit keys one by one, an EN signal of the memory jumps to be high after the data are completely the same, an enabling end is opened, the memory can be operated at the moment, EN returns to be low level after the operation is finished, and the memory is forbidden to read and write.
After the single bus port writes in the code-pairing instruction, the counter and the decoder control each bit of data input by the single bus to carry out bit-by-bit comparison (exclusive OR operation) with the 128-bit key in the memory in the exclusive OR logic module, and the output of the RS trigger is cleared all the time under the control of the counter. If the 128-bit data comparison is the same, the counter triggers the RS flip-flop to output high after the comparison is completed, which represents that the code matching is successful, and then the memory can be operated. Once the inconsistency occurs, the XOR logic outputs the counter outputs to reset the RS flip-flops all the way through, as further described below:
referring to the structure of the Core circuit, as shown in fig. 2, the circuit in the dotted line is a Core structure consisting of 128 NMOS and a 128-to-1 circuit, each bit output of the 128-bit key is connected to the gate of the 128 NMOS transistors of the Core, the external frequency divider and decoder controls the 128-to-1 circuit, and the external exclusive-or logic starts from LSB (least significant bit) to MSB (most significant bit) of the 128 bits when comparing the bits. The external pull-up PMOS tube is weak pull-up, the output is 1 when the pull-down NMOS is switched off, and the output is 0 when the pull-down NMOS is switched on;
the output feedback of the external exclusive-or logic module controls the frequency divider, if the 128 bits are same according to bit comparison, the frequency divider outputs a feedback signal to trigger the RS trigger to output and turn over, the EN signal of the memory is effective, and the memory can be operated at the moment; if a certain bit is different in the 128-bit comparison process, the frequency divider control system immediately stops comparison, the output of the RS trigger cannot be overturned, and the memory is prohibited from being accessed, so that the read-write control of the memory based on the secret key is completed.
The timing of successful code matching is shown in fig. 3, which shows that when there is an operation on the memory, the EN signal is triggered to reset after the memory operation is completed.
If the code is successfully copied and the memory is not operated, the EN signal is reset after a period of time is counted after the memory enable signal EN is jumped to high level, and the period of time is configurable (completed by a timer), and the timing is shown in fig. 4.
With respect to the above embodiments provided by the present invention, it should be understood that the related circuits disclosed may be implemented in other ways. For example, the circuit embodiments described above are merely illustrative, and for example, the division of the units or modules in the circuit is only one logical function division, and there may be other divisions when the actual implementation is performed, for example, a plurality of units or modules may be combined or integrated into a system, or some features may be omitted or not executed. Various operations and methods have been described. Some of the implementation principles have been described in a relatively basic manner in embodiments, but these operations may alternatively be added to and/or removed from these circuit blocks. Additionally, while a particular order of operation is provided in accordance with various exemplary embodiments, it is to be understood that this particular order is exemplary. Alternative embodiments may optionally perform these operations in a different manner, combine certain operations, interleave certain operations, etc. The unit, module features, and certain optional details described herein may also optionally be applied in the circuitry described herein, and in various embodiments the methods may be performed by and/or within an apparatus having such circuitry.
Each functional module in the present invention may be a digital circuit or an analog circuit, etc. Physical implementations include, but are not limited to, physical devices including, but not limited to, transistors, memristors, and the like. The memory module in the above embodiments may also be any suitable magnetic or magneto-optical storage medium, such as RRAM, DRAM, SRAM, EDRAM, HBM, HMC, etc.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A key circuit based on a single bus protocol, comprising:
the single bus port is connected with the single bus and used for receiving the control instruction and the code matching data;
the key control unit comprises a data processing module preset with a key;
an exclusive-or unit that performs a bitwise exclusive-or operation on the pair code data and the key, wherein the exclusive-or unit includes: the exclusive-OR logic module is used for realizing exclusive-OR operation; a first latch disposed between the single bus port and the XOR logic block; the second latch is arranged between the key control unit and the XOR logic module; the processor module is arranged between the key control unit and the second latch and used for realizing the bitwise output of the key; the frequency divider is used for receiving the result of the bitwise XOR operation and outputting a feedback signal;
the input end of the RS trigger is connected with the XOR unit, and the output end of the RS trigger controls the read-write permission of the key control unit according to the operation result of the XOR unit; and
a timer unit, an input of the timer unit is connected to an output of the RS flip-flop, and an output of the timer unit is fed back to the RS flip-flop, wherein the timer unit includes: the timer is preset with a set time length, and the input of the timer is the output of the RS trigger; the output of the AND logic module is fed back to the RS trigger, and the input of the AND logic module comprises the operation result of the key control unit and the output of the timer;
wherein the processor module comprises: the processor is internally provided with N NMOS tubes and an N-to-1 circuit, wherein N is the bit number of the secret key; the PMOS tube is externally connected with the processor; the decoder is externally connected with the processor, and the decoder and the frequency divider jointly act to control the processor to realize the bit-wise output of the key; and the instruction register is arranged between the single bus port and the frequency divider, and receives the control instruction and transmits the control instruction to the frequency divider.
2. The single bus protocol based key circuit of claim 1, wherein the number of bits of the pair of code data and the number of bits of the key are the same.
3. The single bus protocol based key circuit of claim 2, wherein the data processing module is a memory.
4. The single bus protocol-based key circuit according to claim 1, wherein a reset signal is input to each of the first latch and the second latch, and the reset signal is input to each of the frequency divider and the instruction register.
5. The single bus protocol based key circuit of claim 4, wherein the input terminal of the RS flip-flop is connected to the frequency divider and receives the feedback signal output by the frequency divider.
6. The single bus protocol based key circuit of claim 1, wherein a reset signal is input to the and logic module.
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| CN101677399A (en) * | 2008-09-18 | 2010-03-24 | 香港科技大学 | Method and system for encoding multimedia content based on secure coding schemes using stream cipher |
| CN103248543A (en) * | 2013-04-24 | 2013-08-14 | 华为技术有限公司 | Code verification method, code verification control equipment and code verification equipment |
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| GB2325123A (en) * | 1997-05-08 | 1998-11-11 | Ibm | Data encryption/decryption using random numbers |
| CN101854243B (en) * | 2010-04-30 | 2012-12-12 | 株洲南车时代电气股份有限公司 | Circuit system design encryption circuit and encryption method thereof |
| CN103905462B (en) * | 2014-04-16 | 2017-05-17 | 深圳国微技术有限公司 | Encryption processing device and method capable of defending differential power analysis attack |
| CN109495363A (en) * | 2018-12-13 | 2019-03-19 | 上海申矽凌微电子科技有限公司 | A kind of single bus data transmission chip and method |
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Patent Citations (2)
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| CN101677399A (en) * | 2008-09-18 | 2010-03-24 | 香港科技大学 | Method and system for encoding multimedia content based on secure coding schemes using stream cipher |
| CN103248543A (en) * | 2013-04-24 | 2013-08-14 | 华为技术有限公司 | Code verification method, code verification control equipment and code verification equipment |
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