CN110943786A - Signal recovery device and method suitable for quantum invisible transmission system - Google Patents
Signal recovery device and method suitable for quantum invisible transmission system Download PDFInfo
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- CN110943786A CN110943786A CN201911313336.2A CN201911313336A CN110943786A CN 110943786 A CN110943786 A CN 110943786A CN 201911313336 A CN201911313336 A CN 201911313336A CN 110943786 A CN110943786 A CN 110943786A
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
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Abstract
The invention relates to the field of computers, in particular to a signal recovery device suitable for a quantum invisible transmission system, which comprises: the system comprises a beam splitter connected with a quantum transmission channel, a clock recovery module and a balanced homodyne detector which are respectively connected with the beam splitter, an amplifier connected with the balanced homodyne detector, a splitter connected with the amplifier, a delay module connected with the splitter, a high-speed Analog-to-Digital Converter (ADC) sampling module connected with the clock recovery module and the delay module respectively, and an FGPA (field Programmable Gate array) internal logic module. The invention also relates to a signal recovery method suitable for the quantum invisible transmission system.
Description
Technical Field
The invention relates to the field of computers, in particular to a signal recovery device and a signal recovery method suitable for a quantum invisible transmission system.
Background
Quantum communication has been proven to have advantages that classical communication cannot surpass, such as high efficiency, high speed, and absolute security. The quantum invisible transmission system can be used as an important element and a basic framework of quantum communication and can also be used as a quantum repeater to provide powerful support for constructing a quantum communication network, and the transmission scheme can be popularized and applied to transmission networks of important services in industries such as electric power and the like.
The quantum invisible transmission system adopts a balanced homodyne detector at a receiving end to carry out photoelectric conversion on signals, a high-precision analog-to-digital converter (ADC) is required to be used for conversion in order to ensure the recovery precision of the signals, and meanwhile, in order to ensure the fidelity of the signals, the sampling is carried out in a high-signal quality interval by using a high sampling rate. Because the fidelity of the signal is closely related to the information transmitted by the quantum invisible transmission system, the high-fidelity signal can be recovered in real time, and the method becomes one of key technologies of the quantum invisible transmission system from laboratories to practical application.
The existing recovery technology of the receiving end signal of the quantum invisible transmission system adopts an oscilloscope as a high-speed acquisition device to sample the electric signal output by a balanced homodyne detector. Although the data can be acquired at a high speed in real time in an online mode by using the oscilloscope in the whole sampling process, the oscilloscope is limited in sampling precision, and part of the oscilloscope with high precision is very expensive, so that the real-time processing of the data in an actual application environment is difficult to realize; in the aspect of signal data processing, a large amount of sampled data needs to be cached on a computer, and then offline post-processing is performed through computing software to complete signal recovery. Since a large amount of signal data is required in the signal recovery calculation process and a large amount of intermediate data is also generated in the calculation process, great requirements are necessarily put on the data buffer capacity and the data throughput rate in the data processing process, however, the computer and computer-based computer software are difficult to achieve in this respect, and thus the practicability of the quantum stealth transmission system is limited to a great extent.
Disclosure of Invention
The invention aims to provide a signal recovery device and a signal recovery method suitable for a quantum invisible transmission system.
The technical scheme adopted by the invention is as follows: a signal recovery apparatus suitable for use in a quantum invisible transmission system, the apparatus comprising: a beam splitter connected with a quantum transmission channel, a clock recovery module and a balanced homodyne detector respectively connected with the beam splitter, an amplifier connected with the balanced homodyne detector, a splitter connected with the amplifier, a delay module connected with the splitter, a high-speed Analog-to-Digital Converter (ADC) sampling module respectively connected with the clock recovery module and the delay module, an FGPA (field Programmable Gate array) internal logic module respectively connected with the clock recovery module and the delay module, the FGPA (field Programmable Gate array) internal logic module comprises a data synchronization unit, a data monitoring unit connected with the data processing unit, and a control unit connected with the data monitoring unit, the control unit is respectively connected with the delay module and the high-speed Analog-to-Digital Converter sampling module, the data processing unit is connected with a control room through a network port, the balanced homodyne detector is used for detecting amplitude and phase information output by the quantum invisible transmission system, the FPGA is used for acquiring output electric signals by controlling the high-speed analog-to-digital converter acquisition module, obtaining data and transmitting the data back to the interior of the FPGA, and meanwhile, the FPGA is used for setting up a signal recovery algorithm to process and recover real-time data by utilizing the interior logic of the FPGA.
Furthermore, the delay module comprises a plurality of delay units, the high-speed analog-to-digital converter sampling module comprises a plurality of analog-to-digital converter sampling units which are the same as the delay units, each delay unit is connected with one analog-to-digital converter sampling unit in a one-to-one correspondence manner, and the FPGA controls each analog-to-digital converter sampling unit of the high-speed analog-to-digital converter sampling module to realize high-speed synchronous acquisition of output electric signals.
Furthermore, the high-speed analog-to-digital converter sampling module samples based on a time division multiplexing principle, and combines with the signal delay module to sample a single signal for multiple times in a sampling period of the analog-to-digital converter.
Further, the signal recovery algorithm is realized through internal hardware resources of the FPGA.
The invention also provides a signal recovery method suitable for a quantum invisible transmission system, wherein the method comprises the following steps of:
firstly, a quantum invisible transmission system clock obtains a system sending end transmission clock at a receiving end through a clock recovery module, and system clock synchronization of the quantum invisible transmission sending end and the receiving end is realized;
secondly, in the information transmission process, the data synchronization of both quantum invisible transmission sides is realized by adding a data synchronization code at the front end of effective transmission information;
thirdly, after a transmission signal is obtained through a balanced homodyne detector, the amplitude of the transmission signal is amplified through an amplifier, the transmission signal enters a branching unit and is divided into multiple paths of branch transmission signals, each path of branch transmission signal respectively enters a corresponding delay module and a high-speed analog-to-digital converter acquisition module, a receiving end obtains a sending end clock of the quantum invisible transmission system again through a clock recovery module, multiple paths of synchronous clock signals are generated through a phase-locked loop and are respectively transmitted to each analog-to-digital converter sampling unit in the high-speed analog-to-digital converter acquisition module;
fourthly, the FPGA configures the signal delay parameter of each path of delay unit and the parameter of the sampling rate of the analog-digital converter in the high-speed analog-digital converter sampling module;
and fifthly, simultaneously acquiring data by the plurality of analog-to-digital converter sampling units, transmitting the acquired signal data to a data synchronization unit in the FPGA for data synchronization, sending the signal data to a data processing unit by the data synchronization unit, and executing a signal recovery algorithm on the data processing unit to recover the signal data.
Furthermore, in the first step, the quantum invisible transmission system clock obtains a sending clock at a receiving end through a clock recovery module and realizes clock synchronization of the sending end and the receiving end, polarization demultiplexing is carried out on a local optical field and a signal optical field in the single-mode optical fiber, a part of the local optical field is extracted to be used as system synchronous clock recovery, the clock recovery module comprises a clock shaping circuit and a phase-locked loop clock circuit, the system clock at the receiving end carries out shaping processing on the output level of the clock signal at the shaping circuit of the clock recovery module, the output regular clock signal enters the phase-locked loop clock circuit, and the phase-locked loop clock circuit can provide low-jitter and high-frequency multipath clock signals; and the receiving end loads the orthogonal amplitude and the orthogonal phase measuring base on the modulator, and finally outputs the orthogonal amplitude component and the orthogonal phase component of the signal light field as electric signals by using a balanced homodyne detector.
Furthermore, in the fifth step, signal recovery is carried out through a data processing unit realized in the FPGA, high fidelity recovery of the signal data is realized, and the high fidelity recovery of the signal data adopts a high fidelity signal sampling optimizing control flow to control the optimal sampling interval. In the high-speed high-precision acquisition process, the real-time fidelity of the synchronous code signal is used as control information.
Furthermore, in the fifth step, in the control algorithm of the optimal sampling interval, uniform sampling and cyclic sampling modes of a plurality of analog-to-digital converter sampling units within the range of the sampling period of one analog-to-digital converter are realized, and the adjustment of the optimal sampling interval within the sampling period of one analog-to-digital converter is realized by dynamically adjusting the delay parameters of the delay module.
Further, the control of the optimal sampling interval by adopting a high-fidelity signal sampling optimization control process comprises the following steps:
step 1: the receiving end carries out initialization configuration: setting the relative delay of each signal to be 0 and the sampling period to be TsThe total number of optimizing cycles is L, and the upper limit of the stepping delay time of the delay module is Delta Td；
Step 2: the signal period is T, then at eachWithin the signal period, m is T/TsSampling points;
and step 3: data 1-datam of m points in each signal period sampled by each analog-to-digital converter sampling unit are transmitted back to a data synchronization unit of the FPGA, 7-bit synchronization code judgment is carried out, if the judgment result shows that the synchronization code enters the step 4, otherwise, sampling and judgment are continued;
step 4, the data processing unit calculates the fidelity η of m sampling points of a single synchronous code element signal, sorts and takes the maximum fidelity ηmaxRecording the sampling point at this time as
Step 5, taking the maximum fidelity value ηmaxWith a predetermined fidelity threshold ηstBy comparison, if ηmax<ηstEntering a step 6 of a cyclic sampling and optimizing process;
step 6: adjusting the relative delay interval delta T-T between the signals of the sampling units of other (four) A/D converters respectively by taking one A/D converter sampling unit as the referencesAnd 5, each analog-to-digital converter sampling unit samples signals according to the time division multiplexing principle by using the sampling points
Is a central point at [ -Ts/2,Ts/2]Is sampled within the signal interval.
And 7: sampling unit is arranged at [ -T ] for each analog-to-digital converters/2,Ts/2]Calculating the fidelity η of the sampling points in the interval, sorting and taking the maximum value
Recording the sampling point of the A/D converter at the moment
And as the central point of the optimal sampling interval, setting the interval [ -T ]s/(2×5),Ts/(2×5)]As an optimal sampling interval;
and 8, taking the central point of the optimal interval as the central point of delay adjustment, and adjusting the relative delay to △ T-Ts/5nAt the optimal sampling interval [ -T [ ]s/(2×5n-1),Ts/(2×5n-1)]When △ T is Ts/5n≥△TdSequentially and circularly executing the steps 7 and 8, and adding one to the cycle number l after each execution;
and step 9: when l is equal to l0Or fidelity 0.9996, ends the optimization process, records
For the central point of the optimal sampling interval, the sampling point is used
Is centered at [ -T [ ]s/(2×5n-1),Ts/(2×5n-1)]Sampling within the signal interval of (a);
step 10, if the fidelity of the synchronization code is abnormal and the fluctuation amplitude is larger or not at the standard threshold η in the running processstWithin the range, the initialization is started from the step 1 again, and the subsequent steps 2 to 10 are executed.
Compared with the prior art, the invention provides the device and the method for realizing high-fidelity signal recovery in the quantum invisible transmission system, which can accurately recover the high-fidelity signal in real time, monitor the signal recovery quality and enhance the adaptability of the system to signal quality change caused by transmission environment change. The invention can effectively improve the high fidelity and the generation rate of the transmission signals of the quantum invisible transmission system and provide technical support for the practical development of the quantum invisible transmission system.
The invention adopts a high-speed high-precision sampling module consisting of a plurality of analog-to-digital converter sampling units and delay units to accurately sample high-fidelity signals output by the detector at high speed, and controls the sampling mode and the sampling interval of the signals by taking the FPGA as a main control unit of the high-speed sampling according to the recovery quality of the real-time monitoring signals, thereby effectively improving the recovery quality of the signals. Meanwhile, the requirement of the quantum invisible transmission system on the signal to noise ratio and the acquisition precision is very high, and the application requirement of a common high-precision sampling chip is difficult to meet in the aspect of sampling rate, so that the sampling rate is improved by adopting a method of sampling and transmitting signals by a plurality of analog-to-digital converter sampling units in a time-sharing manner. The FPGA logic resource constructs a data processing algorithm unit in the FPGA logic resource, and the FPGA is utilized to execute parallel processing, so that the signal recovery algorithm process is accelerated, and the recovery speed of the high-fidelity signal is effectively improved.
In addition, the invention directly carries out high-speed algorithm processing on the signal data, effectively solves the problem of insufficient space of a large amount of data cache caused by low calculation rate, and enhances the real-time processing capability of the system. The method effectively solves the problems of signal fidelity recovery quality caused by insufficient sampling rate and sampling precision and signal real-time processing capacity caused by insufficient computer data processing capacity in the quantum invisible transmission system.
The high-fidelity signal recovery device can effectively improve the fidelity of the quantum invisible transmission system, thereby ensuring the communication quality.
The invention has flexible control, high signal acquisition rate, high precision and high data processing speed, can efficiently realize the real-time post-processing of data signals, and solves the problem of insufficient signal fidelity caused by low acquisition speed, low precision and insufficient post-processing capacity in the high-speed transmission process of the quantum invisible transmission system. The function of monitoring the signal fidelity in real time is realized, the recovery capability of the information at the receiving end of the quantum invisible transmission system is enhanced, and the stability and the safety of the system are improved.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
fig. 1 is a schematic diagram of a high-fidelity signal recovery apparatus suitable for a quantum invisible transmission system according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a transmission signal and a synchronization code according to an embodiment of the invention;
figure 3 shows a high fidelity signal sampling optimization control flow diagram of an embodiment of the present invention.
The same or similar reference numbers in the drawings identify the same or similar elements.
Detailed Description
The present invention is described in further detail below with reference to the attached drawing figures.
As shown in fig. 1, a signal recovery device suitable for a quantum invisible transmission system, the device includes: a beam splitter connected with a quantum transmission channel, a clock recovery module and a balanced homodyne detector respectively connected with the beam splitter, an amplifier connected with the balanced homodyne detector, a splitter connected with the amplifier, a delay module connected with the splitter, a high-speed Analog-to-Digital Converter (ADC) sampling module respectively connected with the clock recovery module and the delay module, an FGPA (field Programmable Gate array) internal logic module respectively connected with the clock recovery module and the delay module, the FGPA (field Programmable Gate array) internal logic module comprises a data synchronization unit, a data monitoring unit connected with the data processing unit, and a control unit connected with the data monitoring unit, the control unit is respectively connected with the delay module and the high-speed Analog-to-Digital Converter sampling module, the data processing unit is connected with a control room through a network port, the balanced homodyne detector is used for detecting amplitude and phase information output by the quantum invisible transmission system, the FPGA is used for acquiring output electric signals by controlling the high-speed analog-to-digital converter acquisition module, obtaining data and transmitting the data back to the interior of the FPGA, and meanwhile, the FPGA is used for setting up a signal recovery algorithm to process and recover real-time data by utilizing the interior logic of the FPGA.
The time delay module comprises a plurality of time delay units, the high-speed analog-to-digital converter sampling module comprises a plurality of analog-to-digital converter sampling units which are the same as the time delay units, each time delay unit is connected with one analog-to-digital converter sampling unit in a one-to-one correspondence mode, and the FPGA controls each analog-to-digital converter sampling unit of the high-speed analog-to-digital converter sampling module to achieve high-speed synchronous acquisition of output electric signals.
The high-speed analog-to-digital converter sampling module samples based on a time division multiplexing principle, and combines with the signal delay module to sample a single signal for multiple times in a sampling period of the analog-to-digital converter, so that the sampling speed and the sampling precision of the signal are effectively improved, and sufficient data are provided for high-fidelity recovery of the signal.
The signal recovery algorithm is realized through internal hardware resources of the FPGA, real-time recovery processing of signals can be realized within a certain speed range, and meanwhile, the anti-attack capability of the system is enhanced by matching with a signal fidelity change monitoring unit.
A signal recovery method for a quantum invisible transmission system, which samples the signal recovery device for a quantum invisible transmission system, the method comprising:
the clock of the quantum invisible transmission system obtains a sending clock at a receiving end through a clock recovery module, realizes clock synchronization of both sides of transmission by utilizing the sending clock, obtains a transmission signal through a balanced homodyne detector, amplifies the amplitude of the transmission signal through an amplifier, the transmission signal enters a branching unit and is divided into a plurality of paths of branch transmission signals, and each path of branch transmission signal respectively enters a corresponding delay module and a high-speed analog-to-digital converter acquisition module;
the FPGA configures the signal delay parameter of each path of delay unit and the sampling rate parameter of the analog-digital converter in the high-speed analog-digital converter sampling module so as to realize high-speed accurate acquisition of signals;
in the information transmission process, data synchronization of both communication sides is realized by adding a data synchronization code at the front end of effective transmission information, a plurality of analog-to-digital converter sampling units transmit acquired signal data to a data synchronization unit in an FPGA (field programmable gate array) for data synchronization while acquiring the data, the data synchronization unit transmits the signal data to a data processing unit, and high fidelity recovery of the signal data is realized by performing a signal recovery algorithm on the data processing unit.
The clock of the quantum invisible transmission system obtains a sending clock at a receiving end through a clock recovery module, realizes clock synchronization of the sending end and the receiving end, performs polarization demultiplexing on a local light field and a signal light field in a single-mode optical fiber, extracts a part of the local light field as system synchronous clock recovery, the clock recovery module comprises a clock shaping circuit and a phase-locked loop clock circuit, the system clock of the receiving end performs shaping processing on the output level of a clock signal at the shaping circuit of the clock recovery module, the output regular clock signal enters the phase-locked loop clock circuit, and the phase-locked loop clock circuit can provide a plurality of paths of clock signals with low jitter and high frequency; and the receiving end loads the orthogonal amplitude and the orthogonal phase measuring base on the modulator, and finally outputs the orthogonal amplitude component and the orthogonal phase component of the signal light field as electric signals by using a balanced homodyne detector.
The synchronous clock signal enters a sampling module of the high-speed analog-to-digital converter, so as to realize high-fidelity signal acquisition. Because the quantum invisible transmission system has very high requirements on signal-to-noise ratio and acquisition precision for transmitting information, a high-precision analog-to-digital conversion chip AD4002 of ADI company is adopted, can provide high-speed, ultra-low noise and high-precision sampling performance, can effectively reduce the power of a signal chain, reduce the complexity of the signal chain and realize higher channel density, realizes synchronous acquisition among a plurality of analog-to-digital converter sampling units through clock synchronization among a plurality of analog-to-digital converter sampling units, ensures accurate analysis of data, adopts a high-precision delay chip DS1023 as a main device, the step programmable delay of 500ps can be provided, each path of signal output by the shunt enters the high-speed analog-to-digital conversion chip after passing through the delay chip, and the FPGA configures the signal delay parameter of each path of delay module and the sampling rate and other parameters of the analog-to-digital converter in the high-speed analog-to-digital converter acquisition module to realize the high-speed accurate acquisition of the signal. In the system, a high-fidelity signal sampling optimization control flow is adopted to determine the optimal sampling interval of a signal, the sampling rate is set to be 1MSps, the relative delay of each path of delay signal is respectively adjusted to be 200ns in the sampling period of 1000ns of an analog-to-digital converter, and the equivalent is high-speed high-precision sampling of 5 MSps. According to the high-fidelity signal sampling optimization control flow, an optimal sampling interval is searched in a signal period, and the optimal sampling interval is controlled. And the data of the analog-to-digital converters are simultaneously and respectively transmitted into the FPGA to carry out data synchronization among a plurality of data channels, then the signal data are transmitted to the FPGA algorithm unit, and the high-fidelity recovery of the signals is realized by carrying out a signal recovery algorithm in the FPGA.
In the FPGA, a control unit controls a sampling module of a high-speed analog-to-digital converter to realize the optimization process of a high-fidelity sampling interval, and the fidelity is higher than 0.9996 and is used as a judgment threshold value for stopping a sampling optimization control algorithm.
The clock synchronization and the data synchronization are realized based on Local light of optical fiber transmission, so that accurate synchronization of signals of both communication parties can be realized, real-time monitoring of information fidelity in the transmission process is realized through fidelity monitoring of synchronous codes, and a foundation is provided for high fidelity recovery of information.
High fidelity restoration of signal data is achieved by performing a signal restoration algorithm at a data processing unit, comprising:
the method comprises the steps that a high-fidelity signal sampling optimizing control process is adopted to control an optimal sampling interval, wherein in the high-speed high-precision acquisition process, the real-time fidelity of a synchronous code signal is used as control information, the uniform sampling and cyclic sampling modes of a plurality of analog-to-digital converter sampling units within the sampling period range of one analog-to-digital converter are realized through an FPGA (field programmable gate array) internal control algorithm, and the adjustment of the optimal sampling interval within the sampling period of one analog-to-digital converter is realized through dynamically adjusting delay parameters of a delay module; and when the signal fidelity is abnormally fluctuated, the initialization configuration is carried out again so as to achieve the high fidelity recovery effect of the transmitted information.
As shown in fig. 2 and 3, in an embodiment of the signal recovery method applicable to the quantum invisible transmission system, the method for controlling the optimal sampling interval by using the high-fidelity signal sampling optimization control flow includes:
step 1: the receiving end carries out initialization configuration;
step 2: the signal period is 100us, the sampling period is 1000ns, the stepping delay time of the delay module is 500ps, 100 sampling points exist in each signal period, the relative delay of each path of signal is adjusted to be 0, and the total optimization cycle number is set to be 4;
and step 3: transmitting 100 points of data sampled by each analog-to-digital converter sampling unit in each signal period back to a data synchronization unit of the FPGA, judging 7-bit synchronization codes, and entering the step 4 if the synchronization codes are judged, otherwise, continuing sampling and judging;
step 4, the data processing unit calculates the fidelity η of 100 sampling points of each synchronous code element signal, sorts and takes the maximum value ηmax0.99831, record the 52 th sample data of 100 samples at this time
Step 5, maximum value at this time is greater than fidelity threshold ηst＝0.9980Entering a step 6 of a cyclic sampling and optimizing process;
step 6: respectively adjusting the relative delay interval between the signals of the sampling units of the analog-to-digital converters of the third path by taking the sampling units of the analog-to-digital converter of the third path as the reference
All the sampling units of the analog-to-digital converter are positioned at the center point of [ -500ns,500ns ] by taking the 52 th sampling point as the center point]Is sampled within the signal interval, the number of cycles is noted as 1, and then step 7.
And 7: the sampling unit of each analog-to-digital converter is between-500 ns and 500ns]The fidelity η of the sampling points in the interval is calculated, sorted and the maximum fidelity 0.99917 is taken, at this time, the sampling point of the 3 rd path analog-to-digital converter
And 8: sampling the 3 rd path
As the central point of the next delay adjustment, the relative delay is adjusted to be Δ t-40 ns in the interval [ -100ns,100ns]Internally performing sampling, and performing steps 6 and 7, wherein the cycle number is 2;
and step 9: when the 3 rd loop is executed, the calculated fidelity of the 5 th path is 0.99962, which is larger than the preset fidelity value 0.9996, and the searching process is ended to record the current time
By sampling points
Is centered at [ -8ns,8ns]Sampling within the signal interval of (a);
step 10, if the fidelity of the synchronization code is abnormal and the fluctuation amplitude is larger or not at the standard threshold η in the running processstWithin the range, the initialization is started from the step 1 again, and the subsequent steps 2 to 10 are executed.
In summary, the invention provides a device and a method for realizing high fidelity signal recovery in a quantum invisible transmission system, which can accurately recover high fidelity signals in real time, monitor the signal recovery quality, and enhance the adaptability of the system to signal quality changes caused by transmission environment changes. The invention can effectively improve the high fidelity and the generation rate of the transmission signals of the quantum invisible transmission system and provide technical support for the practical development of the quantum invisible transmission system.
The invention adopts a high-speed high-precision sampling module consisting of a plurality of analog-to-digital converter sampling units and delay units to accurately sample high-fidelity signals output by the detector at high speed, and controls the sampling mode and the sampling interval of the signals by taking the FPGA as a main control unit of the high-speed sampling according to the recovery quality of the real-time monitoring signals, thereby effectively improving the recovery quality of the signals. Meanwhile, the requirement of the quantum invisible transmission system on the signal to noise ratio and the acquisition precision is very high, and the application requirement of a common high-precision sampling chip is difficult to meet in the aspect of sampling rate, so that the sampling rate is improved by adopting a method of sampling and transmitting signals by a plurality of analog-to-digital converter sampling units in a time-sharing manner. The FPGA logic resource constructs a data processing algorithm unit in the FPGA logic resource, and the FPGA is utilized to execute parallel processing, so that the signal recovery algorithm process is accelerated, and the recovery speed of the high-fidelity signal is effectively improved.
In addition, the invention directly carries out high-speed algorithm processing on the signal data, effectively solves the problem of insufficient space of a large amount of data cache caused by low calculation rate, and enhances the real-time processing capability of the system. The method effectively solves the problems of signal fidelity recovery quality caused by insufficient sampling rate and sampling precision and signal real-time processing capacity caused by insufficient computer data processing capacity in the quantum invisible transmission system.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. A plurality of units or means recited in the apparatus claims may also be implemented by one unit or means in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (9)
1. A signal recovery device suitable for quantum invisible transmission system is characterized in that: the device comprises a beam splitter connected with a quantum transmission channel, a clock recovery module and a balanced homodyne detector respectively connected with the beam splitter, an amplifier connected with the balanced homodyne detector, a splitter connected with the amplifier, a time delay module connected with the splitter, a high-speed analog-to-digital converter sampling module and an FGPA internal logic module respectively connected with the clock recovery module and the time delay module, wherein the FGPA internal logic module comprises a data synchronization unit, a data monitoring unit connected with the data processing unit and a control unit connected with the data monitoring unit, the control unit is respectively connected with the time delay module and the high-speed analog-to-digital converter sampling module, the data processing unit is connected with a control room through a network port, and the balanced homodyne detector is used for detecting amplitude and phase information output by a quantum invisible transmission system, the FPGA is used for controlling the high-speed analog-to-digital converter acquisition module to acquire output electric signals to obtain data, transmitting the data back to the interior of the FPGA, and simultaneously, utilizing the interior logic of the FPGA to set up a signal recovery algorithm to process and recover the real-time data.
2. The signal recovery device of claim 1, wherein the signal recovery device comprises: the time delay module comprises a plurality of time delay units, the high-speed analog-to-digital converter sampling module comprises a plurality of analog-to-digital converter sampling units which are the same as the time delay units, each time delay unit is connected with one analog-to-digital converter sampling unit in a one-to-one correspondence mode, and the FPGA controls each analog-to-digital converter sampling unit of the high-speed analog-to-digital converter sampling module to achieve high-speed synchronous acquisition of output electric signals.
3. The signal recovery device of claim 1, wherein the signal recovery device comprises: the high-speed analog-to-digital converter sampling module samples based on a time division multiplexing principle and combines with the signal delay module to sample a single signal for multiple times in a sampling period of the analog-to-digital converter.
4. The signal recovery device of claim 1, wherein the signal recovery device comprises: the signal recovery algorithm is realized through FPGA internal hardware resources.
5. A signal recovery method suitable for a quantum invisible transmission system is characterized by comprising the following steps: a signal recovery device adapted for use in a quantum invisible transmission system as claimed in any one of claims 1 to 4, said method comprising:
firstly, a quantum invisible transmission system clock obtains a system sending end transmission clock at a receiving end through a clock recovery module, and system clock synchronization of the quantum invisible transmission sending end and the receiving end is realized;
secondly, in the information transmission process, the data synchronization of both quantum invisible transmission sides is realized by adding a data synchronization code at the front end of effective transmission information;
thirdly, after a transmission signal is obtained through a balanced homodyne detector, the amplitude of the transmission signal is amplified through an amplifier, the transmission signal enters a branching unit and is divided into multiple paths of branch transmission signals, each path of branch transmission signal respectively enters a corresponding delay module and a high-speed analog-to-digital converter acquisition module, a receiving end obtains a sending end clock of the quantum invisible transmission system again through a clock recovery module, multiple paths of synchronous clock signals are generated through a phase-locked loop and are respectively transmitted to each analog-to-digital converter sampling unit in the high-speed analog-to-digital converter acquisition module;
fourthly, the FPGA configures the signal delay parameter of each path of delay unit and the parameter of the sampling rate of the analog-digital converter in the high-speed analog-digital converter sampling module;
and fifthly, simultaneously acquiring data by the plurality of analog-to-digital converter sampling units, transmitting the acquired signal data to a data synchronization unit in the FPGA for data synchronization, sending the signal data to a data processing unit by the data synchronization unit, and executing a signal recovery algorithm on the data processing unit to recover the signal data.
6. The signal recovery method for quantum invisible transmission system according to claim 5, wherein: in the first step, a quantum invisible transmission system clock obtains a sending clock at a receiving end through a clock recovery module, the clock synchronization of the sending end and the receiving end is realized, polarization demultiplexing is carried out on a local light field and a signal light field in a single-mode optical fiber, a part of the local light field is extracted to be used as system synchronous clock recovery, the clock recovery module comprises a clock shaping circuit and a phase-locked loop clock circuit, the output level of the clock signal is shaped by the system clock at the receiving end through the shaping circuit of the clock recovery module, the output regular clock signal enters the phase-locked loop clock circuit, and the phase-locked loop clock circuit can provide a plurality of paths of clock signals with low jitter and high; and the receiving end loads the orthogonal amplitude and the orthogonal phase measuring base on the modulator, and finally outputs the orthogonal amplitude component and the orthogonal phase component of the signal light field as electric signals by using a balanced homodyne detector.
7. The signal recovery method suitable for the quantum invisible transmission system as claimed in claim 5, wherein in the fifth step of the method, signal recovery is performed by a data processing unit implemented inside the FPGA, so as to achieve high fidelity recovery of the signal data. Further, in the fifth step of the method, the high fidelity recovery of the signal data adopts a high fidelity signal sampling optimization control flow to control the optimal sampling interval. In the high-speed high-precision acquisition process, the real-time fidelity of the synchronous code signal is used as control information.
8. The signal recovery method for the quantum invisible transmission system as claimed in claim 7, wherein the algorithm for controlling the optimal sampling interval is to implement a uniform sampling and cyclic sampling mode for a plurality of sampling units of the analog-to-digital converter within a sampling period of the analog-to-digital converter, and to implement the adjustment of the optimal sampling interval within the sampling period of the analog-to-digital converter by dynamically adjusting delay parameters of the delay module.
9. The signal recovery method for the quantum invisible transmission system as claimed in claim 7, wherein the controlling of the optimal sampling interval by using the high fidelity signal sampling optimization control flow comprises:
step 1: the receiving end carries out initialization configuration: setting the relative delay of each signal to be 0 and the sampling period to be TsThe total number of optimizing cycles is L, and the upper limit of the stepping delay time of the delay module is Delta Td；
Step 2: the signal period is T, and m is T/T in each signal periodsSampling points;
and step 3: data 1-datam of m points in each signal period sampled by each analog-to-digital converter sampling unit are transmitted back to a data synchronization unit of the FPGA, 7-bit synchronization code judgment is carried out, if the judgment result shows that the synchronization code enters the step 4, otherwise, sampling and judgment are continued;
step 4, the data processing unit calculates the fidelity η of m sampling points of a single synchronous code element signal, sorts and takes the maximum fidelity ηmaxRecording the sampling point at this time as
Step 5, taking the maximum fidelity value ηmaxWith a predetermined fidelity threshold ηstBy comparison, if ηmax<ηstEntering a step 6 of a cyclic sampling and optimizing process;
step 6: adjusting the relative delay interval delta T-T between the signals of the sampling units of other (four) A/D converters respectively by taking one A/D converter sampling unit as the referencesAnd 5, each analog-to-digital converter sampling unit samples signals according to the time division multiplexing principle by using the sampling points
Is a central point at [ -Ts/2,Ts/2]Is sampled within the signal interval.
And 7: sampling unit is arranged at [ -T ] for each analog-to-digital converters/2,Ts/2]Calculating the fidelity η of the sampling points in the interval, sorting and taking the maximum value
Recording the sampling point of the A/D converter at the moment
And as an optimumSampling interval central point, setting interval [ -T [ ]s/(2×5),Ts/(2×5)]As an optimal sampling interval;
and 8, taking the central point of the optimal interval as the central point of delay adjustment, and adjusting the relative delay to △ T-Ts/5nAt the optimal sampling interval [ -T [ ]s/(2×5n-1),Ts/(2×5n-1)]When △ T is Ts/5n≥△TdSequentially and circularly executing the steps 7 and 8, and adding one to the cycle number l after each execution;
and step 9: when l is equal to l0Or fidelity 0.9996, ends the optimization process, records
For the central point of the optimal sampling interval, the sampling point is used
Is centered at [ -T [ ]s/(2×5n-1),Ts/(2×5n-1)]Sampling within the signal interval of (a);
step 10, if the fidelity of the synchronization code is abnormal and the fluctuation amplitude is larger or not at the standard threshold η in the running processstWithin the range, the initialization is started from the step 1 again, and the subsequent steps 2 to 10 are executed.
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