CN110940689B - Preparation method of SiC device sample and morphology analysis method of SiC device - Google Patents
Preparation method of SiC device sample and morphology analysis method of SiC device Download PDFInfo
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- CN110940689B CN110940689B CN201811098038.1A CN201811098038A CN110940689B CN 110940689 B CN110940689 B CN 110940689B CN 201811098038 A CN201811098038 A CN 201811098038A CN 110940689 B CN110940689 B CN 110940689B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/22—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/22—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
- G01N23/2202—Preparing specimens therefor
Abstract
The invention provides a preparation method of a SiC device sample and a morphology analysis method of a SiC device, which comprises the following steps: removing the non-conductive protective layer on the surface of the SiC device; forming a longitudinal section of the SiC device, and exposing a junction structure to be observed; forming a conductive layer covering the surface of the SiC device and the longitudinal section; removing at least part of the conducting layer on the longitudinal section to form a SiC device sample with the junction morphology observed by a scanning electron microscope; the preparation method of the SiC device sample can clearly observe the junction morphology of the section of the SiC device sample.
Description
Technical Field
The invention relates to the technical field of SiC devices, in particular to a preparation method of a SiC device sample and a morphology analysis method of a SiC device.
Background
SiC (silicon carbide) materials have been one of the materials of the next-generation semiconductor power devices because of their material properties such as high hardness, heat resistance, oxidation resistance, and corrosion resistance. Semiconductor power devices made of SiC materials, such as schottky diodes and power devices of MOSFETs (Metal-Oxide-Semiconductor Field-Effect transistors), have been put into commercial use.
Laboratories generally need to observe and analyze the junction morphology of the longitudinal section of the SiC device, however, because the valence bond of SiC is very tight and chemical properties are inactive, the junction morphology of the longitudinal section of the SiC device cannot be displayed by using a general chemical etching method.
One conventional method is to polish the longitudinal section of the SiC device, and then observe the junction morphology of the longitudinal section of the SiC device by using a SCM (Scanning Capacitance microscope).
Another conventional method is to observe the junction morphology of the longitudinal section of the SiC device by SIMS (Secondary Ion Mass Spectrometry).
The two conventional methods are expensive, so the current method is to use a Scanning Electron Microscope (SEM) to observe the junction morphology of the longitudinal section of the SiC device. However, a protective layer (for example, a polyimide protective film) usually covers the surface of the SiC device, a passivation layer and a dielectric layer also exist below the protective layer, the passivation layer and the dielectric layer all have non-conductive characteristics and belong to non-conductive layers, when the junction morphology of the longitudinal section of the SiC device is scanned by using an electron beam emitted by a scanning electron microscope, primary electrons are not guided away when being injected into the protective layer, the passivation layer or the dielectric layer, but are stored in the protective layer, the passivation layer or the dielectric layer, so that a charging effect is generated, secondary electron excitation of the protective layer and the passivation layer and the dielectric layer at the lower layer is influenced, the junction morphology observed by the scanning electron microscope is unclear, and even the junction morphology cannot be observed.
Disclosure of Invention
Based on this, there is a need for a method of preparing SiC device samples.
A method for preparing a SiC device sample, comprising:
removing the non-conductive protective layer on the surface of the SiC device;
forming a longitudinal section of the SiC device, and exposing a junction structure to be observed;
forming a conductive layer covering the surface of the SiC device and the longitudinal section;
and removing at least part of the conductive layer on the longitudinal section to form the SiC device sample.
According to the preparation method of the SiC device sample, the non-conductive protective layer on the surface of the SiC device sample is removed, and then the conductive layer is formed on the surface, so that when the electron beam emitted by a scanning electron microscope is used for scanning the junction morphology of the longitudinal section of the SiC device, primary electrons can be guided away by the conductive layer on the surface of the SiC device sample, and cannot be stored in the non-conductive layers such as the passivation layer or the dielectric layer, and the generation of the charging effect is avoided. Therefore, for the junction structure of the passivation layer and the region covered by the metal layer below the dielectric layer, the secondary electron excitation of the metal layer is not even slightly influenced, and the appearance of the junction can be clearly observed by a scanning electron microscope; for the morphology of the junction in the regions not covered by the metal layer, secondary electrons are generated when the conductive layer on the surface is excited, so that the morphology of the junction in the regions can be observed. And the conducting layer on the longitudinal section of the SiC device sample is removed, so that when the appearance of the junction on the longitudinal section is observed by using a scanning electron microscope, the phenomenon that the appearance of the junction on the longitudinal section is influenced due to the fact that secondary electrons on a junction area (such as a P-type area or an N-type area) on the longitudinal section are excited by the conducting layer on the longitudinal section can be avoided. Therefore, the preparation method of the SiC device sample can clearly observe the junction morphology of the longitudinal section of the SiC device sample.
In one embodiment, the step of forming a conductive layer covering the surface and the longitudinal section of the SiC device comprises: covering a protective material on the selected interested area in the longitudinal section; a junction structure is present in the region of interest;
the step after forming the conductive layer covering the surface of the SiC device and the cross section comprises: removing the protective material on the region of interest.
In one embodiment, the step of removing at least part of the conductive layer on the longitudinal section to form the SiC device sample is to remove the conductive layer in a selected region of interest in the longitudinal section, so as to form the SiC device sample with the junction morphology in the region of interest observed by a scanning electron microscope; wherein a junction structure is present in the region of interest.
In one embodiment, the step of removing the conductive layer in the selected region of interest in the longitudinal section is to bombard the selected region of interest in the longitudinal section with inert gas ions to remove the conductive layer in the region of interest.
In one embodiment, the step of removing at least part of the conductive layer on the longitudinal section is to remove the conductive layer on the whole longitudinal section by using a polishing process.
In one embodiment, after the forming of the conductive layer covering the surface of the SiC device and the longitudinal section, the step of removing at least part of the conductive layer on the longitudinal section includes:
scanning the surface of the SiC device by using an electron beam emitted by a scanning electron microscope;
detecting whether a charging effect occurs on the surface of the SiC device;
and if so, returning to the step of forming the conductive layer covering the surface of the SiC device and the longitudinal section so as to increase the thickness of the conductive layer.
In one embodiment, the step of forming the conductive layer covering the surface of the SiC device and the longitudinal section is forming the conductive layer covering the surface of the SiC device and the longitudinal section by a sputtering process.
In one embodiment, the protective layer is a polyimide layer.
In one embodiment, the step of forming a longitudinal section of the SiC device to expose a junction structure to be observed includes:
polishing is performed on the longitudinal section until the junction structure to be observed is exposed.
A junction morphology analysis method of the SiC device is also provided, which comprises the following steps:
preparing a SiC device sample according to the method of any of the embodiments described herein;
and acquiring the junction morphology data of the SiC device sample by using a scanning electron microscope.
Drawings
FIG. 1 is a schematic structural view of a SiC device in one embodiment;
FIG. 2 is a schematic flow chart of a method of preparing a sample SiC device in one embodiment;
FIG. 3 is a schematic diagram of the structure of a sample SiC device formed in one embodiment;
fig. 4 is a schematic flow chart of a method for manufacturing a SiC device sample in another embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the preparation method of the SiC device sample in the embodiment of the present application, the finally formed SiC device sample with the junction morphology observed by a scanning electron microscope may be prepared based on the SiC device in fig. 1. The SiC device may be a power device such as a schottky diode and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
The SiC device in fig. 1 includes a SiC substrate 110, a metal layer 120, a passivation layer 130, a dielectric layer 140, and a protective layer 150. As can be seen in the vertical cross section of the SiC device in fig. 1, P-type and N-type regions are also implanted in the SiC substrate, so there is an implanted junction in the SiC substrate. The SiC device of fig. 1 has a structure in which a dielectric layer 140 is located on a SiC substrate 110, a passivation layer 130 is located on the dielectric layer 140, a metal layer 120 is located between a portion of the passivation layer 130 and a portion of the dielectric layer 140, and a protective layer 150 is located on the passivation layer 130. Specifically, the protective layer 150 may be a polyimide protective layer, which may be present in the form of a film on the passivation layer 130. The passivation layer 150, the passivation layer 130, and the dielectric layer 140 are all non-conductive and belong to a non-conductive layer.
Fig. 2 is a schematic flow chart of a method of manufacturing a sample SiC device in one embodiment of the present application. The junction morphology can be but is not limited to the morphology of an implanted junction on a longitudinal section of a SiC device sample, and the depth of implantation of a corresponding region can be seen by observing the junction morphology of the implanted junction on the longitudinal section. Referring to fig. 2, a SiC device sample is prepared by taking the SiC device in fig. 1 as an example, and the preparation method includes:
Specifically, the protective layer 150 on the surface of the SiC device may be removed by bombarding the protective layer 150 with plasma generated by a plasma etcher.
After the protective layer 150 removing step, the surface of the SiC device can be observed by using a microscope to see whether the residual protective layer 150 remains, and if so, the protective layer 150 removing step is performed again until the protective layer 150 is not observed by the microscope.
Specifically, after forming a longitudinal section of the SiC device, polishing is performed on the longitudinal section of the SiC device until the longitudinal section exposes a junction structure to be observed.
Polishing refers to a machining method in which the surface roughness of a workpiece is reduced by mechanical, chemical, or electrochemical actions to obtain a bright, flat surface.
In the step, after the protective layer 150 is removed, the dielectric layer 140 and the passivation layer 130 still exist in the SiC device, then the SiC device is longitudinally cut to form a longitudinal section of the SiC device, and then the longitudinal section is polished until the position of the junction appearance needs to be observed.
At step 206, a conductive layer is formed overlying the surface of the SiC device and the longitudinal profile of the SiC device.
The conductive layer is a film formed of a conductive metal material, and has a thickness of 2 to 3 nm. The metal material may specifically be platinum (Pt) or the like.
In one embodiment, step 206 is to form a conductive layer overlying the surface of the SiC device and the longitudinal profile of the SiC device using a sputtering process.
It should be noted that the sputtering process is a process of bombarding the surface of a solid with particles (ions or neutral atoms, molecules) with certain energy, so that the atoms or molecules near the surface of the solid obtain enough energy to finally escape from the surface of the solid. In this embodiment, the metal body may be placed in a cavity of a plasma machine, and the plasma machine bombards the surface of the metal body with particles (ions, neutral atoms, and molecules) having a certain energy, so that the metal atoms or molecules obtain a sufficient energy to escape from the surface of the metal body and deposit on the surface of the SiC device and the longitudinal section of the SiC device.
And 208, removing the conducting layer on the longitudinal section of the SiC device to form a SiC device sample, wherein the SiC device sample is a SiC device sample with the junction morphology observed by a scanning electron microscope.
A schematic of the structure of the resulting SiC device sample is shown in fig. 3, with the junction morphology observed in longitudinal section in dashed lines in fig. 3. The junction may be, but is not limited to, an implanted junction.
In one embodiment, the conductive layer on the entire longitudinal section can be removed, and the step of removing the conductive layer on the longitudinal section is to remove the conductive layer formed on the longitudinal section by using a polishing process. Specifically, if the conductive layer is formed by a sputtering process, the step of removing the conductive layer on the longitudinal section is to remove the conductive layer formed on the longitudinal section by the sputtering process by a polishing process.
In another embodiment, the conductive layer on the longitudinal section of the SiC device can be removed, and then the step of removing the conductive layer on the longitudinal section of the SiC device is to bombard a selected region of interest in the longitudinal section with inert gas ions to remove the conductive layer in the region of interest, so as to form a SiC device sample for observing the junction morphology in the region of interest by a scanning electron microscope, thereby realizing observation of the micro-region; wherein a junction structure is present in the region of interest.
It should be noted that the region of interest may be a local region on the longitudinal section which is specified by a user such as a designer to be observed, in which a junction structure exists; the region of interest may also be the entire longitudinal cross-sectional area of the SiC device. This embodiment may be embodied by bombarding the conductive layer of the region of interest with a dedicated device that generates inert gas ions using Ion Milling (Ion thinning apparatus).
In one embodiment, the steps before step 206 include: covering a protective material on the selected region of interest; a junction structure is present in the region of interest; then, forming a conductive layer overlying the surface of the SiC device and the longitudinal profile includes the step of removing the protective material over the region of interest. In this embodiment, the protective material may be a barrier material and may be a material that is easily selectively removed, such as a photoresist. Before the conductive layer is formed on the longitudinal section, the interested area is coated with a protective material, so that the junction structure can be protected from being damaged by the processes of bombardment, sputtering and the like when the conductive layer is formed on the interested area.
In this embodiment, the region of interest covered with the protective material in the longitudinal section may also be plated with a conductive layer when plating the surface and the longitudinal section of the SiC device with the conductive layer, and then, the step of removing the conductive layer in the longitudinal section to form the SiC device sample may be removing the conductive layer in the region of interest in the longitudinal section and the protective material in the region of interest to form the SiC device sample without the conductive layer and the protective material in the region of interest.
In order to reduce the probability of charging effect by the protective layer 150 on the surface of the SiC device as much as possible, the thickness of the conductive layer may be increased appropriately when forming the conductive layer covering the surface of the SiC device and the longitudinal section of the SiC device. In one embodiment, referring to fig. 4, after forming the conductive layer covering the surface of the SiC device and the longitudinal section of the SiC device, the step of removing the conductive layer on the longitudinal section includes:
and 402, scanning the surface of the SiC device by using electron beams emitted by a scanning electron microscope.
And step 404, detecting whether the surface of the SiC device generates a charging effect, if so, returning to the step of forming a conductive layer covering the surface of the SiC device and the longitudinal section of the SiC device so as to increase the thickness of the conductive layer.
The charging effect on the surface of the SiC device can be determined by, but is not limited to, the following specific examples:
specifically, a metal wire may be led out from the surface of the SiC device, and if a current is detected on the metal wire, it indicates that the primary electrons hitting the surface of the SiC device are conducted away, and it indicates that no charging effect occurs on the surface of the SiC device. If no current is detected on the metal wire, it indicates that primary electrons striking the surface of the SiC device are not conducted away and stored in the protective layer 150, the passivation layer 130 and the dielectric layer 140, it indicates that a charging effect occurs on the surface of the SiC device, the conductive layer on the surface of the SiC device is not sufficiently covered, and the conductive layer needs to be thickened in subsequent steps.
Specifically, after a conductive layer covering the surface of the SiC device and the longitudinal section of the SiC device is formed, the surface of the SiC device is scanned by a scanning electron microscope, and if the pattern of the obtained surface of the SiC device has a state of deformation, divergence, blur, constant change, or the like, it is described that the polyimide layer on the surface of the SiC device is not completely removed, and it is determined that the charging effect occurs on the surface of the SiC device.
In general, the semiconductor coating process is to coat a nano-scale film on the surface of the device. Then, after the conductive layer is formed on the surface and the longitudinal section of the SiC device for the first time in this embodiment, if a charging effect is detected on the surface of the SiC device, which indicates that the conductive layer may be too thin, or the conductive layer may not completely cover the surface of the SiC device, etc., then the step of forming the conductive layer may be performed again to increase the thickness of the conductive layer on the surface of the SiC device. In this way, in the case where a thick conductive layer is formed only once on the surface of the SiC device and the longitudinal section of the SiC device, the conductive material can be saved by the manufacturing method of this embodiment. And for the situation that a very thin conductive film is plated on the surface of the SiC device and the longitudinal section of the SiC device each time, the probability of the charging effect on the surface of the SiC device can be greatly reduced by using the preparation method of the embodiment in the process of observing the junction appearance of the longitudinal section by using a scanning electron microscope.
In the preparation method of the SiC device sample in the embodiment of the application, the non-conductive protective layer 150 on the surface of the SiC device sample is removed, and then a conductive layer is formed on the surface, so that when the junction morphology of the longitudinal section of the SiC device is scanned by using an electron beam emitted by a scanning electron microscope, primary electrons are guided away by the conductive layer on the surface of the SiC device sample and cannot be stored in the non-conductive layers such as the passivation layer 130 or the dielectric layer 140, and the generation of a charging effect is avoided.
Thus, for the junction structure in the region covered by the metal layer 120 under the passivation layer 130 and the dielectric layer 140, the secondary electron excitation of the metal layer 120 is not even less affected, and the appearance of the junction can be clearly observed by a scanning electron microscope; for the junction morphology of the regions not covered by the metal layer 120, the secondary electrons are generated due to the excited conductive layer on the surface, so that the junction morphology of the regions can be observed.
And the conducting layer on the longitudinal section of the SiC device sample is removed, so that when the appearance of the junction on the longitudinal section is observed by using a scanning electron microscope, the phenomenon that the appearance of the junction on the longitudinal section is influenced due to the fact that secondary electrons on a junction region (such as a P-type region or an N-type region) on the longitudinal section are excited by the conducting layer on the longitudinal section can be avoided. Therefore, the preparation method of the SiC device sample can clearly observe the junction morphology of the longitudinal section of the SiC device sample.
In the preparation method of the SiC device sample in the embodiment of the application, the conducting layer is plated on the non-conducting layer, the conducting layer does not exist on the longitudinal section of the SiC device, or the conducting layer is plated on the non-conducting layer and a non-interested region on the longitudinal section of the SiC device, the conducting layer does not exist in the interested region, and the conducting layer is plated locally.
The embodiment of the application also provides a junction morphology analysis method of the SiC device, which comprises the steps of firstly preparing a SiC device sample according to the preparation method in any embodiment of the application, and then obtaining junction morphology data of the SiC device sample by using a scanning electron microscope. The junction structure of the SiC device sample can be an implanted junction, and the junction topographic data can include implantation depth data for an implanted region of the SiC device sample.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent should be subject to the appended claims.
Claims (9)
1. A preparation method of a SiC device sample is characterized by comprising the following steps:
removing the non-conductive protective layer on the surface of the SiC device;
forming a longitudinal section of the SiC device, and exposing a junction structure to be observed;
forming a conductive layer covering the surface of the SiC device and the longitudinal section;
removing at least part of the conductive layer on the longitudinal section to form a SiC device sample; the at least partially conductive layer comprises a conductive layer in a region of interest;
wherein the step of forming a conductive layer covering the surface of the SiC device and the longitudinal profile comprises: covering the selected region of interest in the longitudinal section with a protective material; a junction structure is present in the region of interest;
the step after forming the conductive layer covering the surface of the SiC device and the longitudinal section includes: removing the protective material on the region of interest.
2. The method of claim 1, wherein the step of removing at least a portion of the conductive layer in the longitudinal section to form a SiC device sample is removing the conductive layer in selected regions of interest in the longitudinal section to form a SiC device sample having a junction morphology in the regions of interest observed by a scanning electron microscope; wherein a junction structure is present in the region of interest.
3. The method of claim 2,
the step of removing the conductive layer in the selected region of interest in the longitudinal section is to bombard the selected region of interest in the longitudinal section with inert gas ions to remove the conductive layer in the region of interest.
4. The method according to claim 1, wherein the step of removing at least part of the conductive layer on the longitudinal section is removing the conductive layer on the entire longitudinal section by a polishing process.
5. The method of claim 1, wherein after forming the conductive layer covering the surface of the SiC device and the longitudinal profile, the step prior to removing at least a portion of the conductive layer on the longitudinal profile comprises:
scanning the surface of the SiC device by using an electron beam emitted by a scanning electron microscope;
detecting whether a charging effect occurs on the surface of the SiC device;
and if so, returning to the step of forming the conductive layer covering the surface of the SiC device and the longitudinal section so as to increase the thickness of the conductive layer.
6. The method according to any one of claims 1 to 5,
the step of forming the conductive layer covering the surface of the SiC device and the longitudinal section is to form the conductive layer covering the surface of the SiC device and the longitudinal section by a sputtering process.
7. The method according to any one of claims 1 to 5,
the protective layer is a polyimide layer.
8. The method of any of claims 1-5, wherein the step of forming a longitudinal profile of the SiC device to expose a junction structure to be observed comprises:
polishing is performed on the longitudinal section until the junction structure to be observed is exposed.
9. A junction morphology analysis method of a SiC device is characterized by comprising the following steps:
preparing a SiC device sample according to the method of any one of claims 1-8;
and acquiring the junction morphology data of the SiC device sample by using a scanning electron microscope.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6303399B1 (en) * | 2000-09-12 | 2001-10-16 | Advanced Micro Devices Inc. | Method of sample preparation for electron microscopy |
| EP1241705A1 (en) * | 2001-03-14 | 2002-09-18 | Sharp Kabushiki Kaisha | Process of manufacturing electron microscopic sample for analysing a semiconductor device |
| CN102569115A (en) * | 2010-12-23 | 2012-07-11 | 无锡华润上华半导体有限公司 | Detection method of semiconductor device defect |
| CN103196713A (en) * | 2013-02-27 | 2013-07-10 | 上海华力微电子有限公司 | Preparation method of analysis samples |
| CN103543044A (en) * | 2012-07-17 | 2014-01-29 | 无锡华润上华半导体有限公司 | Preparation method for section shape analyzing sample of MEMS (micro electro mechanical systems) device |
| JP2017199540A (en) * | 2016-04-27 | 2017-11-02 | 学校法人関西学院 | Standard sample with inclined support table, method for evaluating scan type electron electroscope and method of evaluating sic substrate |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4627682B2 (en) * | 2005-05-27 | 2011-02-09 | 株式会社日立ハイテクノロジーズ | Sample preparation apparatus and method |
| EP2749863A3 (en) * | 2012-12-31 | 2016-05-04 | Fei Company | Method for preparing samples for imaging |
-
2018
- 2018-09-20 CN CN201811098038.1A patent/CN110940689B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6303399B1 (en) * | 2000-09-12 | 2001-10-16 | Advanced Micro Devices Inc. | Method of sample preparation for electron microscopy |
| EP1241705A1 (en) * | 2001-03-14 | 2002-09-18 | Sharp Kabushiki Kaisha | Process of manufacturing electron microscopic sample for analysing a semiconductor device |
| CN102569115A (en) * | 2010-12-23 | 2012-07-11 | 无锡华润上华半导体有限公司 | Detection method of semiconductor device defect |
| CN103543044A (en) * | 2012-07-17 | 2014-01-29 | 无锡华润上华半导体有限公司 | Preparation method for section shape analyzing sample of MEMS (micro electro mechanical systems) device |
| CN103196713A (en) * | 2013-02-27 | 2013-07-10 | 上海华力微电子有限公司 | Preparation method of analysis samples |
| JP2017199540A (en) * | 2016-04-27 | 2017-11-02 | 学校法人関西学院 | Standard sample with inclined support table, method for evaluating scan type electron electroscope and method of evaluating sic substrate |
Non-Patent Citations (3)
| Title |
|---|
| Sample preparation technique for delineating interfacial films on device multilayer structures;Anonymous;《IBM Technical Disclosure Bulletin》;19850930;第28卷(第4期);第1753-4页 * |
| 扫描电子显微镜在半导体工艺中的应用技术研究;王嵩宇;《微处理机》;20040630(第3期);第10-11页 * |
| 扫描电镜剖面EBIC方法;唐圣明;《电子显微学报》;19880629(第3期);第235页 * |
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