CN110938434B - Etching method of inner side wall, etching gas and preparation method of nanowire device - Google Patents

Etching method of inner side wall, etching gas and preparation method of nanowire device Download PDF

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CN110938434B
CN110938434B CN201911234819.3A CN201911234819A CN110938434B CN 110938434 B CN110938434 B CN 110938434B CN 201911234819 A CN201911234819 A CN 201911234819A CN 110938434 B CN110938434 B CN 110938434B
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etching
side wall
nanowire device
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hard mask
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CN110938434A (en
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李俊杰
周娜
李永亮
王桂磊
张青竹
杨涛
殷华湘
李俊峰
王文武
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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Abstract

The invention relates to an etching method of an inner side wall, etching gas and a preparation method of a nanowire device, belonging to the technical field of semiconductorsThe problem that materials such as side wall materials, silicon and a top hard mask in the groove cannot be obtained at the same time in the prior art is solved. Gas for etching inner sidewall of nanowire device, comprising CH2F2、CH4、O2And Ar, the ratio of the components is 1:1:1: 2-1: 1:1:5, the upper radio frequency power is 100-1000W in the etching process, and the lower radio frequency power is 10-80W; the power of the lower electrode is 0-60W, and the temperature of the base is-20-90 ℃. The preparation method of the nanowire device comprises the following steps: epitaxially laminating a hard mask on a substrate; transversely etching the SiGe layer to form a filling gap with a preset length; depositing an inner side wall material; and etching to remove the material of the inner side wall outside the filled gap to form the inner side wall. The invention not only can reserve the side wall material in the groove, but also can realize the high selection ratio of materials such as silicon, a top hard mask and the like.

Description

Etching method of inner side wall, etching gas and preparation method of nanowire device
Technical Field
The invention relates to the technical field of semiconductors, in particular to an etching method of an inner side wall, etching gas and a preparation method of a nanowire device.
Background
After the CMOS technology enters the 3-5 nm technology generation, in order to enhance the gate control of the device and overcome the short channel effect, a stacked gate all around device (GAA) will be the mainstream development direction, wherein the inner sidewall is an important technology (as shown in the following flow chart), which can control the effective gate length, reduce the leakage between the gate and the source and drain, and reduce the parasitic capacitance. However, the formation of the inner side wall needs accurate anisotropy, has high selection ratio to materials except for the inner side wall, can strictly control the etching precision, not only ensures that the end of the nanowire has no side wall material residue, but also keeps enough side wall material in the concave part, and therefore, the control difficulty is extremely high.
With the conventional RIE plasma anisotropic etching, although the sidewall material in the recess can be retained, it is difficult to obtain a high selectivity ratio for other materials such as silicon and the top hard mask material, as shown in fig. 1 and 2. As can be seen in FIG. 1, the top SiO2the/SiN hard mask cannot be retained and the sidewalls are damaged.
As can be seen in fig. 2, the bottom is damaged.
With the conventional RIE plasma biased isotropic etching, although a high selectivity to other materials can be achieved, it is difficult to control the sidewall material remaining in the recess, as shown in fig. 3 and 4. As can be seen from fig. 3 and 4, the top SiN is hollowed out and the sidewall material in the recess is hollowed out. As can be seen from fig. 4, although the whole is etched clean, the material in the sidewall recess is not successfully retained.
Disclosure of Invention
In view of the above analysis, the present invention aims to provide an etching method for an inner sidewall, an etching gas, and a method for manufacturing a nanowire device, so as to solve the problem that the existing etching method cannot achieve the compatibility of the sidewall material in the groove and the high selectivity of the materials such as silicon and the top hard mask.
The purpose of the invention is mainly realized by the following technical scheme:
in one aspect, the invention provides a gas for etching an inner sidewall of a nanowire device, wherein the etching gas comprises CH2F2、CH4、O2And Ar.
On the basis of the scheme, the invention is further improved as follows:
further, each component CH in the etching gas is calculated according to volume percentage2F2/CH4/O2The ratio of/Ar is 1:1:1:2 to 1:1:1: 5.
On the other hand, the present inventionThe invention also provides an etching method of the inner side wall of the nanowire device, the etching gas is adopted, and the flow rate of each component in the etching process is CH2F2：10～30sccm，CH4：10～30sccm，O2：10～30sccm，Ar 40～100sccm。
Furthermore, an ICP etching machine is used in the etching process, the upper radio frequency power is 100-1000W, and the lower radio frequency power is 10-80W.
Furthermore, the power of the lower electrode is 0-60W, and the temperature of the base is-20-90 ℃.
In addition, the invention also provides a preparation method of the nanowire device, which comprises the following steps:
step S1: extending Si and SiGe lamination and a hard mask on a substrate;
step S2: laterally etching the SiGe layer using CF4/C4F8Carrying out plasma selective etching to form a filling gap with a preset length;
step S3: depositing inner side wall materials in the filling gaps and on the exposed surfaces of the other structural layers;
step S4: and removing the material of the inner side wall outside the filled gap by adopting the etching method of claims 3-5 to form the inner side wall.
Further, in step S2, CF is calculated by volume percentage4/C4F8The ratio of (A) to (B) is 2: 1-10: 1.
Further, in step S2, the flow rate of the etching gas is CF4：100～200sccm，C4F8：10～100sccm。
Further, step S1 specifically includes the following steps:
step S11: forming a laminated part and a false gate on a substrate, wherein the laminated part is positioned on the surface of the substrate and comprises a Si layer and a SiGe layer which are alternately arranged, and the false gate is positioned on the surface of the laminated part far away from the substrate;
step S12: and depositing a hard mask on the outer surface of the false gate.
Further, the hard mask is SiO2A layer and/or a SiN layer.
The invention can realize at least one of the following beneficial effects:
(1) by selecting the Composition (CH) of a particular etching gas2F2/CH4/O2And Ar) not only can reserve the side wall material in the groove, but also can realize high selection ratio of materials such as silicon, a top hard mask and the like.
(2) By controlling the components CH in the etching gas2F2/CH4/O2The ratio of/Ar is 1:1:1: 2-1: 1:1:5, which is beneficial to controlling the etching morphology.
(3) By controlling the upper radio frequency power to be 100-1000W and the lower radio frequency power to be 10-80W, a certain etching rate (not less than 1nm/min) can be ensured, and other materials such as SiO can be etched2The etching selectivity is not lower than 5: 1.
(4) The temperature of the base is controlled to be-20-90 ℃, so that a certain etching rate (not less than 1nm/min) can be ensured, anisotropic etching can be realized, and an inner side wall structure is reserved.
(5) By controlling the flow rate of each component in the etching gas to CH2F2：10～30sccm，CH4：10～30sccm，O2: 10-30 sccm and Ar 40-100 sccm, which can ensure a certain etching rate (not less than 1nm/min) and ensure the etching of other materials such as SiO2The etching has high selection ratio which is not lower than 5:1, and the side wall roughness can not occur.
(6) By controlling CF in the etching gas4:C4F8In such a ratio that the sidewall GeO can be etchedyMaterial, and can control etching to stay in GeOyThe material does not etch the SiGe material below, so that the etching depth of the cavity can be accurately controlled, and the thickness of the inner side wall can be further controlled.
In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 shows RIE plasma anisotropic etching resulting in top SiO2the/SiN hard mask cannot be reserved, and the side wall is damaged;
FIG. 2 is a graph of bottom damage caused by RIE plasma anisotropic etching;
FIG. 3 is a diagram of the top SiN being undercut and the sidewall material in the recess being undercut as a result of RIE plasma partial isotropic etching;
FIG. 4 is a low power electron microscope image of FIG. 3;
FIG. 5 is a macroscopic view of a method for fabricating a nanowire device, where (a) is the epitaxy of Si and SiGe stacks, dummy gates and SiO on a substrate2And/or SiN after hard mask, (b) after selective lateral etching SiGe, (c) after depositing inner side wall material in the filled gap and on the exposed surface of other structure layer, and (d) after etching with the special plasma etching gas;
FIG. 6 is a microscopic view of the fabrication method of the nanowire device, wherein (a) is the epitaxial Si and SiGe stack, the dummy gate and SiO on the substrate2And/or SiN after hard mask, (b) after selective lateral etching SiGe, (c) after depositing inner side wall material in the filled gap and on the exposed surface of other structure layer, (d) after etching with the special plasma etching gas of the present invention, and (e) as the enlarged diagram of FIG. 6 (d);
FIG. 7 is CH4At flow rates above 30sccm, (-CH) occurs2-)nDepositing;
FIG. 8 is CH4When the flow rate is lower than 10sccm, the situation of no selection ratio occurs;
FIG. 9 is O2When the flow rate is higher than 30sccm, anisotropy can not be maintained, and an undercut schematic diagram appears;
FIG. 10 is O2Flow rates below 10sccm result in a schematic of sidewall roughness.
FIG. 11 is a schematic view of a substrate, stack of layers;
FIG. 12 is a schematic diagram of a fin formation process;
FIG. 13 is a schematic illustration of the provision of a dummy gate on the exposed surface of the fin;
fig. 14 is a schematic diagram of the fin after etching to remove portions of the fin on both sides of the sidewall.
Reference numerals:
10-a substrate; 20-strain buffer layer; 30-a lamination section; 41-false gate; 42-side wall; a 31-Si layer; a 32-SiGe layer; 310-silicon oxide; 320-germanium oxide.
Detailed Description
The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form a part hereof, and which together with the embodiments of the invention serve to explain the principles of the invention and not to limit its scope.
Example one
The invention discloses a specific embodiment of gas for etching an inner side wall of a nanowire device, which comprises the following components: CH (CH)2F2、CH4、O2And Ar.
Compared with the prior art, the embodiment can not only retain the side wall material in the groove, but also realize high selection ratio of materials such as silicon, a top hard mask and the like by optimizing the composition of the etching gas, and the selection ratio is not lower than 5: 1.
Specifically, each component CH in the etching gas2F2/CH4/O2The ratio of/Ar is 1:1:1: 2-1: 1:1:5, and the etching morphology can be accurately controlled by controlling the ratio.
Example two
The invention discloses a method for etching the inner side wall of the nanowire device. The etching method uses the etching gas of the first embodiment, and the flow rate of each component in the etching process is CH2F2：10～30sccm，CH4：10～30sccm，O2：10～30sccm，Ar40～100sccm。
Compared with the prior art, the etching method provided by the embodimentThe flow rate of each component in the etching gas is controlled to be CH2F2：10～30sccm，CH4：10～30sccm，O2: 10-30 sccm and Ar 40-100 sccm, which can ensure a certain etching rate (not less than 1nm/min) and ensure the etching of other materials such as SiO2The etching has high selection ratio which is not lower than 5:1, and the side wall roughness can not occur.
Specifically, when CH2F2When the flow rate is lower than 10sccm, the etching is stopped; at flow rates above 30sccm, etch selectivity to other materials is low, such as SiO2Has an etch selectivity of less than 5: 1.
To prevent the occurrence of (-CH)2-)nDeposition, the etching method provided in this example uses CH4The flow rate of (2) is controlled to 10 to 30 sccm. This is because, when CH4Above 30sccm, (-CH) occurs2-)nDeposition, as shown in fig. 7; when CH is present4Below 10sccm, no selectivity occurs, as shown in FIG. 8.
Considering if O is present2On the one hand, partial isotropic etching occurs and on the other hand, side wall roughness occurs, so that through innovative research, O is optimized2Will ultimately be O2The flow rate of (2) is controlled to 10 to 30 sccm. In the experiment, if O is found2If the flow rate of (2) is out of the above range, there is a problem of undercut.
Specifically, when O is2Above 30sccm, anisotropy cannot be maintained, and an undercut problem occurs, as shown in FIG. 9; when O is present2Below 10sccm, this results in a rough sidewall, as shown in FIG. 10.
From the viewpoint of improving the labor productivity, the etching rate cannot be too low, e.g., cannot be lower than 1 nm/min. This requires tight control of the flow rate of Ar, since too low or too high a flow rate of Ar will result in an etch rate of less than 1 nm/min. It was found experimentally that when the flow rate of Ar is below 40sccm, the etch rate is too low (<1 nm/min); similarly, when the flow rate of Ar is higher than 100sccm, an etching rate lower than 1nm/min is also observed. Therefore, in the etching method of the present embodiment, the flow rate of Ar is controlled to be 40-100 sccm.
It should be noted that the etching machine used in the etching method of the present embodiment is an ICP etching machine. In order to ensure a high selectivity for etching other materials, in particular for SiO2High selectivity. In the embodiment, the upper radio frequency power of the ICP etching machine is controlled to be 100-1000W, and the lower radio frequency power is controlled to be 10-80W.
Specifically, when the upper RF power is lower than 100W, the etching rate is too low (<1 nm/min); when the upper radio frequency power is higher than 1000W, the power is applied to other materials such as SiO2The etch selectivity is low, below 5: 1.
Similarly, when the lower RF power is 10W, the etching rate is too low (<1 nm/min); when the lower RF power is higher than 100W, it is suitable for other materials such as SiO2The etch selectivity is low, below 5: 1.
According to the etching method, the upper radio frequency power is controlled to be 100-1000W, and the lower radio frequency power is controlled to be 10-80W, so that a certain etching rate (not less than 1nm/min) can be ensured, and high selection ratio of etching other materials, such as SiO, can be realized2The selection ratio of (A) is not less than 5: 1.
In the experiment, the temperature of the base also has a very important influence on the etching effect, so the temperature of the base is also controlled in the etching method of the embodiment.
Specifically, when the susceptor temperature is below-20 ℃, the etching rate is too low, such as below 1 nm/min; and when the temperature of the base is higher than 90 ℃, completely isotropic etching is caused, so that the inner side wall structure cannot be reserved.
In the embodiment, the temperature of the base is controlled to be-20-90 ℃, so that a certain etching rate (not less than 1nm/min) can be ensured, anisotropic etching can be realized, and an inner side wall structure is reserved.
EXAMPLE III
In another embodiment of the present invention, as shown in fig. 5 and 6, a method for manufacturing a nanowire device is disclosed, which includes the following steps:
step S1: epitaxial Si and SiGe stacks and SiO on substrates2And/or a SiN hard mask;
step S2: adopting oxidation process to make two ends of SiGe layer produce germanium oxide and two ends of Si layer produce silicon oxide, adopting CF4/C4F8Performing plasma selective etching to remove germanium oxide generated by oxidation in the SiGe layer, so that a filling gap with a preset length is formed between the residual SiGe layer and the adjacent Si layer with silicon oxide at two ends;
step S3: depositing inner side wall materials in the filled gaps and on the exposed surfaces of other structural layers;
step S4: and removing the material of the inner side wall outside the filled gap by adopting the etching method of the second embodiment to form the inner side wall.
Specifically, step S1 includes the steps of:
step S11: forming a laminated part and a false gate on a substrate, wherein the laminated part is positioned on the surface of the substrate and comprises a Si layer and a SiGe layer which are alternately arranged, and the false gate is positioned on the surface of the laminated part far away from the substrate;
step S12: depositing SiO on the outer surface of the false gate2And/or a SiN hard mask.
Note that, in the stacked portion in step S11, the SiGe layer, the Si layer, the SiGe layer, and the like may be stacked in this order, or the Si layer, the SiGe layer, the Si layer, and the like may be stacked in this order. Specifically, the SiGe layer is deposited first or the Si layer is deposited first according to actual conditions. In addition, the number of the structural layers in the stacked part is at least three, and the specific number of the structural layers also needs to be set according to the actual situation, and is specifically determined according to the number of stacked nanowires.
Further, the number of structural layers in the stacked part was 6, and 3 nanowires were stacked.
In addition, the oxidation process in step S2 may be a single oxidation step or a plurality of oxidation steps.
In a specific embodiment of the present invention, the step S1 includes: forming a fin on the substrate 10, as shown in fig. 12, the fin including SiGe layers 32 and Si layers 31 alternately arranged; providing a dummy gate 41 on a portion of the exposed surface of the fin, as shown in fig. 13, and providing sidewalls 42 on both sides of the dummy gate, as shown in fig. 13; etching away the portions of the fins on both sides of the sidewall 42 to obtain the stacked portion 30, as shown in fig. 14.
The fin of fig. 12 may be formed by stacking a Si material and a SiGe material on the substrate 10 in this order to form a SiGe layer 32 and a Si layer 31 having a larger area, as shown in fig. 11, and then forming the fin of fig. 12 by etching. Specifically, the Si material and the SiGe material may be provided by any method available in the art, and in a specific embodiment of the present invention, a reduced pressure epitaxy process or a molecular beam epitaxy process is used. The process of forming the fin by etching may be to form a hard mask pattern by a side wall transfer technique (STL for short) or other lithography techniques, where the hard mask may be a silicon nitride layer, a silicon dioxide layer, or a stack of a silicon dioxide layer and a silicon nitride layer, and then to form the fin by etching using a dry etching process.
The step S2 includes: step S21, performing the oxidation process for 3-7 min by using a rapid thermal processing method (RTP) at 700-900 ℃ in an oxygen atmosphere; step S22, repeating the step S21 at least times to generate germanium oxide 320 at two ends of the SiGe layer 32 in the stacked part 30 and silicon oxide 310 at two ends of the Si layer 31, wherein in the step, a low temperature oxidation process is adopted and the growth is repeated for multiple times to further ensure that germanium oxide GeO is generated at two ends of the SiGe layer 32ySo that silicon oxide 310, i.e., SiO, is generated at both ends of the Si layer 31xAnd it is ensured that the SiGe layer 32 and the Si layer 31 do not mutually expand.
In order to provide stress to the SiGe layer 32 and the Si layer 31 of the subsequent stacked part 30, in an embodiment of the present invention, before step S1, the method further includes disposing a strain buffer layer 20 on the surface of the substrate 10, and the stacked part 30 is located on the surface of the strain buffer layer 20 away from the substrate 10. During the subsequent formation of the fin, part of the stress buffer layer is etched away, as shown in fig. 12.
The material of the stress buffer layer of the invention can be selected according to the actual situation, and particularly, the material with obvious Ge concentration difference with the material of the bottommost layer in the lamination part (namely, the structural layer with the minimum distance from the substrate in the lamination part) is selected, and the difference is between 20% and 90%.
Furthermore, the material of the strain buffer layer is SiGe, and the weight of Ge in the strain buffer layer accounts for 10% -50%. This can provide the necessary stress to the stack to improve device performance.
It should be noted that the substrate of the present invention can be formed of any feasible material, such as a silicon substrate or an SOI substrate, and those skilled in the art can select a specific material to form the substrate of the present invention according to actual situations.
In step S2, CF is calculated by volume percentage4/C4F8The ratio of (A) to (B) is 2: 1-10: 1. This is because: when CF4:C4F8A ratio lower than 2:1 will result in no etching of the sidewall GeOyMaterials, since too high a C/F ratio results in greater deposition than etching; when CF4:C4F8When the ratio is higher than 10:1, the etching can not be controlled to stay at GeOyThe material can also etch the SiGe material below, so that the etching depth of the cavity cannot be accurately controlled, the thickness of the subsequent inner side wall cannot be controlled, and the length of the nanowire is influenced finally.
Specifically, in step S2, the flow rate of the etching gas during etching is CF4：100～200sccm，C4F8：10～100sccm。
Compared with the prior art, in the preparation method, the germanium oxide is generated at two ends of the SiGe layer by adopting an oxidation process, the silicon oxide is generated at two ends of the Si layer, the germanium oxide generated by oxidation in the SiGe layer is removed, a filling gap with a preset length is formed between the residual SiGe layer and the adjacent Si layer with the silicon oxide at two ends, and finally, the inner side wall material is filled in the filling gap to form the inner side wall. In the method, two different oxides are obtained on two material layers of SiGe layer and Si layer in a self-alignment way by optimizing the oxidation process conditions, whereinGermanium oxide GeOyThe method has poor stability, can remove the Ge layer in water or other acid solutions at a high selectivity ratio, and can accurately control the length of a filling gap for filling the inner side wall in the Ge layer through a scheme of one-time or multiple-time oxidation so as to accurately reach a preset length, and further can subsequently form the inner side wall with an accurate length. Compared with the scheme of forming the notch by wet etching in the prior art, the process has stronger controllability. And the generated silicon oxide can also avoid the damage caused by the etching of the transverse removing part and the strong etching of the inner side, thereby being convenient for improving the performance of the device.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims (8)

1. The method for etching the inner side wall of the nanowire device is characterized in that etching gas comprises CH2F2、CH4、O2And Ar, each component CH in the etching gas2F2/CH4/O2The ratio of/Ar is 1:1:1: 2-1: 1:1:5, and the flow rate of each component in the etching process is CH2F2：10～30sccm，CH4：10～30sccm，O2：10～30sccm，Ar 40～100sccm。
2. The method for etching the inner side wall of the nanowire device as claimed in claim 1, wherein an ICP etching machine is used in the etching process, the upper radio frequency power is 100-1000W, and the lower radio frequency power is 10-80W.
3. The method for etching the inner side wall of the nanowire device according to claim 1 or 2, wherein the power of the lower electrode is 0-60W, and the temperature of the base is-20-90 ℃.
4. A method for preparing a nanowire device is characterized by comprising the following steps:
step S1: extending Si and SiGe lamination and a hard mask on a substrate;
step S2: laterally etching the SiGe layer using CF4/C4F8Carrying out plasma selective etching to form a filling gap with a preset length;
step S3: depositing inner side wall materials in the filling gaps and on the exposed surfaces of the other structural layers;
step S4: and removing the material of the inner side wall except the filled gap by adopting the etching method of any one of claims 1 to 3 to form the inner side wall.
5. The method for producing a nanowire device according to claim 4, wherein in step S2, CF is present in percentage by volume4/C4F8The ratio of (A) to (B) is 2: 1-10: 1.
6. The method for preparing a nanowire device according to claim 4 or 5, wherein in step S2, the flow rate of the etching gas is CF4：100～200sccm，C4F8：10～100sccm。
7. The method for preparing a nanowire device according to claim 4, wherein the step S1 specifically comprises the following steps:
step S11: forming a laminated part and a false gate on a substrate, wherein the laminated part is positioned on the surface of the substrate and comprises a Si layer and a SiGe layer which are alternately arranged, and the false gate is positioned on the surface of the laminated part far away from the substrate;
step S12: and depositing a hard mask on the outer surface of the false gate.
8. The method of claim 7, wherein the hard mask is SiO2A layer and/or a SiN layer.
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