CN110933253B - Data frame synchronization source end, host end, synchronization device and method - Google Patents
Data frame synchronization source end, host end, synchronization device and method Download PDFInfo
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- CN110933253B CN110933253B CN201911165019.0A CN201911165019A CN110933253B CN 110933253 B CN110933253 B CN 110933253B CN 201911165019 A CN201911165019 A CN 201911165019A CN 110933253 B CN110933253 B CN 110933253B
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Abstract
The invention discloses a data frame synchronization source end, a data frame synchronization host end, a data frame synchronization device and a data frame synchronization method. Wherein, synchronizer includes: the system comprises a host end and an information source end, wherein the host end is respectively connected with each information source end; a control mode instruction generating unit at the host end sends a control mode instruction to a mode adjusting unit at the source end according to the synchronization deviation value at the source end; the mode adjusting unit adjusts the frequency of a clock signal of a controllable clock unit at the signal source end according to the instruction of the control mode instruction generating unit; the controllable clock unit can generate clock signals with various frequencies; the data generating unit generates a data frame according to the clock signal of the controllable clock unit and sends the data frame to the host terminal. The invention gradually approaches to frame synchronization by adjusting the clock frequency, can avoid the phenomenon of frame insertion or frame dropping, has good video fluency and good impression, does not need to use cache, and reduces the cost.
Description
Technical Field
The invention belongs to the technical field of video processing, and particularly relates to a data frame synchronization source end, a data frame synchronization host end, a data frame synchronization device and a data frame synchronization method.
Background
Multiple camera shots often result in video asynchrony due to differences in the transmission lines of the cameras. At present, there are two main ways to achieve video synchronization, one is performed at the host end, and the other is performed at the video source end. The video synchronization at the host needs to store the videos captured by the cameras by using the cache and then perform the synchronization output, and the cost of the video synchronization is increased because the storage element is expensive. The method for synchronizing at the video source end mainly includes two schemes, one scheme is that a Frame Rate Conversion (FRC) technology is utilized to change the Frame Rate output by a camera so as to achieve synchronization, but because the shooting frequency of the camera is not changed, the phenomenon of Frame insertion or Frame dropping can occur when the Frame Rate is changed by the technology, the video fluency is influenced, the appearance is poor, and the FRC technology also needs to be used for caching, so the cost is high, in addition, generally, the conventional FRC uses a triple caching technology, so that 1-2 frames can be delayed, and 1.5 frames can be delayed averagely; the other is that a synchronous clock is arranged at a host end, the synchronous clock generates a clock output signal according to the actual asynchronous time difference of each camera, and the camera at the video source end uses the clock output signal to shoot.
Disclosure of Invention
In order to overcome at least one defect of high cost, poor fluency, time delay, stability and the like of a video synchronization method in the prior art of multi-camera shooting, the invention provides a signal source end, a host end, a synchronization device and a method for data frame synchronization.
In a first aspect, the present invention provides a data frame synchronization apparatus, including: a host terminal and a plurality of message source terminals;
the host side includes:
a reference frame synchronization generating unit for determining a reference frame;
the data frame synchronization processing unit is used for receiving the data frame from the source end and calculating a synchronization deviation value between the received data frame and the reference frame;
the control mode instruction generating unit is used for sending an instruction of a control mode to the information source terminal according to the synchronization deviation value;
the source terminal includes:
the controllable clock unit is used for generating clock signals with various frequencies within a preset range;
the data generating unit is used for generating a data frame according to the clock signal of the controllable clock unit and sending the data frame to the data frame synchronous processing unit;
and the mode adjusting unit is used for adjusting the frequency of the clock signal of the controllable clock unit according to the control mode command sent by the control mode command generating unit so as to reduce the synchronization deviation value.
Further, the control mode includes: an approximation mode;
the approximation mode means that the controllable clock unit adopts positive or negative frequency offset to realize clock output, so that the synchronization deviation value is reduced;
and when the synchronization deviation value is larger than a first threshold value, the control mode instruction generating unit sends the instruction of the approach mode to the mode adjusting unit.
Further, the host end further includes: a reference clock unit for generating a reference clock signal;
the source terminal further includes: the uplink clock receiving unit is used for receiving the reference clock signal generated by the reference clock unit, and the comparison filtering device is used for calculating and comparing the feedback of the clock signal output by the controllable clock unit with the received reference clock signal;
the control mode further includes: the accurate following mode refers to the fact that the comparison filtering device adjusts the clock signals generated by the controllable clock unit according to the calculation comparison result;
when the synchronization deviation value is not greater than the first threshold value, the control mode instruction generating unit sends the instruction of the precise following mode to the mode adjusting unit.
Further, the control mode further includes: a fine tuning mode;
the fine tuning mode is that the controllable clock unit adopts positive or negative frequency offset to realize clock output, so that the synchronization deviation value is reduced;
when the mode is in the accurate following mode, if the synchronization deviation value is larger than the first threshold value, the control mode instruction generating unit sends the instruction of the fine tuning mode to the mode adjusting unit.
Further, a first frequency offset and a second frequency offset of the controllable clock unit are preset, wherein the first frequency offset is greater than the second frequency offset;
in the approximation mode, the controllable clock unit realizes clock output by adopting the positive or negative first frequency offset;
in the fine tuning mode, the controllable clock unit uses the second frequency offset, which is positive or negative, to realize clock output.
Further, the first frequency offset is a maximum frequency offset of the controllable clock unit within a preset range.
Further, the controllable clock unit sets a locking frequency within a preset range;
the control mode further includes: a locking mode, wherein the locking mode refers to that the controllable clock unit performs clock output at the locking frequency;
the mode adjusting unit also detects whether the uplink clock receiving unit receives the reference clock signal;
when the mobile terminal is in the accurate following mode, if the mode adjusting unit detects that the reference clock signal is not received by the uplink clock receiving unit, the control mode instruction generating unit sends the instruction of the locking mode to the mode adjusting unit.
Further, the number of the source terminals is at least 2.
Further, the reference frame synchronization generating unit itself generates a data frame, and determines the data frame generated by itself as the reference frame.
Further, the source end is a video source end, the data generation unit is a video generation unit, and the data frame is a video frame.
In a second aspect, the present invention further provides a host for data frame synchronization, including:
a reference frame synchronization generating unit for determining a reference frame;
the data frame synchronization processing unit is used for acquiring a data frame and calculating a synchronization deviation value between the acquired data frame and the reference frame;
and the control mode instruction generating unit is used for sending an instruction of a control mode according to the synchronization deviation value.
Further, the control mode includes: an approximation mode;
when the synchronization deviation value is larger than a first threshold value, the control mode instruction generating unit sends an instruction of the approach mode;
the approach mode is that the host end informs the source end to accelerate or decelerate the clock output frequency, so that the synchronization deviation value is reduced.
Further, the host end further includes: the reference clock unit is used for generating and transmitting a reference clock signal;
the control mode further includes: a precise following mode;
when the synchronization deviation value is not larger than the first threshold value, the control mode instruction generating unit sends an instruction of the precise following mode;
the accurate following mode means that the host end informs the signal source end to calculate and compare the feedback of the clock signal output by the host end with the reference clock signal, and adjusts the clock output of the signal source end.
Further, the control mode further includes: a fine tuning mode;
when the control mode command generating unit is in an accurate following mode, if the synchronization deviation value is larger than the first threshold value, the control mode command generating unit sends a command of the fine tuning mode;
the fine tuning mode is that the host end informs the source end to adopt positive or negative frequency offset to accelerate or slow down the clock output frequency, so that the synchronization deviation value is reduced.
Further, in the approach mode, the host end notifies the source end to implement clock output by using a positive or negative first frequency offset; in the fine tuning mode, the host end informs the source end of adopting a positive or negative second frequency offset to realize clock output; the first frequency offset is greater than the second frequency offset.
Further, the host end includes at least 2 interfaces for connecting to the source end.
Further, the reference frame synchronization generating unit generates a data frame by itself, and determines the data frame generated by itself as the reference frame.
In a third aspect, the present invention provides a source end for data frame synchronization, including:
the controllable clock unit is used for generating clock signals with various frequencies within a preset range;
the data generating unit is used for generating a data frame according to the clock signal of the controllable clock unit and transmitting the data frame;
and the mode adjusting unit is used for receiving an instruction of a control mode and adjusting the frequency of the clock signal of the controllable clock unit according to the instruction of the control mode.
Further, the control mode includes: an approximation mode;
the approximation mode means that the controllable clock unit realizes clock output by adopting positive or negative frequency offset.
Further, the source side further includes:
an uplink clock receiving unit for receiving a reference clock signal;
the comparison filtering device is used for calculating and comparing the feedback of the clock signal output by the controllable clock unit with the received reference clock signal;
the control mode further includes: and the accurate following mode refers to the mode that the comparison filtering device adjusts the clock signal generated by the controllable clock unit according to the calculation comparison result.
Further, the control mode further includes: and a fine tuning mode, wherein the fine tuning mode is that the controllable clock unit realizes clock output by adopting positive or negative frequency offset.
Further, a first frequency offset and a second frequency offset of the controllable clock unit are preset, wherein the first frequency offset is greater than the second frequency offset;
in the approximation mode, the controllable clock unit realizes clock output by adopting the positive or negative first frequency offset;
in the fine tuning mode, the controllable clock unit uses the second frequency offset, which is positive or negative, to realize clock output.
Further, the first frequency offset is a maximum frequency offset of the controllable clock unit within a preset range.
Further, the controllable clock unit sets a locking frequency within a preset range;
the control mode further includes: a locking mode, wherein the locking mode refers to that the controllable clock unit performs clock output at the locking frequency;
the mode adjusting unit also detects whether the uplink clock receiving unit receives the reference clock signal;
when the mobile terminal is in the accurate following mode, if the mode adjusting unit detects that the reference clock signal is not received by the uplink clock receiving unit, the mode adjusting unit executes the locking mode.
Further, the data generation unit is a video generation unit, and the data frame is a video frame.
In a fourth aspect, the present invention provides a data frame synchronization method, including the following steps:
s1: determining a reference frame;
s2: acquiring a data frame sent by a source end, and calculating a synchronization deviation value between the acquired data frame and the reference frame;
s3: sending a control mode instruction to the information source terminal according to the synchronization deviation value;
s4: the source end adjusts the frequency of a clock signal generated by a controllable clock unit of the source end according to the instruction of the control mode, so that the synchronization deviation value is reduced;
s5: and the signal source end generates a data frame according to the clock signal and sends the data frame to the host end.
Further, the control mode includes: an approximation mode, wherein the approximation mode is that a controllable clock unit at the signal source end adopts positive or negative frequency offset to realize clock output, so that the synchronization deviation value is reduced;
step S3 includes the following steps:
s31: presetting a first threshold value of a synchronization deviation value;
s32: and when the synchronization deviation value is larger than the first threshold value, sending an instruction of the approach mode to the information source terminal.
Further, the data frame synchronization method further includes the following steps: sending a reference clock signal to the information source terminal;
the control mode further includes: the accurate following mode is that the signal source end calculates and compares the feedback of the clock signal generated by the controllable clock unit of the signal source end with the received reference clock signal, and adjusts the frequency of the clock signal generated by the controllable clock unit according to the calculation and comparison result;
step S3 further includes the steps of:
s33: and when the synchronization deviation value is not greater than the first threshold value, sending an instruction of the accurate following mode to the information source terminal.
Further, the control mode further includes: a fine tuning mode, wherein the fine tuning mode is that a controllable clock unit at the signal source end adopts positive or negative frequency offset to realize clock output, so that the synchronization deviation value is reduced;
step S3 further includes the steps of:
s34: and when the information source terminal is in an accurate following mode, if the synchronization deviation value is greater than the first threshold value, sending a fine tuning mode instruction to the information source terminal.
Further, the data frame synchronization method further includes: presetting a first frequency offset and a second frequency offset of a controllable clock unit of the signal source end, wherein the first frequency offset is greater than the second frequency offset;
in the approximation mode, the controllable clock unit realizes clock output by adopting the positive or negative first frequency offset;
in the fine tuning mode, the controllable clock unit uses the second frequency offset, which is positive or negative, to realize clock output.
Further, the first frequency offset is a maximum frequency offset of the controllable clock unit within a preset range.
Further, the data frame synchronization method further includes: the controllable clock unit sets a locking frequency within a preset range;
the control mode further includes: the locking mode refers to that a controllable clock unit of the signal source end carries out clock output under the locking frequency;
step S3 further includes the steps of:
s35: and when the signal source terminal is in the accurate following mode, if the signal source terminal is detected not to receive the reference clock signal, sending a command of the locking mode to the signal source terminal.
Further, the number of the source terminals is at least 2.
Further, in step S1, the host determines the self-generated data frame as the reference frame.
Further, the source end is a video source end, and the data frame is a video frame.
The invention has the following beneficial effects:
1. the invention realizes the frame synchronization of each information source end by adjusting the clock frequency of the information source end, and can avoid the phenomenon of inserting frames or discarding frames, so the video has good fluency and good impression.
2. The invention realizes the frame synchronization of each signal source end directly by adjusting the clock frequency of the signal source end without using a buffer memory, can reduce the time delay and avoid the time delay caused by the conventional FRC technology.
3. In the gradual approaching process, the source end does not need to use a cache, so that storage elements are saved, and the cost is reduced.
Drawings
Fig. 1 is a schematic overall structure diagram of a first embodiment of the present invention.
Fig. 2 is a schematic diagram of an implementation process of the first embodiment of the invention.
Fig. 3 is a schematic diagram of an optimized implementation process according to a first embodiment of the present invention.
FIG. 4 is a schematic overall flow chart of the second embodiment of the present invention.
FIG. 5 is a detailed flowchart of a step in the second embodiment of the present invention.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the patent; for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the present patent.
Example one
As shown in fig. 1, the present invention provides a data frame synchronization apparatus, including: the host end is connected with the two source ends respectively. Fig. 1 shows only two source terminals as an example, but in practice, those skilled in the art can reasonably set the number of source terminals, host terminals and various source terminals according to actual needs.
In this embodiment, the signal source terminal is a camera device, and can collect a video signal, where the video signal includes an image of one frame. The host end can be a video processor, and can perform synthesis processing on the acquired video signals. Specifically, as shown in fig. 1, the host side includes: a reference frame synchronization generating unit, a data frame synchronization processing unit and a control mode instruction generating unit; the source side includes: a mode adjustment unit, a controllable clock unit and a data generation unit.
The reference frame synchronization generating unit is used for determining a reference frame; the data frame synchronization processing unit is used for receiving the data frames sent by the data generating units of the at least two source terminals and calculating the synchronization deviation value between the data frames sent by each source terminal and the reference frame.
The control mode instruction generating unit sends an instruction of a control mode to the mode adjusting unit according to the synchronization deviation value; the mode adjusting unit adjusts the frequency of the clock signal of the controllable clock unit according to the instruction of the control mode, so that the data frame generated by the data generating unit approaches the reference frame, namely the synchronization deviation value is reduced; the controllable clock unit can generate clock signals with various frequencies within a preset range; the data generating unit generates a data frame according to the clock signal of the controllable clock unit and sends the data frame to the data frame synchronization processing unit.
Taking the image pickup device as an example, the controllable clock unit works at a default vibration frequency to send out a clock signal, the data generation unit works at a default speed according to the clock signal of the controllable clock unit to generate a frame of video data frame, and after the frame of video data frame is generated, the data frame is sent out to the host terminal. A reference frame synchronization generating unit of a host end determines a reference frame, and a data frame synchronization processing unit calculates a synchronization deviation value between the received data frame and the reference frame after receiving the data frame sent by a signal source end. Since there are multiple source terminals, and each source terminal does the same thing, the data frame synchronization processing unit receives the data frame sent by each source terminal, and calculates the synchronization deviation value between each source data frame that has arrived at the host terminal and the reference frame. The control mode instruction generating unit judges according to the synchronization deviation value, if the synchronization deviation value is within a certain threshold value range, the time deviation is not considered to occur, and synchronization related adjustment on a corresponding information source end is not needed. If the deviation value exceeds a certain threshold value, the source data frame is considered to have time deviation, and the corresponding source end needs to be adjusted in a synchronous correlation mode. Subsequently, the control mode instruction generating unit sends an instruction of the control mode to the source end, and the source end is required to perform synchronization related adjustment. The mode adjustment unit at the source end determines, according to the instruction of the control mode instruction generation unit, to perform synchronization-related adjustment on the source end, where a specific adjustment manner is, as shown in the following embodiment, to adjust a clock signal of the controllable clock unit. The controllable clock unit is adjusted such that the frequency of the vibrations changes, and the clock signal is generated at another frequency within the predetermined range. The data generating unit also operates at another rate to generate a data frame and transmit the data frame as the frequency changes. On the other hand, because the working rate of the source end changes, the frequency of the data frame received by the host end also changes correspondingly, so that the time difference between the received data frame and the reference frame is reduced, the synchronization deviation value is also reduced correspondingly, and finally the synchronization between the received data frame and the reference frame is achieved.
Although the working speed of the source end is changed, the influence is only the time of forming a single data frame, the video frames output by the source end are continuous, and after the received source video signals are synchronized and subjected to homologous processing in the host end, the total amount of the video frames of each source in the same time interval is the same, so that the problem of poor picture fluency caused by frame dropping or frame inserting can be solved
In one embodiment, a first threshold value of the synchronization deviation value is preset; the control modes include: an approximation mode, wherein the approximation mode is that a controllable clock unit at a signal source end adopts positive or negative frequency offset to realize clock output, so that a data frame generated by a data generation unit approximates to a reference frame, namely, a synchronization deviation value is reduced; and when the synchronization deviation value is larger than the first threshold value, the control mode instruction generating unit sends an instruction of an approach mode to the mode adjusting unit. When the synchronization deviation value exceeds a certain threshold value, it is determined that synchronization related adjustment is required, and at this time, an instruction of an approach mode is sent to change the frequency of the controllable clock unit at the source end to change the working rate of the data generation unit, so that the data frame approaches the reference frame, i.e., the synchronization deviation value is reduced.
For example, as shown in fig. 2, for the host, the synchronization deviation value between the reference frame and the received data frame is Δ T, where Δ T is greater than a first threshold of the preset synchronization deviation value, and the data frame is from one of the source ends. It has to be noted here that the synchronization deviation value refers to the value of the deviation between the received data frame and the reference frame, so that the synchronization deviation value is always positive regardless of whether the received data frame is faster or slower. Then, the clock signal of the controllable clock unit at the source end is adjusted to be increased from the frequency f1 to f 1', the "work efficiency" of the source end is improved due to the increase of the frequency, the output video frames are also "uprooted", Δ T gradually decreases and is not greater than the first threshold value finally, and at this time, the source end is considered to be synchronized.
It can be understood that Δ T is a preset threshold, which reflects the synchronization precision, and those skilled in the art can reasonably set Δ T according to actual situations so as to meet the engineering requirements.
It has to be noted that in the present embodiment, the frequency of the controllable clock unit is adjusted by using a frequency offset method, but it is obvious to those skilled in the art that other methods for changing the clock frequency may be used to change the frequency of the controllable clock unit. In addition, it should be noted that, since the controllable clock unit can generate clock signals with multiple frequencies within a preset range, in the approximation mode, multiple different frequencies may be used for approximation, for example, a method of first performing a large frequency offset and then performing a small frequency offset is used, or different thresholds may be preset, and different frequency offsets are used within different threshold ranges.
As shown in fig. 1, in one embodiment, the host further includes: a reference clock unit; the source end further comprises: the device comprises an uplink clock receiving unit and a comparison filtering device; the uplink clock receiving unit is used for receiving a clock signal of the reference clock unit; the comparison filtering device is used for calculating and comparing the feedback of the self output clock signal with the received clock signal of the reference clock unit. The control mode further includes: and the accurate following mode refers to a comparison filtering device adjusting the clock signal generated by the controllable clock unit according to the calculation comparison result. And when the synchronization deviation value is not greater than the first threshold value, the control mode instruction generating unit sends an instruction of an accurate following mode to the mode adjusting unit.
The process of realizing the frame synchronization of each source end through the approximation mode is a gradual approximation process, can well avoid the phenomenon of inserting frames or discarding frames, and has good video smoothness and good impression. In addition, the invention realizes the frame synchronization of each signal source end directly by adjusting the clock frequency of the signal source end without using a buffer memory, thereby reducing the time delay. In addition, due to the gradual approaching process, a buffer memory is not needed at the information source end, storage elements are saved, and the cost is reduced.
However, the reason for causing video non-synchronization is various, and even if the clock frequencies of the respective source terminals are preset to be consistent and the synchronization is performed, the frequency of one of the machines is different from that of the other machines due to other objective reasons, such as frequency drop caused by overheating, so that the videos cannot be synchronized. In view of the above, the present invention in one embodiment sets the precise following mode, and makes corresponding modifications to the source end and the host end for the usage of the mode. The host computer end is provided with a reference clock unit, and each signal source end is provided with an uplink clock receiving unit for receiving signals of the host computer end reference clock unit. After the data frame and the reference frame are synchronized through the approach mode, the control mode instruction generating unit at the host end sends an instruction of an accurate following mode to the mode adjusting unit at the information source end, the information source end follows the reference clock through the local clock, the self output clock signal and the received clock signal of the reference clock unit are calculated and compared, and the clock output of the controllable clock unit is adjusted. And the accurate following mode is executed at the information source end, so that the information source ends all work under one frequency, and the result of the previous approximation mode is consolidated. Of course, if the approach mode itself is synchronized and need not be performed, the exact follow mode may also be used, so the conditions for using this mode may be understood as: when the synchronization deviation value is not greater than the first threshold.
It should be noted that the precise following mode does not follow the reference clock signal "blindly" in contrast to the usual signal switched directly to the reference clock by an electronic switch. A big feature of the exact follow mode is that the frequency of the reference clock is a reference frequency, and the output frequency is actually a controllable clock unit. Since the reference clock signal from the host needs to be transmitted over a long distance to reach the source end, this process is affected by various kinds of emergency situations, resulting in an abrupt or accidental change of the reference clock signal. If each source terminal is directly switched to the reference clock signal, secondary asynchronization is caused. Therefore, the stability of the clock signal output by the signal source end is utilized to limit the output range of the reference clock signal. Generally, the frequency generated by the controllable clock unit is only within a preset range, and in any case, the frequency of the output of the controllable clock unit cannot exceed the preset range. And in the accurate following mode, the signal source end is used for calculating and comparing the self output clock signal with the received clock signal of the reference clock unit, and regulating the clock output of the controllable clock unit. Through calculation and comparison, if the received reference clock signal at the host end is not seriously abnormal, the clock output of the controllable clock unit is consistent with the reference clock; if the reference clock signal is seriously abnormal, the reference clock signal cannot completely follow the serious abnormal frequency signal of the reference clock due to the limitation of the preset range of the controllable clock unit, and only the maximum or minimum frequency of the controllable clock unit can be sent at most, so the generation of burst asynchronization can be reduced to a certain extent.
Although the synchronization deviation value is within the first threshold range, there is a slight deviation of the pixel level between different source data frames, and the clock source will have a slight deviation and a rebalancing process due to the influence of other objective factors such as temperature during the actual use process, but these two cases are only the deviation of the pixel level, so in order to achieve the best effect, the pixel level FIFO buffer unit can be properly arranged in the data frame synchronization processing unit.
In practical use, because a certain distance exists between the host end and the information source end, a period of time is required for sending the instruction of the accurate following mode sent by the host end to the information source end, and in the period of time, the information source end still works in an approaching mode, so that the instruction is probably overgreat and secondary asynchronization is caused. Specifically, as shown in fig. 3, synchronization has been achieved at time t1, when the command for the exact follow mode is sent, but the source side cannot receive a response until time t2, but still operates in the approach mode during the time t1 to t2, so that the end result is that the data frame is shifted from behind to ahead. If the correction is performed in the reverse approach mode, the delay problem of signal transmission may be "overleft" again, and the received data frame is changed from early to late, and the final result is that the source side always works in a fast or slow manner, but the synchronization of the reference frame and the received data frame cannot be realized.
In view of the above, in an embodiment of the present invention, a fine tuning mode is set, where the fine tuning mode is to use a positive or negative frequency offset to implement clock output by the controllable clock unit, so that the data frame generated by the data generation unit approaches the reference frame, i.e. the synchronization deviation value is reduced. When the mode is in the accurate following mode, if the synchronous deviation value is larger than the first threshold value, the control mode instruction generating unit sends an instruction of the fine tuning mode to the mode adjusting unit. Continuing with the example of fig. 3, at time t2, the source end starts to operate in the precise following mode, the host end finds that the synchronization deviation value is greater than the first threshold value at time t3, and sends the instruction of the fine tuning mode, the expression of fig. 3 is only convenient to understand, in practice, the time t3 is often before time t2, the source end receives the instruction and responds at time t4, synchronization is achieved at time t5, at this time, the host end sends the precise following mode instruction again, and the source end receives the instruction and responds at time t 6. At time t6, the synchronization deviation value is controlled to be within the first threshold, the precise following mode may be used all the time, but if the synchronization deviation value is not within the first threshold at time t6, the above cycle of the precise following mode and the fine tuning mode may be continued, so that the received data frame is finally synchronized in the oscillation. In addition, even in the exact follow mode, slight deviations may occur, which, when accumulated to a certain amount, exceed the first threshold range of the synchronization deviation value, and the fine tuning mode is suitably used to bring the synchronization deviation value back into the first threshold range again.
Preferably, a first frequency offset and a second frequency offset of the controllable clock unit are preset, and the first frequency offset is greater than the second frequency offset; in an approximation mode, a controllable clock unit realizes clock output by adopting positive or negative first frequency offset; in the fine tuning mode, the controllable clock unit uses a second frequency offset, positive or negative, to achieve the clock output. Generally, the approximation mode is to achieve synchronization quickly, so a large frequency offset is used for approximation, but the large frequency offset cannot achieve final synchronization due to communication delay, and the slow approximation with a small frequency offset can reduce the influence caused by communication delay, so the fine tuning mode uses a small frequency offset to approximate synchronization.
Preferably, the first frequency deviation is a maximum frequency deviation of the controllable clock unit within a preset range. Generally, the approach mode is to achieve synchronization quickly, so the maximum frequency offset of the controllable clock unit within a preset range can be used to achieve the purpose of high speed.
In actual use, there is a possibility that a signal of the reference clock cannot be transmitted to the uplink clock receiving unit of the source end due to a situation such as a broken transmission cable, and at this time, if the signal is in the accurate following mode, the source end is in a situation where no clock signal can follow, and no data frame is output. In view of the fact that this may occur, the invention in one embodiment provides a suitable modification of the source side to set a locking frequency within a preset range for the controllable clock unit and to increase the locking pattern. And the locking mode refers to that the controllable clock unit performs clock output at a locking frequency. The mode adjusting unit also detects whether the uplink clock receiving unit receives a reference clock signal, when the uplink clock receiving unit is in an accurate following mode, if the mode adjusting unit detects that the uplink clock receiving unit does not receive the reference clock signal, the mode instruction generating unit is controlled to send an instruction of a locking mode to the mode adjusting unit, and the controllable clock unit works at a locking frequency set in a preset range and continues to output data frames outwards.
In one embodiment, the number of source terminals of the present invention is at least 2. When only one source end is provided, the source end can be synchronized with the host end, when a plurality of source ends are provided, the plurality of source ends can be synchronized with the host end, and finally, synchronization among all the source ends is achieved.
In one embodiment, the reference frame synchronization generation unit determines a data frame of one of the source terminals as a reference frame. For the source terminal used for determining the reference frame, the data frame of the source terminal does not need to be synchronized, the synchronous work of one source terminal is reduced, and the system work is simpler.
In one embodiment, the reference frame synchronization generating unit generates the data frame itself, and determines the data frame generated by itself as the reference frame. Compared with the reference frame generation method of the previous embodiment, this embodiment has the advantage of avoiding that no reference frame is generated when the source terminal generating the reference frame is turned off or fails or the transmission line is in trouble.
Two methods for determining the reference frame are listed above, and those skilled in the art can determine the reference frame in other ways according to actual needs.
In one embodiment, the source end is a video source end, the data generation unit is a video generation unit, and the data frame is a video frame. As mentioned above, the video source is a camera. In practice, the same method can be used to implement data frames that regularly repeat, either at the audio source or at the combination of the audio source and the video source. Of course, those skilled in the art can also extend the present invention to other types of source terminals according to actual needs.
The host end of the invention controls the source end by adopting a command control mode, and the command of the host end is verified, so the command has higher effectiveness. In addition, the controllable clock unit presets the self-generated frequency within a certain range, so that the instruction beyond the range can be automatically ignored as an error instruction, and the effectiveness of the instruction is improved again.
Example two
Corresponding to the data frame synchronization apparatus in the first embodiment, the present invention further provides a data frame synchronization method, a flowchart of the method is shown in fig. 4, and the method includes the following steps:
s1: determining a reference frame;
s2: acquiring a data frame sent by a source end, and calculating a synchronization deviation value between the acquired data frame and a reference frame;
s3: sending a command of a control mode to the information source terminal according to the synchronization deviation value;
s4: the signal source end adjusts the frequency of a clock signal generated by a controllable clock unit of the signal source end according to the instruction of the control mode, so that a data frame generated by the signal source end approaches a reference frame, namely, the synchronization deviation value is reduced;
s5: and the source terminal generates a data frame according to the clock signal and transmits the data frame.
Through steps S1 and S2, a synchronization deviation value of each source terminal can be obtained, and it can be determined which source terminal needs to take a synchronization measure. Step S3 is to instruct the source terminal that needs to take the synchronization measure according to the synchronization deviation value. Of course, it can be set that, in any case, the command is sent to all the source terminals, but the command includes the option of not adjusting the synchronization. After the signal source receives the instruction, the clock signal of the signal source is adjusted according to the instruction, and the specific output content can refer to the first embodiment. When the clock signal of the source end is changed, the frequency of the data frame generation is also changed, and then the data frame is sent to the host end at another frequency.
In one embodiment, the control modes include: and the approximation mode is that the controllable clock unit at the source end adopts positive or negative frequency offset to realize clock output, so that the data frame generated at the source end approximates to the reference frame, namely the synchronization deviation value is reduced. Step S3 is shown in fig. 5, and further includes the following steps:
s31: presetting a first threshold value of a synchronization deviation value;
s32: and when the synchronization deviation value is larger than the first threshold value, sending an instruction of approaching a mode to the information source terminal.
As can be seen from the description of the first embodiment, in this case, step S3 is to change the "operating efficiency" of the source end to make the received data frame approach the reference frame, i.e. to make the synchronization deviation value smaller, so as to achieve the final synchronization. The method for realizing synchronization by changing the work efficiency can avoid unsmooth picture caused by frame dropping or frame inserting, can realize zero stock of data frames, does not need to use a storage element, and saves the cost.
In one embodiment, the data frame synchronization method of the present invention further includes: and transmitting the reference clock signal to the source terminal. The control mode further includes: and the accurate following mode is that the signal source end calculates and compares the feedback of the clock signal generated by the controllable clock unit of the signal source end with the received reference clock signal, and adjusts the frequency of the clock signal generated by the controllable clock unit according to the calculation and comparison result.
Step S3 further includes the steps of:
s33: and when the synchronization deviation value is not greater than the first threshold value, sending an instruction of an accurate following mode to the source terminal.
As shown in fig. 5, the determination of the first threshold includes two branches: when the synchronous deviation value is larger than a first threshold value, the host end sends an instruction of approaching a mode; and when the synchronization deviation value is not larger than the first threshold value, the source terminal executes an accurate following mode.
The accurate following mode is based on the adjustment of a reference clock signal at the host terminal to a self clock unit signal, so that the normal work of a signal source terminal under the reference clock can be ensured, and accidents in the signal transmission process can be avoided.
In one embodiment, the control mode further comprises: a fine tuning mode; the fine tuning mode is that a controllable clock unit at the source end adopts positive or negative frequency offset to realize clock output, so that a data frame generated at the source end approaches a reference frame, namely, a synchronization deviation value is reduced.
Step S3 further includes the steps of:
s34: when the information source terminal is in the accurate following mode, if the synchronization deviation value is larger than the first threshold value, an instruction of a fine tuning mode is sent to the information source terminal, and the information source terminal executes the fine tuning mode.
Preferably, the data frame synchronization method of the present invention further includes: presetting a first frequency offset and a second frequency offset of a controllable clock unit of a signal source end, wherein the first frequency offset is greater than the second frequency offset; in an approximation mode, a controllable clock unit realizes clock output by adopting positive or negative first frequency offset; in the fine tuning mode, the controllable clock unit uses a second frequency offset, positive or negative, to achieve the clock output.
Preferably, the first frequency deviation is a maximum frequency deviation of the controllable clock unit within a preset range.
In one embodiment, the control mode further comprises: a lock mode, in which the controllable clock unit at the source end performs stable clock output at the lock frequency, and step S3 further includes the following steps:
s35: when the signal source terminal is in the accurate following mode, if the signal source terminal is detected not to receive the reference clock signal, a command of the locking mode is sent to the signal source terminal, and the signal source terminal executes the locking mode.
The locking mode is complementary and perfect to the accurate following mode, and if the reference clock signal is not received, a locking frequency set in a preset range by the controllable clock unit is used as the clock signal to be output, so that the problem that the machine cannot work normally due to the fact that the reference clock signal does not exist is avoided.
In one embodiment, the number of source terminals is at least 2.
In one embodiment, in step S1, the host determines the self-generated data frame as the reference frame.
In one embodiment, the source end is a video source end, the data generation unit is a video generation unit, and the data frame is a video frame. In fact, besides the source terminal being a video source terminal, an audio source terminal or a combination of the audio source terminal and the video source terminal can also be implemented by using the same method. Of course, those skilled in the art can also extend the present invention to other types of source terminals according to actual needs.
EXAMPLE III
Corresponding to the data frame synchronization device in the first embodiment, the invention further provides a host end for data frame synchronization. This host computer end includes: a reference frame synchronization generating unit, a data frame synchronization processing unit and a control mode instruction generating unit;
the reference frame synchronization generating unit is used for determining a reference frame; the data frame synchronization processing unit is used for acquiring a data frame and calculating a synchronization deviation value between the received data frame and a reference frame; and the control mode instruction generating unit sends an instruction for adjusting the control mode of the source terminal frequency according to the synchronization deviation value.
In one embodiment, a first threshold value of the synchronization deviation value is preset; the control modes include: and (4) approaching a mode. And when the synchronization deviation value is larger than the first threshold value, controlling the mode instruction generating unit to send an instruction of an approaching mode. The approach mode is that the host end informs the source end to accelerate or decelerate the clock output frequency, so that the data frame sent by the source end approaches the reference frame.
In one embodiment, the host further comprises: a reference clock unit; the control mode further includes: the precise following mode.
The reference clock unit is used for generating and transmitting a reference clock signal.
The accurate following mode means that the host informs the signal source end to calculate and compare the feedback of the clock signal output by the host and a reference clock signal, and adjusts the clock output of the signal source end.
And when the synchronization deviation value is not greater than the first threshold value, controlling the mode instruction generating unit to send an instruction of an accurate following mode.
In one embodiment, the control mode further comprises: a fine tuning mode. And when the mobile terminal is in the accurate following mode, if the synchronization deviation value is greater than the first threshold value, controlling the mode instruction generating unit to send an instruction of a fine tuning mode. The fine tuning mode is that the host end informs the signal source end to adopt positive or negative frequency offset to accelerate or slow down the clock output frequency, so that the data frame sent by the signal source end approaches the reference frame, namely the synchronization deviation value is reduced.
In one embodiment, a first frequency offset and a second frequency offset are preset, and the first frequency offset is larger than the second frequency offset. In an approaching mode, a host end informs a signal source end to adopt a positive or negative first frequency offset to realize clock output; in the fine tuning mode, the host end informs the source end to adopt a positive or negative second frequency offset to realize clock output.
In one embodiment, the host side includes at least 2 interfaces to connect the source side.
In one embodiment, the reference frame synchronization generating unit generates the data frame itself, and determines the data frame generated by itself as the reference frame.
In one embodiment, the source end is a video source end, and the data frame is a video frame.
Example four
Corresponding to the data frame synchronization device in the first embodiment, the invention further provides a data frame synchronization source end. The source terminal includes: a mode adjustment unit, a controllable clock unit and a data generation unit.
The mode adjusting unit is used for receiving the instruction of the control mode and adjusting the frequency of the clock signal of the controllable clock unit according to the instruction of the control mode so as to enable the data frame generated by the data generating unit to approach the reference frame, namely, the synchronization deviation value is reduced; the controllable clock unit can generate clock signals with various frequencies within a preset range; the data generating unit generates a data frame according to the clock signal of the controllable clock unit and transmits the data frame.
In one embodiment, the control modes include: and the approximation mode is that the controllable clock unit adopts positive or negative frequency deviation to realize clock output, so that the data frame generated by the data generation unit approximates to the reference frame, namely the synchronization deviation value is reduced.
In one embodiment, the source side further comprises: the device comprises an uplink clock receiving unit and a comparison filtering device; the uplink clock receiving unit is used for receiving a reference clock signal; the comparison filtering device is used for calculating and comparing the feedback of the clock signal output by the controllable clock unit with the received reference clock signal.
The control mode further includes: a precise following mode; the accurate following mode refers to the comparison filtering device adjusting the clock signal generated by the controllable clock unit according to the calculation comparison result.
In one embodiment, the control mode further comprises: a fine tuning mode; the fine tuning mode means that the controllable clock unit adopts positive or negative frequency deviation to realize clock output, so that the data frame generated by the data generation unit approaches the reference frame, namely the synchronization deviation value is reduced.
In one embodiment, a first frequency offset and a second frequency offset of a controllable clock unit are preset, wherein the first frequency offset is greater than the second frequency offset; in an approximation mode, a controllable clock unit realizes clock output by adopting positive or negative first frequency offset; in the fine tuning mode, the controllable clock unit uses a second frequency offset, positive or negative, to achieve the clock output.
In one embodiment, the first frequency offset is a maximum frequency offset of the controllable clock unit within a preset range.
In one embodiment, the controllable clock unit sets a locking frequency within a preset range; the control mode further includes: a locking mode, which means that the controllable clock unit performs a clock output at the locking frequency. The mode adjusting unit also detects whether the uplink clock receiving unit receives the reference clock signal, and when the uplink clock receiving unit is in the accurate following mode, if the mode adjusting unit detects that the uplink clock receiving unit does not receive the reference clock signal, the mode adjusting unit executes the locking mode.
In one embodiment, the source end is a video source end, the data generation unit is a video generation unit, and the data frame is a video frame.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (31)
1. A data frame synchronization apparatus, comprising: a host terminal and a plurality of message source terminals;
the host side includes:
a reference frame synchronization generating unit for determining a reference frame;
the data frame synchronization processing unit is used for receiving the data frame from the source end and calculating a synchronization deviation value between the received data frame and the reference frame;
the control mode instruction generating unit is used for sending an instruction of a control mode to the information source terminal according to the synchronization deviation value;
the source terminal includes:
the controllable clock unit is used for generating clock signals with various frequencies within a preset range;
the data generating unit is used for generating a data frame according to the clock signal of the controllable clock unit and sending the data frame to the data frame synchronous processing unit;
the mode adjusting unit is used for adjusting the frequency of the clock signal of the controllable clock unit according to the control mode command sent by the control mode command generating unit so as to reduce the synchronization deviation value;
the control modes include: an approximation mode;
the approximation mode means that the controllable clock unit outputs a clock by adopting a positive or negative preset first frequency offset, so that the synchronization deviation value is reduced;
and when the synchronization deviation value is larger than a first threshold value, the control mode instruction generating unit sends the instruction of the approach mode to the mode adjusting unit.
2. The apparatus for synchronizing data frames according to claim 1, wherein the host further comprises: a reference clock unit for generating a reference clock signal;
the source terminal further includes: the uplink clock receiving unit is used for receiving the reference clock signal generated by the reference clock unit, and the comparison filtering device is used for calculating and comparing the feedback of the clock signal output by the controllable clock unit with the received reference clock signal;
the control mode further includes: the accurate following mode refers to the fact that the comparison filtering device adjusts the clock signals generated by the controllable clock unit according to the calculation comparison result;
when the synchronization deviation value is not greater than the first threshold value, the control mode instruction generating unit sends the instruction of the precise following mode to the mode adjusting unit.
3. The apparatus for data frame synchronization according to claim 2, wherein the control mode further comprises: a fine tuning mode;
the fine tuning mode is that the controllable clock unit adopts a positive or negative preset second frequency offset to realize clock output, so that the synchronization deviation value is reduced;
when the mode is in the accurate following mode, if the synchronization deviation value is larger than the first threshold value, the control mode instruction generating unit sends the instruction of the fine tuning mode to the mode adjusting unit.
4. The apparatus of claim 3, wherein the first frequency offset is greater than the second frequency offset.
5. The apparatus of claim 4, wherein the first frequency offset is a maximum frequency offset of the controllable clock unit within a predetermined range.
6. The data frame synchronizing device according to any one of claims 2 to 5, wherein the controllable clock unit sets a locking frequency within a preset range;
the control mode further includes: a locking mode, wherein the locking mode refers to that the controllable clock unit performs clock output at the locking frequency;
the mode adjusting unit also detects whether the uplink clock receiving unit receives the reference clock signal;
when the mobile terminal is in the accurate following mode, if the mode adjusting unit detects that the reference clock signal is not received by the uplink clock receiving unit, the control mode instruction generating unit sends the instruction of the locking mode to the mode adjusting unit.
7. The data frame synchronization device according to any of claims 1-5, wherein the number of source terminals is at least 2.
8. The data frame synchronization device according to any one of claims 1 to 5, wherein the reference frame synchronization generation unit generates a data frame itself, and determines the data frame generated by itself as the reference frame.
9. The apparatus according to any of claims 1-5, wherein the source end is a video source end, the data generation unit is a video generation unit, and the data frame is a video frame.
10. A host end of data frame synchronization, comprising:
a reference frame synchronization generating unit for determining a reference frame;
the data frame synchronization processing unit is used for acquiring a data frame and calculating a synchronization deviation value between the acquired data frame and the reference frame;
the control mode instruction generating unit is used for sending an instruction of a control mode according to the synchronization deviation value;
the control modes include: an approximation mode;
when the synchronization deviation value is larger than a first threshold value, the control mode instruction generating unit sends an instruction of the approach mode;
the approach mode is that the host end informs the source end of adopting a positive or negative preset first frequency offset to accelerate or slow down the clock output frequency, so that the synchronization deviation value is reduced.
11. The host end of claim 10, wherein the host end further comprises: the reference clock unit is used for generating and transmitting a reference clock signal;
the control mode further includes: a precise following mode;
when the synchronization deviation value is not larger than the first threshold value, the control mode instruction generating unit sends an instruction of the precise following mode;
the accurate following mode means that the host end informs the signal source end to calculate and compare the feedback of the clock signal output by the host end with the reference clock signal, and adjusts the clock output of the signal source end.
12. The host end of claim 11, wherein the control pattern further comprises: a fine tuning mode;
when the control mode command generating unit is in an accurate following mode, if the synchronization deviation value is larger than the first threshold value, the control mode command generating unit sends a command of the fine tuning mode;
the fine tuning mode is that the host end informs the source end to adopt a positive or negative preset second frequency offset to accelerate or slow down the clock output frequency, so that the synchronization deviation value is reduced.
13. The host-side of claim 12, wherein the first frequency offset is greater than the second frequency offset.
14. A host side for data frame synchronization according to any of claims 10-13, wherein said host side comprises at least 2 interfaces to a source side.
15. The host side of data frame synchronization according to any one of claims 10 to 13, wherein the reference frame synchronization generating unit generates a data frame by itself and determines the data frame generated by itself as the reference frame.
16. A source end for data frame synchronization, comprising:
the controllable clock unit is used for generating clock signals with various frequencies within a preset range;
the data generating unit is used for generating a data frame according to the clock signal of the controllable clock unit and transmitting the data frame;
the mode adjusting unit is used for receiving an instruction of a control mode and adjusting the frequency of a clock signal of the controllable clock unit according to the instruction of the control mode;
the control modes include: an approximation mode;
the approximation mode means that the controllable clock unit outputs a clock by using a positive or negative preset first frequency offset.
17. The source end of claim 16, wherein the source end further comprises:
an uplink clock receiving unit for receiving a reference clock signal;
the comparison filtering device is used for calculating and comparing the feedback of the clock signal output by the controllable clock unit with the received reference clock signal;
the control mode further includes: and the accurate following mode refers to the mode that the comparison filtering device adjusts the clock signal generated by the controllable clock unit according to the calculation comparison result.
18. The source side of claim 17, wherein the control mode further comprises: and a fine tuning mode, wherein the fine tuning mode is that the controllable clock unit realizes clock output by adopting a positive or negative preset second frequency offset.
19. The source end of claim 18, wherein the first frequency offset is greater than the second frequency offset.
20. The source-side of data frame synchronization of claim 19, wherein the first frequency offset is a maximum frequency offset of the controllable clock unit within a predetermined range.
21. A source terminal for data frame synchronization according to any of claims 17-20, wherein said controllable clock unit sets a locking frequency within a predetermined range;
the control mode further includes: a locking mode, wherein the locking mode refers to that the controllable clock unit performs clock output at the locking frequency;
the mode adjusting unit also detects whether the uplink clock receiving unit receives the reference clock signal;
when the mobile terminal is in the accurate following mode, if the mode adjusting unit detects that the reference clock signal is not received by the uplink clock receiving unit, the mode adjusting unit executes the locking mode.
22. The source end of any of claims 16-20, wherein the data generating unit is a video generating unit, and the data frame is a video frame.
23. A data frame synchronization method, characterized in that the data frame synchronization method comprises the steps of:
s1: determining a reference frame;
s2: acquiring a data frame sent by a source end, and calculating a synchronization deviation value between the acquired data frame and the reference frame;
s3: sending a control mode instruction to the information source terminal according to the synchronization deviation value;
s4: the source end adjusts the frequency of a clock signal generated by a controllable clock unit of the source end according to the instruction of the control mode, so that the synchronization deviation value is reduced;
s5: the signal source end generates a data frame according to the clock signal and sends the data frame;
the control modes include: an approximation mode, wherein the approximation mode is that a controllable clock unit at the signal source end adopts a positive or negative preset first frequency offset to realize clock output, so that the synchronization deviation value is reduced;
step S3 includes the following steps:
s31: presetting a first threshold value of a synchronization deviation value;
s32: and when the synchronization deviation value is larger than the first threshold value, sending an instruction of the approach mode to the information source terminal.
24. The data frame synchronization method according to claim 23, further comprising the steps of: sending a reference clock signal to the information source terminal;
the control mode further includes: the accurate following mode is that the signal source end calculates and compares the feedback of the clock signal generated by the controllable clock unit of the signal source end with the received reference clock signal, and adjusts the frequency of the clock signal generated by the controllable clock unit according to the calculation and comparison result;
step S3 further includes the steps of:
s33: and when the synchronization deviation value is not greater than the first threshold value, sending an instruction of the accurate following mode to the information source terminal.
25. The method of claim 24, wherein the control mode further comprises: a fine tuning mode, wherein the fine tuning mode is that a controllable clock unit at the signal source end adopts a positive or negative preset second frequency offset to realize clock output, so that the synchronization deviation value is reduced;
step S3 further includes the steps of:
s34: and when the information source terminal is in an accurate following mode, if the synchronization deviation value is greater than the first threshold value, sending a fine tuning mode instruction to the information source terminal.
26. The method of data frame synchronization of claim 25, wherein the first frequency offset is greater than the second frequency offset.
27. The method of claim 26, wherein the first frequency offset is a maximum frequency offset of the controllable clock unit within a predetermined range.
28. The data frame synchronization method according to any one of claims 24 to 27, further comprising: the controllable clock unit sets a locking frequency within a preset range;
the control mode further includes: the locking mode refers to that a controllable clock unit of the signal source end carries out clock output under the locking frequency;
step S3 further includes the steps of:
s35: and when the signal source terminal is in the accurate following mode, if the signal source terminal is detected not to receive the reference clock signal, sending a command of the locking mode to the signal source terminal.
29. The method according to any of claims 23-27, wherein the number of source terminals is at least 2.
30. The data frame synchronization method according to any one of claims 23 to 27, wherein in step S1, the self-generated data frame is determined as the reference frame.
31. The method of any of claims 23-27, wherein the source end is a video source end and the data frame is a video frame.
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