CN110932363A - Balanced drive circuit and electronic equipment - Google Patents
Balanced drive circuit and electronic equipment Download PDFInfo
- Publication number
- CN110932363A CN110932363A CN201911363505.3A CN201911363505A CN110932363A CN 110932363 A CN110932363 A CN 110932363A CN 201911363505 A CN201911363505 A CN 201911363505A CN 110932363 A CN110932363 A CN 110932363A
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- electrically connected
- subunit
- equalizing
- driving circuit
- battery
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
- H02J7/0014—Circuits for equalisation of charge between batteries
- H02J7/0016—Circuits for equalisation of charge between batteries using shunting, discharge or bypass circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
- H02J7/0014—Circuits for equalisation of charge between batteries
- H02J7/0019—Circuits for equalisation of charge between batteries using switched or multiplexed charge circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The embodiment of the invention discloses an equalization driving circuit and electronic equipment, wherein the equalization driving circuit comprises a processor and a plurality of equalization driving circuit units; each balance driving circuit unit comprises a capacitor, a balance circuit subunit and a driving circuit subunit; the first end of each capacitor is electrically connected with one output end of the processor, and the second end of each capacitor is electrically connected with the control end of the corresponding equalizing circuit subunit; the second end of each capacitor is electrically connected with the input terminal of the corresponding drive circuit subunit, and the output terminal of the first drive circuit subunit is electrically connected with the grounding end of the processor to form a closed loop; and the output terminal of the Nth drive circuit subunit is electrically connected with the last equalization drive circuit unit so as to be indirectly electrically connected with the grounding terminal of the processor to form a closed loop. The embodiment of the invention simplifies the balance driving circuit, realizes the balance of all batteries, reduces the cost and improves the reliability.
Description
Technical Field
The embodiment of the invention relates to the technical field of circuits, in particular to an equalization driving circuit and electronic equipment.
Background
With the progress of science and technology, the lithium batteries are more and more widely applied to equipment in various industries, and 6 or less lithium batteries are applied to the occasions of series connection of electric tools, the Internet of things, unmanned planes and the like, so that the service life of a single battery needs to be prolonged in a balanced manner.
In the serial application of 6 or less lithium batteries, in order to reduce the power consumption and the cost of products, a non-isolated power supply scheme is adopted, namely, the grounding end of a Micro Control Unit (MCU) is grounded with the negative electrode of the 1 st battery; however, the MCU drives the battery to passively balance the MOS transistor due to non-isolation common ground, the MCU cannot directly conduct the 2 nd to 6 th balancing MOS transistors and can only be controlled by adopting an isolation optocoupler mode, however, the 1 st to 6 th circuits can be simultaneously conducted by adopting the isolation optocoupler mode, the 2 nd to 6 th circuit balance cannot be realized, and the circuit is complex, high in cost and low in reliability.
Disclosure of Invention
The embodiment of the invention provides an equalizing driving circuit and electronic equipment, which can reduce the process fault tolerance and ensure the working characteristics of devices.
In a first aspect, an embodiment of the present invention provides an equalization driving circuit, including:
the system comprises a processor and a plurality of balance driving circuit units;
each equalization driving circuit unit comprises a capacitor, an equalization circuit subunit and a driving circuit subunit; the first end of each capacitor is electrically connected with one output end of the processor, and the second end of each capacitor is electrically connected with the control end of the corresponding equalizing circuit subunit;
the second end of each capacitor is electrically connected with the input terminal of the corresponding drive circuit subunit, and the output terminal of the first drive circuit subunit is electrically connected with the grounding terminal of the processor to form a closed loop; and the output sub-terminal of the Nth driving circuit sub-unit is electrically connected with the last equalization driving circuit unit so as to be indirectly electrically connected with the grounding terminal of the processor to form a closed loop.
Optionally, each of the equalization circuit subunits includes:
a switch tube and a battery;
the second end of each capacitor is electrically connected with the control end of the corresponding switch tube, the first end of each switch tube is electrically connected with the positive electrode of the battery, the second end of each switch tube is electrically connected with the negative electrode of the battery, and the negative electrode of the battery of the first equalization circuit subunit is electrically connected with the grounding end of the processor; and the negative electrode of the battery of the Nth equalizing circuit subunit is electrically connected with the positive electrode of the battery of the last equalizing circuit subunit.
Optionally, each of the balancing circuit subunits further includes a first resistor, a first end of the first resistor is electrically connected to the positive electrode of the corresponding battery, and a second end of the first resistor is electrically connected to the first end of the corresponding switching tube.
Optionally, the switch tube is an N-type field effect tube.
Optionally, each of the driving circuit subunits includes a second resistor, a first end of the second resistor is electrically connected to a second end of the capacitor corresponding thereto, and a second end of the second resistor is electrically connected to a second end of the switching tube corresponding thereto and a negative electrode of the battery corresponding thereto.
Optionally, the second end of the second resistor of the nth driving circuit subunit is further electrically connected to the battery anode of the previous equalizing circuit subunit and the first end of the first resistor of the previous equalizing circuit subunit.
Optionally, the signal output by the output end of the processor is a PWM square wave.
In a second aspect, an embodiment of the present invention provides an electronic device, including the equalizing driving circuit described in any of the first aspects.
The embodiment of the invention provides an equalization driving circuit and electronic equipment, wherein the equalization driving circuit comprises a processor and a plurality of equalization driving circuit units; each balance driving circuit unit comprises a capacitor, a balance circuit subunit and a driving circuit subunit; the first end of each capacitor is electrically connected with one output end of the processor, and the second end of each capacitor is electrically connected with the control end of the corresponding equalizing circuit subunit; the second end of each capacitor is electrically connected with the input terminal of the corresponding drive circuit subunit, and the output terminal of the first drive circuit subunit is electrically connected with the grounding end of the processor to form a closed loop; and the output terminal of the Nth drive circuit subunit is electrically connected with the last equalization drive circuit unit so as to be indirectly electrically connected with the grounding terminal of the processor to form a closed loop. The balance driving circuit is simplified, the balance of all batteries is realized, the cost is reduced, and the reliability is improved.
Drawings
Fig. 1 is a schematic diagram of an equalizing driving circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another equalizing driving circuit according to the embodiment of the present invention;
FIG. 3 is a schematic diagram of another equalizing driving circuit according to the embodiment of the present invention;
FIG. 4 is a schematic diagram of another equalizing driving circuit according to the embodiment of the present invention;
FIG. 5 is a waveform diagram of a different position provided by an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
An embodiment of the present invention provides an equalization driving circuit, and fig. 1 is a schematic diagram of an equalization driving circuit provided in an embodiment of the present invention, and referring to fig. 1, the equalization driving circuit includes:
a processor 10, a plurality of equalization driving circuit units 20;
each equalization driving circuit unit comprises a capacitor C, an equalization circuit subunit 21 and a driving circuit subunit 22; the first end of each capacitor C is electrically connected with one output end of the processor, and the second end of each capacitor C is electrically connected with the control end of the corresponding equalization circuit subunit 21;
a second end of each capacitor C is electrically connected with an input terminal of the corresponding driving circuit subunit 22, and an output terminal of the first driving circuit subunit 20 is electrically connected with a ground terminal B of the processor to form a closed loop; the output terminal of the nth driving circuit subunit 20 is electrically connected to the last equalizing driving circuit unit 20 to be indirectly electrically connected to the ground terminal of the processor 10 to form a closed loop.
Specifically, the equalization drive circuit includes: a processor 10, a plurality of equalization driving circuit units 20; the processor 10 is electrically connected with the plurality of equalization driving circuit units 20, and the signals output by the processor 10 control the on and off of the plurality of equalization driving circuit units 20, so that the equalization of the equalization driving circuit units 20 can be realized when the equalization driving circuit units 20 are turned on; wherein, each equalization driving circuit unit 20 comprises a capacitor C, an equalization circuit subunit 21 and a driving circuit subunit 22; a first terminal of each capacitor C is electrically connected to AN output terminal of the processor 10, for example, the capacitor C of the first equalizing drive circuit unit 20 is electrically connected to a first output terminal a1 of the processor, the capacitor C of the second equalizing drive circuit unit 20 is electrically connected to a second output terminal a2 of the processor, and the capacitor C of the nth equalizing drive circuit unit 20 is electrically connected to AN nth output terminal AN of the processor. The second end of each capacitor C is electrically connected with the control end of the corresponding equalization circuit subunit 21, the processor 10 outputs a signal through the output end, the signal is transmitted to the control end of the equalization circuit subunit 21 after passing through the capacitor C, and the on/off of the equalization circuit subunit 21 can be switched according to the signal; a second end of each capacitor C is electrically connected to an input terminal of the corresponding driving circuit subunit 22, wherein an output terminal of the first driving circuit subunit 22 is electrically connected to a ground terminal B of the processor 10 to form a closed loop; the output terminal of the nth driving circuit subunit 22 is electrically connected to the previous equalizing driving circuit unit 20 to be indirectly electrically connected to the ground terminal B of the processor 10 to form a closed loop, so as to turn on all the driving circuit subunits. The capacitor C can delay the signal transmission to the driving circuit subunit 22 and the equalizing circuit subunit 21, so as to control the time for conducting each equalizing circuit subunit 21, thereby realizing the effect of equalizing all the equalizing circuit subunits 21 simultaneously, simplifying the equalizing driving circuit, reducing the cost and improving the reliability.
An embodiment of the present invention provides an equalization driving circuit, including: a processor 10, a plurality of equalization driving circuit units 20; each equalization driving circuit unit comprises a capacitor C, an equalization circuit subunit 21 and a driving circuit subunit 21; a first end of each capacitor C is electrically connected with one output end of the processor 10, and a second end of each capacitor C is electrically connected with a control end of the corresponding equalization circuit subunit 21; a second end of each capacitor C is electrically connected to an input terminal of the corresponding driving circuit subunit 22, and an output terminal of the first driving circuit subunit 22 is electrically connected to a ground terminal B of the processor 10 to form a closed loop; the output terminal of the nth driving circuit subunit 22 is electrically connected to the previous equalizing driving circuit unit 20 to be indirectly electrically connected to the ground terminal B of the processor 10 to form a closed loop. The embodiment of the invention can delay the signal transmission to the driving circuit subunit 22 and the equalizing circuit subunit 21, thereby controlling the time for conducting each equalizing driving circuit unit 20, realizing the effect of equalizing all the equalizing circuit subunits 21 simultaneously, simplifying the equalizing driving circuit, reducing the cost and improving the reliability.
Optionally, fig. 2 is a schematic diagram of another equalizing driving circuit provided in an embodiment of the present invention, and referring to fig. 2, each of the equalizing circuit subunits includes:
a switch tube Q and a battery U;
the second end of each capacitor C is electrically connected with the control end of the corresponding switch tube Q, the first end of the switch tube Q is electrically connected with the positive electrode of the battery U, the second end of the switch tube Q is electrically connected with the negative electrode of the battery U, and the negative electrode of the battery U of the first equalization circuit subunit 21 is electrically connected with the grounding end B of the processor 10; the negative pole of the battery U of the nth equalizing circuit subunit 21 is electrically connected with the positive pole of the battery U of the last equalizing circuit subunit 21.
Specifically, the second end of each capacitor C is electrically connected to the control end of the corresponding switch tube Q, that is, the control end of the switch tube Q is the control end of the equalization circuit subunit 21, and the switch tube Q switches its own on state and off state according to the signal output by the processor 10, thereby implementing the on and off of the equalization circuit subunit 21; the first end of the switch tube Q is electrically connected with the positive pole of the battery U, the second end of the switch tube Q is electrically connected with the negative pole of the battery U, and when the switch tube Q is switched on, the circuit of the equalization circuit subunit 21 is switched on to form backflow.
Optionally, fig. 3 is a schematic diagram of another equalizing driving circuit according to an embodiment of the present invention, and referring to fig. 3, each equalizing circuit subunit 21 further includes a first resistor R1, a first end of the first resistor R1 is electrically connected to the positive electrode of the battery U corresponding thereto, and a second end of the first resistor R1 is electrically connected to the first end of the switching tube Q corresponding thereto.
Specifically, each equalization circuit subunit 21 further includes a first resistor R1, a first end of the first resistor R1 is electrically connected to the positive electrode of the corresponding battery U, a second end of the first resistor R1 is electrically connected to the first end of the corresponding switch tube Q, and if the switch tube Q is turned on, the first resistor R1 is connected in parallel to the two ends of the battery U; illustratively, when the voltage of the battery U is too high, the processor 10 outputs a signal for turning on the switch Q to turn on the switch Q, and the current is shunted through the first resistor R1, so that the charging current of the battery U with high voltage is small, and the voltage of the battery U is equalized.
Optionally, referring to fig. 3, the switching transistor Q is an N-type field effect transistor.
Specifically, the switching tube Q is an N-type field effect transistor, and when the gate of the N-type field effect transistor receives a high level, the source and the drain of the N-type field effect transistor are turned on, so that the equalization circuit subunit 21 is turned on, and the battery voltage is equalized.
Optionally, fig. 4 is a schematic diagram of another equalizing driving circuit according to an embodiment of the present invention, and referring to fig. 4, each driving circuit subunit 22 includes a second resistor R2, a first end of the second resistor R2 is electrically connected to a second end of the capacitor C corresponding thereto, and a second end of the second resistor R2 is electrically connected to a second end of the corresponding switching tube Q and a negative electrode of the corresponding battery U.
Specifically, each driving circuit subunit 22 includes a second resistor R2, a first end of the second resistor R2 is electrically connected to a second end of the capacitor C corresponding thereto, and a second end of the second resistor R2 is electrically connected to a second end of the switching tube Q corresponding thereto and a negative electrode of the battery U corresponding thereto; the second resistor R2 is configured to achieve effective power-off of the switching transistor Q, for example, if the output terminal of the processor 10 suddenly stops outputting a high level to the gate of the N-type fet, a certain residual voltage exists between the gate and the drain of the N-type fet, and the N-type fet cannot be normally turned off in time, and by setting the second resistor R2, a certain residual voltage exists between the gate and the drain of the N-type fet is consumed, so as to achieve effective power-off of the N-type fet.
The negative terminal of the battery U in the first driving circuit subunit 22 is electrically connected to the ground terminal of the processor 10, that is, the second terminal of the second resistor R2 in the first driving circuit subunit 22 is electrically connected to the ground terminal of the processor 10.
Alternatively, referring to fig. 4, the second end of the second resistor R2 of the nth driving circuit subunit 22 is further electrically connected to the positive electrode of the battery U of the previous equalizing circuit subunit 21 and the first end of the first resistor R1 of the previous equalizing circuit subunit 21.
Specifically, the second end of the second resistor R2 of the nth driving circuit subunit 22 is further electrically connected to the positive electrode of the battery U of the previous equalizing circuit subunit 21 and the first end of the first resistor R1 of the previous equalizing circuit subunit 21; the second end of the second resistor R2 of the nth driving circuit subunit 21 is electrically connected to the positive electrode of the battery U of the previous equalizing circuit subunit 21, that is, the second end of the second resistor R2 of the nth driving circuit subunit 22 passes through the battery U of the nth-1 equalizing circuit subunit 21 to the negative electrode of the first equalizing circuit subunit battery U, and then the negative electrode of the battery U of the first equalizing circuit subunit 21 is electrically connected to the ground terminal B of the processor 10, thereby implementing conduction of the nth driving circuit subunit 22.
Optionally, the signal output by the output end of the processor is a PWM square wave.
For example, fig. 5 is a waveform diagram of different positions according to an embodiment of the present invention, referring to fig. 5, after the output of the processor 10 outputs the PWM square wave, the PWM square wave signal is delayed when being transmitted to the capacitor C, the PWM square wave signal is transmitted to the second resistor R2 later than the PWM square wave signal output by the output of the processor 10 through the waveform diagram inconsistency of different positions, and the PWM square wave signal is transmitted to the first resistor R1 later than the PWM square wave signal of the second resistor R2. After the driving circuit subunit 22 is turned on, the balancing circuit subunit 21 is turned on, so as to achieve the balancing effect of the balancing circuit subunit 21 on the battery U.
An embodiment of the present invention further provides an electronic device, which includes the equalizing driving circuit according to any of the embodiments, and has the same technical effects as the embodiments, and details are not repeated here.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (8)
1. An equalization driver circuit, comprising:
the system comprises a processor and a plurality of balance driving circuit units;
each equalization driving circuit unit comprises a capacitor, an equalization circuit subunit and a driving circuit subunit; the first end of each capacitor is electrically connected with one output end of the processor, and the second end of each capacitor is electrically connected with the control end of the corresponding equalizing circuit subunit;
the second end of each capacitor is electrically connected with the input terminal of the corresponding drive circuit subunit, and the output terminal of the first drive circuit subunit is electrically connected with the grounding terminal of the processor to form a closed loop; and the output sub-terminal of the Nth driving circuit sub-unit is electrically connected with the last equalization driving circuit unit so as to be indirectly electrically connected with the grounding terminal of the processor to form a closed loop.
2. The equalizing drive circuit of claim 1, wherein each equalizing circuit subunit comprises:
a switch tube and a battery;
the second end of each capacitor is electrically connected with the control end of the corresponding switch tube, the first end of each switch tube is electrically connected with the positive electrode of the battery, the second end of each switch tube is electrically connected with the negative electrode of the battery, and the negative electrode of the battery of the first equalization circuit subunit is electrically connected with the grounding end of the processor; and the negative electrode of the battery of the Nth equalizing circuit subunit is electrically connected with the positive electrode of the battery of the last equalizing circuit subunit.
3. The equalizing drive circuit according to claim 1, wherein each equalizing circuit subunit further comprises a first resistor, a first end of the first resistor is electrically connected to the positive electrode of the battery corresponding thereto, and a second end of the first resistor is electrically connected to the first end of the switching tube corresponding thereto.
4. The equalizing drive circuit of claim 3, wherein said switching tubes are N-type field effect transistors.
5. The equalizing drive circuit according to claim 1 or 2, wherein each of the drive circuit subunits comprises a second resistor, a first end of the second resistor is electrically connected to a second end of the capacitor corresponding thereto, and a second end of the second resistor is electrically connected to a second end of the switch tube corresponding thereto and a negative electrode of the battery corresponding thereto.
6. The equalizing drive circuit according to claim 3 or 5, wherein the second end of the second resistor of the nth driving circuit subunit is further electrically connected to the positive electrode of the battery of the last equalizing circuit subunit and the first end of the first resistor of the last equalizing circuit subunit.
7. The equalizing drive circuit of claim 1, wherein the signal output by the processor output is a PWM square wave.
8. An electronic device comprising the equalizing drive circuit according to any one of claims 1 to 7.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911363505.3A CN110932363A (en) | 2019-12-26 | 2019-12-26 | Balanced drive circuit and electronic equipment |
| PCT/CN2020/091104 WO2021128715A1 (en) | 2019-12-26 | 2020-05-19 | Equalization drive circuit and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911363505.3A CN110932363A (en) | 2019-12-26 | 2019-12-26 | Balanced drive circuit and electronic equipment |
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| Publication Number | Publication Date |
|---|---|
| CN110932363A true CN110932363A (en) | 2020-03-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911363505.3A Pending CN110932363A (en) | 2019-12-26 | 2019-12-26 | Balanced drive circuit and electronic equipment |
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| Country | Link |
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| CN (1) | CN110932363A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021128715A1 (en) * | 2019-12-26 | 2021-07-01 | 上海派能能源科技股份有限公司 | Equalization drive circuit and electronic device |
| WO2021244265A1 (en) * | 2020-06-01 | 2021-12-09 | 青岛安捷能源科技有限公司 | Cell balancing device based on capacitor network, cascadable balancing battery pack, and control method thereof |
-
2019
- 2019-12-26 CN CN201911363505.3A patent/CN110932363A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021128715A1 (en) * | 2019-12-26 | 2021-07-01 | 上海派能能源科技股份有限公司 | Equalization drive circuit and electronic device |
| WO2021244265A1 (en) * | 2020-06-01 | 2021-12-09 | 青岛安捷能源科技有限公司 | Cell balancing device based on capacitor network, cascadable balancing battery pack, and control method thereof |
| US11728662B2 (en) | 2020-06-01 | 2023-08-15 | Qingdao Anjie Energy Technology Co. Ltd. | Cell balancing device based on capacitor network, cascadable balanced battery pack and control method thereof |
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