CN110931370A

CN110931370A - Method for forming chip packaging structure

Info

Publication number: CN110931370A
Application number: CN201910894180.5A
Authority: CN
Inventors: 郑心圃; 翁得期; 林柏尧; 游明志; 蔡柏豪; 庄博尧
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-09-20
Filing date: 2019-09-20
Publication date: 2020-03-27

Abstract

The embodiment of the invention provides a method for forming a chip packaging structure, which comprises the steps of forming a conductive column on a redistribution structure; bonding the wafer to the redistribution structure; forming a mold seal layer over the redistribution structure, wherein the mold seal layer surrounds the conductive posts and the die, and the conductive posts pass through the mold seal layer; forming a cover layer on the mold sealing layer and the conductive posts, wherein the cover layer has through holes exposing the conductive posts and comprises fibers; and forming a conductive via structure in the via hole, wherein the conductive via structure is connected to the conductive pillar.

Description

Method for forming chip packaging structure

Technical Field

Embodiments of the present invention relate to a method for forming a semiconductor device, and more particularly, to a method for forming a chip package structure.

Background

Semiconductor devices are used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the material layers using photolithography and etching processes to form circuit elements and features thereon.

Many integrated circuits are typically fabricated on semiconductor wafers. The semiconductor wafer may be divided into dies. The die may be packaged and various techniques for packaging have been developed.

Disclosure of Invention

The embodiment of the invention comprises a method for forming a chip packaging structure, which comprises the steps of forming a conductive column on a redistribution structure; bonding the wafer to the redistribution structure; forming a mold seal layer over the redistribution structure, wherein the mold seal layer surrounds the conductive posts and the die, and the conductive posts pass through the mold seal layer; forming a cover layer on the mold sealing layer and the conductive posts, wherein the cover layer has through holes exposing the conductive posts and comprises fibers; and forming a conductive via structure in the via hole, wherein the conductive via structure is connected to the conductive pillar.

Drawings

The embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are merely illustrative examples. In fact, the dimensions of the elements may be exaggerated or minimized to clearly illustrate the technical features of the embodiments of the present invention.

FIGS. 1A-1G are cross-sectional views illustrating various stages in a process for forming a wafer package structure, according to some embodiments.

FIG. 2 is a cross-sectional view illustrating a wafer package structure according to some embodiments.

FIGS. 3A-3H are cross-sectional views illustrating various stages in a process for forming a wafer package structure, in accordance with some embodiments.

FIG. 4 is a cross-sectional view illustrating a wafer package structure according to some embodiments.

FIGS. 5A-5H are cross-sectional views illustrating various stages in a process for forming a wafer package structure, in accordance with some embodiments.

FIG. 6 is a cross-sectional view illustrating a wafer package structure according to some embodiments.

Description of reference numerals:

110 to substrate

111 core layer

111a, 111 b-surface

112a, 112 b-conductive pad layer

113-conductive via structure

114a, 114b, 114c, 114d insulating layer

115 to wiring layer

116-Wiring layer

116a, 116 b-conductive pad layer

117 wiring layers

118-wiring layer

118 a-conductive pad layer

119a, 119 b-surface

119 c-side wall

120-conductive bump

130A, 130B, 130C, 130D, 130E, 130F-wafer

131 to semiconductor substrate

131 a-front surface

131b rear surface

132 dielectric layer

133-conductive cushion layer

134 to inner connection layer

135-conductive structure

135a to the top surface

136 to the top surface

140 to conductive layer

150-primer layer

160-carrier substrate

170-redistribution structure

171-insulating layer

171 a-through hole

172-conductive cushion layer

173-insulating layer

173 a-through hole

174 wiring layer

175 insulating layer

175 a-through hole

176 wiring layer

177 insulating layer

177 a-through hole

178a, 178 b-conductive backing layer

180-conductive layer

190-primer layer

200. 200A-wafer packaging structure

210-column structure

220-passive element

230-conductive layer

240-mold seal layer

242 to the top surface

250-carrier substrate

260-conductive bump

272. 274 adhesion layer

310-carrier substrate

320-redistribution structure

321 to insulating layer

321 a-through hole

322-conductive cushion layer

323 insulating layer

323 a-through hole

324 wiring layer

325 insulating layer

325 a-through hole

326 to wiring layer

327 insulating layer

327a through hole

328a, 328 b-conductive pad layer

330-conductive column

332-top surface

340-conductive layer

350-primer layer

360-mold sealing layer

362-Top surface

370-cap layer

372-through hole

380 mask layer

382-opening

392-conductive via structure

394-conductive line

396-conductive cushion layer

400. 400A-wafer packaging structure

410-solder mask

412 to opening

420-carrier substrate

430-conductive bump

440-packaging structure

450-conductive bump

460-primer layer

510-carrier substrate

520 solder mask

522-opening

530 seed layer

540 mask layer

542 opening to

550-wiring layer

552 to pad section

554 line part

560 to substrate layer

562-through hole

564-groove

564a bottom surface

566-top surface

570-conductive pole

572 to Top surface

580-adhesion layer

590-mold sealing layer

592 to the top surface

600. 600A-wafer packaging structure

610-redistribution structure

611 insulating layer

611 a-through hole

612-wiring layer

613 insulating layer

613 a-through hole

614 to wiring layer

615 insulating layer

615 a-through hole

616-conductive cushion layer

620-conductive bump

630-packaging structure

640-conductive bump

650-primer layer

S1, S2-side wall

T1, T2-thickness

L-conductive wire

P-conductive pad layer

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. The following disclosure describes specific examples of components and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if embodiments of the present invention describe a first feature formed on or above a second feature, that means that embodiments may include embodiments in which the first feature is in direct contact with the second feature, embodiments may also include embodiments in which additional features are formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein to facilitate describing the relationship of element(s) or feature(s) to other element(s) or feature(s) in the drawings and include different orientations of the device in use or operation and the orientation depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.

Other components and processes may also be included. For example, test structures may be included to facilitate verification testing of three-dimensional packages or three-dimensional integrated circuit components. The test structures may include, for example, test pads formed in or on a substrate in a redistribution structure that allows for testing of three-dimensional packages or three-dimensional integrated circuit elements, the use of probes and/or probe cards, and the like. In addition to the final structure, verification testing may also be performed on the relay structure. In addition, the structures and methods shown herein may be combined with testing methods, which include intermediate verification of known good dies to increase yield and reduce cost.

FIGS. 1A-1G are cross-sectional views illustrating various stages in a process for forming a wafer package structure, according to some embodiments. According to some embodiments, as shown in fig. 1A, a substrate 110 is provided. According to some embodiments, the substrate 110 includes a core layer 111,

conductive pad layers

112a and 112b, a conductive via structure 113, insulating

layers

114a, 114b, 114c, and 114d, and

wiring layers

115, 116, 117, and 118.

According to some embodiments, the conductive via structure 113 passes through the core layer 111. According to some embodiments, the core layer 111 has two opposing

faces

111a and 111 b. According to some embodiments, a conductive pad layer 112a is located over surface 111 a. According to some embodiments, the conductive pad layers 112a are respectively located on the conductive via structures 113 thereunder and connected to the conductive via structures 113. According to some embodiments, conductive pad 112b is located below surface 111 b. According to some embodiments, the conductive pad layers 112b are respectively located under the conductive via structures 113 and connected to the conductive via structures 113.

According to some embodiments, insulating layer 114a is located over surface 111a and covers conductive pad layer 112 a. According to some embodiments, the wiring layer 115 is located over the insulating layer 114 a. According to some embodiments, a portion of the wiring layer 115 passes through the insulating layer 114a and is connected to the conductive pad layer 112 a.

According to some embodiments, the insulating layer 114b is positioned on the insulating layer 114a and covers the wiring layer 115. According to some embodiments, the wiring layer 116 is located over the insulating layer 114 b. According to some embodiments, a portion of the wiring layer 116 passes through the insulating layer 114b and is connected to the wiring layer 115. According to some embodiments, wiring layer 116 includes

conductive pad layers

116a and 116b over insulating layer 114 b.

According to some embodiments, insulating layer 114c is located over surface 111b and covers conductive pad layer 112 b. According to some embodiments, a wiring layer 117 is located over the insulating layer 114 c. According to some embodiments, a portion of wiring layer 117 passes through insulating layer 114c and is connected to conductive pad layer 112 b.

According to some embodiments, insulating layer 114d is located over insulating layer 114c and covers wiring layer 117. According to some embodiments, the wiring layer 118 is located over the insulating layer 114 d. According to some embodiments, a portion of the wiring layer 118 passes through the insulating layer 114d and is connected to the wiring layer 117. According to some embodiments, wiring layer 118 includes a conductive pad layer 118a over insulating layer 114 d.

According to some embodiments, the

conductive pad layers

112a and 112b, the conductive via structure 113, and the wiring layers 115, 116, 117, and 118 include a conductive material such as copper (copper), aluminum (aluminum), or tungsten (tungsten). According to some embodiments, core layer 111 and insulating

layers

114a, 114b, 114c, and 114d comprise an insulating material, such as a polymer material.

Polymeric materials include epoxy-containing materials such as prepregs (PP) or Ajinomoto build up films (ABF). According to some embodiments, the prepreg (PP) comprises fibers. According to some embodiments, the prepreg is a fiber reinforced polymer material, pre-impregnated with an epoxy resin material. According to some embodiments, the ajinomoto build-up film (ABF) comprises a non-fibrous epoxy material. According to some embodiments, the insulating

layers

114a, 114b, 114c, and 114d are formed in a lamination process and an etching process.

According to some embodiments, as shown in fig. 1A, a conductive bump (bump)120 is formed on the conductive pad layer 116 a. According to some embodiments, the conductive bumps 120 are electrically connected to the conductive pad layers 116a therebelow respectively. According to some embodiments, the conductive bump 120 is made of solder (solder), such as Sn and Ag or other suitable conductive material (e.g., gold). According to some embodiments, the conductive bumps 120 are solder balls (solder balls).

According to some embodiments, as shown in fig. 1A, the wafer 130A is bonded to the conductive pad layer 116b of the substrate 110 by the conductive bump 140. According to some embodiments, the chip 130A is also called a system-on-chip (SoC), a logic chip, a memory chip, or an rf front end (RFFE) module such as an rf chip, a baseband (BB) chip, a power amplifier, or the like. According to some embodiments, the conductive bumps 120 surround the wafer 130A.

According to some embodiments, wafer 130A includes a semiconductor substrate 131, a dielectric layer 132, a conductive pad layer 133, and an interconnect layer 134. According to some embodiments, wafer 130A also includes conductive structures 135.

According to some embodiments, the semiconductor substrate 131 has a front surface 131a and a rear surface 131b opposite to the front surface 131 a. According to some embodiments, active devices (e.g., transistors, diodes, or the like) and/or passive devices (e.g., resistors, capacitors, inductors, or the like) are formed in the semiconductor substrate 131 below the front surface 131a or adjacent to the front surface 131 a.

According to some embodiments, the semiconductor substrate 131 is made of at least one elemental semiconductor material, including silicon or germanium in a single crystal, polycrystalline, or amorphous structure. In other embodiments, the semiconductor substrate 131 is made of a compound semiconductor, such as silicon carbide (silicon carbide), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), an alloy semiconductor such as SiGe or GaAsP, or a combination thereof. The semiconductor substrate 131 may also include multiple layers of semiconductors, Semiconductor On Insulator (SOI), such as silicon on insulator or germanium on insulator, or combinations thereof.

According to some embodiments, a dielectric layer 132 is formed below the semiconductor substrate 131. The dielectric layer 132 is made of a polymer material such as a Polybenzoxazole (PBO) layer, a polyimide (polyimide) layer, a benzocyclobutene (BCB) layer, an epoxy layer, a photosensitive material layer, or other suitable materials.

According to some embodiments, a conductive pad layer 133 is formed in the dielectric layer 132. According to some embodiments, the conductive pad layer 133 is electrically connected to a device (not shown) formed in/on the semiconductor substrate 131. According to some embodiments, the conductive pad layer 133 is made of a conductive material, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, tungsten (W), a tungsten alloy, titanium (Ti), a titanium alloy, tantalum (Ta), or a tantalum alloy.

According to some embodiments, an interconnect layer 134 is formed below the dielectric layer 132. According to some embodiments, interconnect layer 134 includes a dielectric layer (not shown) and a conductive interconnect structure (not shown) in the dielectric layer. According to some embodiments, a conductive structure 135 is formed below the interconnect layer 134. According to some embodiments, the conductive structure 135 includes conductive pillars or conductive bumps (e.g., micro-bumps).

According to some embodiments, the interconnect structure is electrically connected to the conductive structure 135 and the conductive pad layer 133. According to some embodiments, the conductive structure 135 is made of a conductive material, such as copper, a copper alloy, aluminum, an aluminum alloy, tungsten, a tungsten alloy, titanium, a titanium alloy, tantalum, or a tantalum alloy.

According to some embodiments, the conductive structures 135 are respectively bonded to the conductive pad layer 116b thereunder through the conductive layer 140 therebetween. According to some embodiments, the conductive layer 140 is made of solder, such as Sn and Ag or other suitable conductive materials (e.g., gold). According to some embodiments, as shown in fig. 1A, a primer (underfill) layer 150 is formed between the wafer 130A and the substrate 110. According to some embodiments, primer layer 150 includes an insulating material, such as a polymeric material.

According to some embodiments, as illustrated in fig. 1B, a carrier substrate 160 is provided. According to some embodiments, the carrier substrate 160 is configured to provide temporary mechanical and structural support during subsequent process steps. According to some embodiments, the carrier substrate 160 includes glass, silicon oxide (silicon oxide), aluminum oxide (aluminum oxide), metal, combinations thereof, and/or the like. According to some embodiments, the carrier substrate 160 includes a metal frame.

According to some embodiments, as illustrated in fig. 1B, a redistribution structure 170 is formed over the carrier substrate 160. Forming redistribution structure 170 includes forming insulating layer 171 over carrier substrate 160; forming a conductive pad layer 172 on the insulating layer 171 and in the through hole 171a of the insulating layer 171; forming an insulating layer 173 on the insulating layer 171 and the conductive pad layer 172; forming a wiring layer 174 on the insulating layer 173 and in the via hole 173a of the insulating layer 173; forming an insulating layer 175 over the insulating layer 173 and the wiring layer 174; forming a wiring layer 176 on the insulating layer 175 and in the via 175a of the insulating layer 175; forming an insulating layer 177 over the insulating layer 175 and the wiring layer 176; and forming

conductive pads

178a and 178b on the insulating layer 177 and in the via 177a of the insulating layer 177. According to some embodiments, the conductive pad layer 178a is wider than the conductive pad layer 178 b. According to some embodiments, conductive pad layer 178a surrounds conductive pad layer 178 b.

According to some embodiments, the conductive pad layer 172 directly contacts the carrier substrate 160. In some other embodiments (not shown), the conductive pad layer 172 is spaced apart from the carrier substrate 160. According to some embodiments, the wiring layers 174 and 176 are electrically connected to each other. According to some embodiments, the conductive pad layers 172, 178a, and 178b are electrically connected to the wiring layers 174 and 176.

According to some embodiments, the insulating

layers

171, 173, 175, and 177 are made of an insulating material such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), silicon oxynitride (silicon oxynitride), or the like. According to some embodiments, the routing layers 174 and 176 and the

conductive pads

172, 178a, and 178b are made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten).

According to some embodiments, as illustrated in fig. 1B, wafer 130B is bonded to conductive pad layer 178B of redistribution structure 170. According to some embodiments, wafer 130B is similar to or the same as wafer 130A of fig. 1A. According to some embodiments, the wafer 130B includes a semiconductor substrate 131, a dielectric layer 132, a conductive pad layer 133, an interconnect layer 134, and a conductive structure 135, which are similar to or identical to the semiconductor substrate 131, the dielectric layer 132, the conductive pad layer 133, the interconnect layer 134, and the conductive structure 135 of the wafer 130A of fig. 1A, respectively. Accordingly, the details of wafer 130B are not repeated here.

According to some embodiments, the conductive structures 135 are respectively bonded to the underlying conductive pad layers 178b with the conductive layer 180 therebetween. According to some embodiments, conductive layer 180 is made of solder, such as Sn and Ag or other suitable conductive materials (e.g., gold).

According to some embodiments, as illustrated in fig. 1B, an underfill layer 190 is formed between the wafer 130B and the redistribution structure 170. According to some embodiments, the make layer 190 comprises an insulating material, such as a polymeric material.

According to some embodiments, as illustrated in fig. 1B, a pillar structure 210 is formed on the conductive pad layer 178a of the redistribution structure 170. According to some embodiments, the pillar structures 210 are made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten).

According to some embodiments, as illustrated in fig. 1C, the substrate 110 is bonded to the redistribution structure 170 through the conductive bump 120. According to some embodiments, the dies 130A and 130B are located between the substrate 110 and the redistribution structure 170. According to some embodiments, the conductive bump 120 surrounds the

wafers

130A and 130B.

According to some embodiments, the bonding process includes disposing the conductive bump 120 on the pillar structure 210; and performing a reflow process to connect the conductive bump 120 to the pillar structure 210. According to some embodiments, the pillar structures 210 penetrate the conductive bumps 120 during a reflow process.

According to some embodiments, as shown in fig. 1D, the substrate 110 has two

opposite surfaces

119a and 119 b. According to some embodiments, the surface 119a faces away from the redistribution structure 170. According to some embodiments, the substrate 110 has a sidewall 119c between the

surfaces

119a and 119 b. According to some embodiments, as illustrated in FIG. 1D, the dies 130C and 130D and the passive component 220 are bonded to the surface 119 a. In other embodiments, a passive element (not shown) is bonded to surface 119 b. According to some embodiments,

wafers

130C and 130D are similar or identical to wafer 130A in fig. 1A.

According to some embodiments, each of the dies 130C and 130D includes a semiconductor substrate 131, a dielectric layer 132, a conductive pad 133, an interconnect layer 134, and a conductive structure 135, which are similar to or identical to the semiconductor substrate 131, the dielectric layer 132, the conductive pad 133, the interconnect layer 134, and the conductive structure 135 of the die 130A of fig. 1A, respectively. Accordingly, the details of

wafers

130C and 130D are not repeated here.

According to some embodiments, the conductive structures 135 are respectively bonded to the underlying conductive pad layers 118a with the conductive layer 230 therebetween. According to some embodiments,

wafers

130C and 130D are electrically connected to redistribution structure 170 through conductive layer 230, wiring layers 117 and 118,

conductive pads

112a and 112b, conductive via structure 113, wiring layers 115 and 116, conductive bump 120, and pillar structure 210.

According to some embodiments, conductive layer 230 is made of solder, such as Sn and Ag or other suitable conductive materials. According to some embodiments, the passive element 220 is electrically connected to the wiring layers 117 and 118. According to some embodiments, the passive element 220 includes a resistor, an inductor, a capacitor, or other suitable passive elements.

According to some embodiments, as illustrated in fig. 1E, a mold seal layer 240 is formed between the substrate 110 and the redistribution structure 170, and formed on the sidewall 119c and the surface 119a of the substrate 110. According to some embodiments, molding layer 240 encapsulates dies 130A and 130B. According to some embodiments, the molding layer 240 surrounds the dies 130A and 130B, the conductive bumps 120, and the pillar structures 210.

According to some embodiments, the molding layer 240 encapsulates the dies 130C and 130D and the passive components 220. According to some embodiments, the molding layer 240 surrounds the dies 130C and 130D and the passive components 220.

According to some embodiments, top surface 242 of mold layer 240 is substantially coplanar with top surface 136 of wafer 130C. According to some embodiments, the top surface 136 of the wafer 130C is exposed to the external atmosphere, which improves heat dissipation. According to some embodiments, a portion of mold layer 240 is located between sidewall S1 of wafer 130A and sidewall S2 of wafer 130B.

According to some embodiments, the mold seal layer 240 is made of an insulating material, such as a polymer material. According to some embodiments, the mold layer 240 is formed in the same molding process (e.g., a transfer molding process) and thus made of the same material. According to some embodiments, the material of the molding layer 240 is different from the material of the core layer 111 and the insulating

layers

114a, 114b, 114c, and 114 d.

According to some embodiments, as illustrated in fig. 1F, a carrier substrate 250 is bonded to the encapsulation layer 240. According to some embodiments, the carrier substrate 250 is configured to provide temporary mechanical and structural support during subsequent process steps. According to some embodiments, the carrier substrate 250 includes glass, silicon oxide, aluminum oxide, metal, combinations thereof, and/or the like. According to some embodiments, the carrier substrate 250 comprises a metal frame.

According to some embodiments, as illustrated in fig. 1F, the carrier substrate 160 is removed. According to some embodiments, the substrate 110 is turned upside down. According to some embodiments, as depicted in fig. 1F, the insulating layer 171 of the redistribution structure 170 is removed. In some other embodiments (not shown), insulating layer 171 is partially removed to expose more of the surface of conductive pad layer 172. According to some embodiments, the insulating layer 171 is (partially) removed in a dry etch process or a wet etch process.

According to some embodiments, as shown in fig. 1F, conductive bumps 260 are formed on the conductive pad layers 172, respectively. According to some embodiments, the conductive bumps 260 are made of a conductive material, such as solder (e.g., Sn, Ag, or Au).

According to some embodiments, as illustrated in fig. 1G, a cutting process is performed on the redistribution structure 170 to cut through the redistribution structure 170 and the mold encapsulation layer 240 to form the wafer package structure 200. For simplicity, FIG. 1G shows only one of the chip package structures 200.

According to some embodiments, in the chip package structure 200, the substrate 110 has a thickness T1, and the redistribution structure 170 has a thickness T2. According to some embodiments, the thickness T1 is greater than the thickness T2. According to some embodiments, the ratio of the thickness T1 to the thickness T2 ranges from about 7 to about 13.

According to some embodiments, in the chip package structure 200, the conductive pad layer 118a is electrically connected to the conductive pad layer 116b through the wiring layer 117, the conductive pad layer 112b, the conductive via structure 113, the conductive pad layer 112a, and the wiring layer 115. Thus, according to some embodiments,

wafers

130C and 130D may be electrically connected to wafer 130A.

According to some embodiments, wafer 130C (or wafer 130D) may be placed face-to-face with wafer 130A, and thus the electrical connection path between wafer 130C (or wafer 130D) and wafer 130A is short. As a result, the operating speed of the chip package structure 200 is improved, which improves the performance of the chip package structure 200. Furthermore, according to some embodiments, the power consumption of the die package structure 200 is reduced.

According to some embodiments, since the two opposite sides of the substrate 110 can be bonded to the die, the integration density of the dies 130A, 130C, and 130D is improved, which can reduce the size of the die package 200. According to some embodiments, the active devices (e.g., the dies 130A, 130B, 130C, and 130D) and the passive devices 220 may be integrated on the substrate 110 and the redistribution structure 170 in the chip package structure 200.

Since the material of the substrate 110 (or the core layer 111 and the insulating

layers

114a, 114b, 114c, and 114d) is different from that of the mold layer 240, the thicknesses of the substrate 110 and the mold layer 240 may be adjusted to reduce the warpage of the chip package structure 200. The appropriate thickness ratio of the substrate 110 to the molding layer 240 can be calculated by computer simulation. According to some embodiments, reliability of the joints (e.g., conductive bumps 120) of the wafer package structure 200 is improved due to the reduced warpage of the wafer package structure 200.

Fig. 2 is a cross-sectional view of a wafer package structure 200A according to some embodiments. According to some embodiments, as illustrated in fig. 2, a wafer package structure 200A is similar to the wafer package structure 200 of fig. 1G, except that the wafer package structure 200A further includes adhesion layers 272 and 274.

According to some embodiments, an adhesion layer 272 is located between wafer 130A and redistribution structure 170. According to some embodiments, an adhesion layer 274 is located between the wafer 130B and the substrate 110. According to some embodiments, the adhesion layers 272 and 274 are made of a polymer material, a heat sink material (e.g., silver paste, copper paste, or solder paste), or other suitable material. According to some embodiments, the adhesion layers 272 and 274 are made of the same material. In other embodiments, the adhesion layers 272 and 274 are made of different materials.

In some embodiments, an adhesion layer 272 is formed over wafer 130A prior to bonding substrate 110 to redistribution structure 170. In other embodiments, the adhesion layer 272 is formed over the redistribution structure 170 prior to bonding the substrate 110 to the redistribution structure 170.

According to some embodiments, an adhesion layer 274 is formed over wafer 130B prior to bonding substrate 110 to redistribution structure 170. In other embodiments, the adhesion layer 274 is formed over the substrate 110 prior to bonding the substrate 110 to the redistribution structure 170.

Fig. 3A-3H are cross-sectional views of various stages in a process for forming a chip package structure, according to some embodiments. According to some embodiments, as shown in fig. 3A, a carrier substrate 310 is provided. According to some embodiments, the carrier substrate 310 is configured to provide temporary mechanical and structural support during subsequent process steps.

According to some embodiments, the carrier substrate 310 comprises glass, silicon oxide, aluminum oxide, metal, combinations thereof, and/or the like. According to some embodiments, the carrier substrate 310 comprises a metal frame. In some embodiments (not shown), an adhesion layer is applied over the carrier substrate 310 for a subsequent lift-off process.

According to some embodiments, as illustrated in fig. 3A, a redistribution structure 320 is formed over a carrier substrate 310. Forming the redistribution structure 320 includes forming an insulating layer 321 over the carrier substrate 310; forming a conductive pad layer 322 on the insulating layer 321 and in the via hole 321a of the insulating layer 321; forming an insulating layer 323 over the insulating layer 321 and the conductive pad layer 322; forming a wiring layer 324 on the insulating layer 323 and in the through hole 323a of the insulating layer 323; forming an insulating layer 325 over the insulating layer 323 and the wiring layer 324; forming a wiring layer 326 on the insulating layer 325 and in the via 325a of the insulating layer 325; forming an insulating layer 327 on the insulating layer 325 and the wiring layer 326; and forming

conductive pads

328a and 328b on insulating layer 327 and in vias 327a of insulating layer 327.

According to some embodiments, conductive pad 328a is wider than conductive pad 328 b. According to some embodiments, conductive pad layer 328a surrounds conductive pad layer 328 b. According to some embodiments, the conductive pad layer 322 directly contacts the carrier substrate 310. In some other embodiments (not shown), the conductive pad layer 322 is spaced apart from the carrier substrate 310.

According to some embodiments, the routing layers 324 and 326 are electrically connected to each other. According to some embodiments,

conductive pads

322, 328a, and 328b are electrically connected to wiring layers 324 and 326.

According to some embodiments, the insulating

layers

321, 323, 325, and 327 are made of an insulating material such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), silicon oxynitride, or the like. According to some embodiments, routing layers 324 and 326 and

conductive pads

322, 328a, and 328b are made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten).

According to some embodiments, as illustrated in fig. 3A, the conductive pillars 330 are formed on the conductive pad layer 328a of the redistribution structure 320. According to some embodiments, the pillar structures 330 are made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten).

Thereafter, according to some embodiments, as illustrated in fig. 3A, wafer 130E is bonded to conductive pad layer 328b of redistribution structure 320. According to some embodiments, the columnar structures 330 surround the wafer 130E. In some embodiments (not shown), the top surface of wafer 130E is substantially coplanar with the top surface of pillar structures 330. According to some embodiments, wafer 130E is similar to or the same as wafer 130A of fig. 1A.

According to some embodiments, the wafer 130E includes a semiconductor substrate 131, a dielectric layer 132, a conductive pad layer 133, an interconnect layer 134, and a conductive structure 135, which are similar to or identical to the semiconductor substrate 131, the dielectric layer 132, the conductive pad layer 133, the interconnect layer 134, and the conductive structure 135 of the wafer 130A of fig. 1A, respectively. Accordingly, details of wafer 130E are not repeated here.

According to some embodiments, the conductive structures 135 are respectively bonded to the underlying conductive pad layer 328b with the conductive layer 340 therebetween. According to some embodiments, conductive layer 340 is made of solder, such as Sn and Ag or other suitable conductive materials. According to some embodiments, as illustrated in fig. 3A, an underfill layer 350 is formed between the wafer 130E and the redistribution structure 320. According to some embodiments, the make layer 350 includes an insulating material, such as a polymeric material.

According to some embodiments, as illustrated in fig. 3B, a mold layer 360 is formed over the redistribution structure 320. According to some embodiments, the molding layer 360 surrounds the conductive pillars 330 and the wafer 130E. According to some embodiments, an encapsulation layer 360 covers the wafer 130E. According to some embodiments, the conductive posts 330 penetrate the molding layer 360.

According to some embodiments, as depicted in fig. 3B, the top surface 332 of the conductive pillar 330 and the top surface 362 of the mold seal layer 360 are substantially coplanar. The mold seal 360 is made of a polymer material, such as Ajinomoto Buildupfilm (ABF). According to some embodiments, the ajinomoto-enhanced membrane comprises a non-fibrous epoxy material. According to some embodiments, the mold layer 360 is formed using a molding process, such as a transfer molding process.

According to some embodiments, as illustrated in fig. 3C, a cap layer 370 is formed on the mold sealing layer 360 and the conductive pillars 330. According to some embodiments, cap layer 370 directly contacts mold seal layer 360. According to some embodiments, cover layer 370 comprises fibers. According to some embodiments, cover layer 370 is made of a fibrous polymer material, such as a prepreg. According to some embodiments, cap layer 370 and mold seal layer 360 are made of different materials. According to some embodiments, capping layer 370 is formed using a lamination process.

Thereafter, according to some embodiments, as illustrated in fig. 3C, a via 372 is formed in the cap layer 370. According to some embodiments, the vias 372 expose the underlying conductive pillars 330, respectively. According to some embodiments, the via 372 is formed using a laser drilling process, a wet etching process, or a dry etching process.

According to some embodiments, as illustrated in fig. 3D, a mask layer 380 is formed over the cap layer 370. According to some embodiments, the mask layer 380 is made of a polymer material, such as a photoresist material. According to some embodiments, the mask layer 380 is formed using a coating process.

According to some embodiments, as illustrated in fig. 3D, an opening 382 is formed in the mask layer 380. According to some embodiments, opening 382 exposes a portion of cap layer 370. According to some embodiments, the openings 382 are respectively located above the vias 372 and connected to the vias 372. According to some embodiments, the opening 382 is formed using a photolithographic process.

According to some embodiments, as depicted in fig. 3D, a conductive via structure 392, a conductive line 394, and a conductive pad layer 396 are formed. According to some embodiments, the conductive via structures 392 are respectively formed in the through holes 372. According to some embodiments, a conductive line 394 is formed over capping layer 370.

According to some embodiments, the conductive pad layer 396 is partially over the conductive via structure 392 thereunder and is electrically connected to the conductive via structure 392. According to some embodiments, the conductive via structures 392 are respectively connected to the underlying conductive pillars 330. According to some embodiments, the conductive via structures 392 are in direct contact with the underlying conductive pillars 330, respectively.

According to some embodiments, as depicted in fig. 3E, the mask layer 380 is removed. According to some embodiments, as depicted in fig. 3E, a solder mask layer 410 is formed over the cap layer 370, the conductive pad layer 396, and the conductive line 394. According to some embodiments, as illustrated in fig. 3E, an opening 412 is formed in the solder mask layer 410.

According to some embodiments, the openings 412 expose the conductive pad layers 396, respectively. According to some embodiments, the solder mask layer 410 is made of a polymer material, such as a photoresist material. According to some embodiments, the solder resist layer 410 is formed using a coating process. According to some embodiments, the solder mask layer 410 is made of a photoresist material and the opening 412 is formed using a photolithography process. In some embodiments (not shown), a surface treatment layer is formed over conductive pad layer 396. The surface treatment layer includes, for example, electroless nickel gold (ENIG), electroless nickel palladium immersion gold (ENEPIG), and/or solder paste.

According to some embodiments, as shown in fig. 3F, the carrier substrate 420 is bonded to the solder resist layer 410. According to some embodiments, the carrier substrate 420 is configured to provide temporary mechanical and structural support during subsequent process steps. According to some embodiments, the carrier substrate 420 comprises glass, silicon oxide, aluminum oxide, metal, combinations thereof, and/or the like. According to some embodiments, the carrier substrate 420 comprises a metal frame.

According to some embodiments, as shown in fig. 3G, the carrier substrate 310 is removed. According to some embodiments, the removal process is also referred to as a lift-off process. According to some embodiments, the redistribution structure 320 is flipped upside down, as shown in fig. 3G. According to some embodiments, the insulating layer 321 of the redistribution structure 320 is removed, as shown in fig. 3G. In some embodiments (not shown), insulating layer 321 is partially removed to expose more of the surface of conductive pad layer 322. According to some embodiments, the insulating layer 321 is (partially) removed in a dry etch process or a wet etch process.

According to some embodiments, as shown in fig. 3G, a conductive bump 430 is formed on the conductive pad layer 322. According to some embodiments, redistribution structure 320 is located between conductive bump 430 and encapsulation layer 360. According to some embodiments, the conductive bumps 430 are made of a conductive material, such as solder (solder), for example Sn, Ag, or Au.

According to some embodiments, as shown in fig. 3H, a lift-off process is performed to remove the carrier substrate 420 from the solder mask layer 410. According to some embodiments, as shown in fig. 3H, a dicing process is performed to cut through the redistribution structure 320, the mold seal layer 360, the cap layer 370, and the solder resist layer 410 to form the chip package structure 400. For simplicity, fig. 3H illustrates only one of the die package structures 400, according to some embodiments.

According to some embodiments, the method of forming the wafer package structure 400 forms the capping layer 370 directly on the mold sealing layer 360 without using conductive bumps, and thus reduces the size (e.g., height) of the wafer package structure 400.

Since the cover layer 370 and the mold sealing layer 360 are made of different materials, the warpage of the die package structure 400 can be reduced by adjusting the thicknesses of the cover layer 370 and the mold sealing layer 360. A suitable thickness ratio of cap layer 370 to mold seal layer 360 may be calculated by computer simulation.

According to some embodiments, reliability of the joints of wafer package structure 400 is improved due to the reduced warpage of wafer package structure 400. According to some embodiments, the terminals of the chip package structure 400 include a conductive layer 340, a conductive structure 135, and a conductive pad layer 328 b.

Fig. 4 illustrates a cross-sectional view of a wafer package structure 400A, according to some embodiments. According to some embodiments, as shown in fig. 4, a die package structure 400A is similar to the die package structure 400 of fig. 3H, except that the die package structure 400A further includes a package structure 440 bonded to a conductive pad layer 396 of the die package structure 400 by conductive bumps 450. The die package structure 400A may further include a primer layer 460 formed between the package structure 440 and the solder resist layer 410.

According to some embodiments, forming the package structure 440 and the underfill layer 460 includes, for example, bonding the package structure 440 to the conductive pad layer 396 of fig. 3E; thereafter, a primer layer 460 is formed between the package structure 440 and the solder resist layer 410 in fig. 3E; thereafter, the steps of FIGS. 3F-3G are performed; and then, as shown in fig. 4, a dicing process is performed to cut through the redistribution structure 320, the mold sealing layer 360, the cap layer 370, the solder resist layer 410, and the underfill layer 460 to form a chip package structure 400A. For simplicity, fig. 4 illustrates only one of the die package structures 400A, according to some embodiments.

The package structure 440 may include one or more dies (e.g., dynamic random access memory dies, not shown), one or more wiring substrates (not shown), redistribution structures (not shown), conductive bumps (not shown), or other suitable components. According to some embodiments, the conductive bumps 450 are made of solder such as Sn and Ag or other suitable conductive materials (e.g., gold). According to some embodiments, the underfill layer 460 is partially located between the package structure 440 and the solder resist layer 410.

Fig. 5A-5H are cross-sectional views of various stages in a process for forming a wafer package structure, according to some embodiments. According to some embodiments, as illustrated in fig. 5A, a carrier substrate 510 is provided. According to some embodiments, the carrier substrate 510 is configured to provide temporary mechanical and structural support during subsequent process steps.

According to some embodiments, the carrier substrate 510 includes glass, silicon oxide, aluminum oxide, metal, combinations thereof, and/or the like. According to some embodiments, the carrier substrate 510 includes a metal frame.

According to some embodiments, as illustrated in fig. 5A, a solder mask layer 520 is formed on a carrier substrate 510. According to some embodiments, the solder mask layer 520 is made of a polymer material, such as a photoresist material. According to some embodiments, the solder resist layer 520 is formed using a coating process.

According to some embodiments, as illustrated in fig. 5A, a seed layer 530 is formed on the solder resist layer 520. According to some embodiments, the seed layer 530 is formed using a deposition process, such as a physical vapor deposition process. The seed layer 530 is made of titanium, copper, and/or other suitable conductive material.

According to some embodiments, as illustrated in fig. 5A, a mask layer 540 is formed over the seed layer 530. According to some embodiments, the mask layer 540 is made of a polymer material, such as a photoresist material. According to some embodiments, the mask layer 540 is formed using a coating process.

According to some embodiments, as illustrated in fig. 5A, an opening 542 is formed in the mask layer 540. According to some embodiments, the opening 542 exposes a portion of the seed layer 530. According to some embodiments, the opening 542 is formed using a photolithographic process.

According to some embodiments, as illustrated in fig. 5A, a wiring layer 550 is formed in the opening 542 and over the seed layer 530. According to some embodiments, routing layer 550 includes pad portions 552 and line portions 554. According to some embodiments, the wiring layer 550 is made of a conductive material such as copper, aluminum, or tungsten. According to some embodiments, the wiring layer 550 is formed using an electroplating process.

According to some embodiments, as depicted in fig. 5B, the mask layer 540 is removed. According to some embodiments, the masking layer 540 is removed using a photolithography process. Then, according to some embodiments, as illustrated in fig. 5B, the seed layer 530, which was originally covered by the mask layer 540, is removed.

According to some embodiments, the seed layer 530, which was originally covered by the mask layer 540, is removed using an etching process. According to some embodiments, the pad portion 552 and the seed layer 530 remaining under the pad portion 552 together form a conductive pad layer P. According to some embodiments, the line portion 554 and the seed layer 530 remaining below the line portion 554 together form a conductive line L.

According to some embodiments, as illustrated in fig. 5B, a substrate layer 560 is formed over the solder resist layer 520 and the wiring layer 550. According to some embodiments, the routing layer 550 is embedded in the substrate layer 560. According to some embodiments, the substrate layer 560 is made of a polymer material, such as a prepreg (PP) or Ajinomotobuildup film (ABF) comprising fibers and epoxy. According to some embodiments, the substrate layer 560 is formed using a lamination process.

According to some embodiments, as illustrated in fig. 5C, vias 562 are formed in the substrate layer 560. According to some embodiments, vias 562 expose pad portions 552, respectively. According to some embodiments, via 562 is formed using a laser drilling process, a dry etching process, or a wet etching process.

According to some embodiments, as illustrated in fig. 5C, a conductive pillar 570 is formed in the via 562. According to some embodiments, the conductive post 570 is copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), or tantalum alloy. According to some embodiments, the conductive pillars 570 are formed using an electroplating process.

According to some embodiments, as illustrated in fig. 5D, a portion of the substrate layer 560 is removed to form a recess 564 in the substrate layer 560. According to some embodiments, the groove 564 does not pass through the substrate layer 560. According to some embodiments, the groove 564 has a bottom surface 564 a. According to some embodiments, the groove 564 is formed using a laser drilling process, a dry etching process, or a wet etching process. According to some embodiments, as illustrated in fig. 5D, the wafer 130F is located in the groove 564. According to some embodiments, the substrate layer 560 is partially located between the wafer 130F and the carrier substrate 510.

According to some embodiments, wafer 130F is similar to or the same as wafer 130A of fig. 1A. Wafer 130F includes a semiconductor substrate 131, a dielectric layer 132, a conductive pad 133, an interconnect layer 134, and a conductive structure 135, which are similar to or identical to the semiconductor substrate 131, the dielectric layer 132, the conductive pad 133, the interconnect layer 134, and the conductive structure 135 of wafer 130A of fig. 1A, respectively. Accordingly, details of wafer 130F are not repeated here.

In some embodiments, wafer 130F is bonded to bottom surface 564a by an adhesion layer 580. According to some embodiments, an adhesion layer 580 is located between the wafer 130F and the substrate layer 560. According to some embodiments, the adhesion layer 580 is made of a polymer material, a heat sink material (e.g., silver paste, copper paste, or solder paste), or other suitable material.

According to some embodiments, as shown in fig. 5D, a molding layer 590 is formed in the groove 564 and on the substrate layer 560 and the conductive post 570. According to some embodiments, the mold seal 590 covers the entire wafer 130F. According to some embodiments, the mold seal 590 is made of a polymeric material. According to some embodiments, the mold layer 590 and the substrate layer 560 are made of different materials.

According to some embodiments, as shown in fig. 5E, a thinning process is performed on the molding layer 590 until the conductive structures 135 and the conductive pillars 570 of the wafer 130F are exposed. According to some embodiments, the thinning process comprises a chemical mechanical polishing process.

According to some embodiments, the top surface 135a of the conductive structure 135, the top surface 592 of the mold seal 590, the top surface 566 of the substrate layer 560, and the top surface 572 of the conductive post 570 are substantially coplanar. According to some embodiments, the entire wafer 130F is located within the recess 564.

According to some embodiments, as illustrated in fig. 5F, the redistribution structure 610 is formed on the substrate layer 560, the conductive pillars 570, the molding compound 590, and the wafer 130F. According to some embodiments, forming the redistribution structure 610 includes forming an insulating layer 611 over the substrate layer 560, the conductive pillars 570, the molding compound 590, and the wafer 130F; forming a wiring layer 612 on the insulating layer 611 and in the through hole 611a of the insulating layer 611; forming an insulating layer 613 over the insulating layer 611 and the wiring layer 612; forming a wiring layer 614 on the insulating layer 613 and in the via 613a of the insulating layer 613; forming an insulating layer 615 over the insulating layer 613 and the wiring layer 614; and forming a conductive pad layer 616 on the insulating layer 615 and in the via 615a of the insulating layer 615. According to some embodiments, conductive pad layer 616 may include an under bump metallization layer. The conductive pad layer 616 includes a conductive material such as copper, a copper alloy, titanium, a titanium alloy, or other suitable material.

In some embodiments, the routing layer 612 directly contacts the conductive pillars 570 and the conductive structures 135. According to some embodiments, the routing layers 612 and 614 and the conductive pad layer 616 are electrically connected to each other.

According to some embodiments, the insulating

layers

611, 613, and 615 are made of an insulating material such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), silicon oxynitride, or the like. According to some embodiments, the routing layers 612 and 614 and the conductive pad layer 616 are made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten).

According to some embodiments, as illustrated in fig. 5G, a conductive bump 620 is formed on the conductive pad layer 616. According to some embodiments, the redistribution structure 610 is partially located between the conductive bump 620 and the mold encapsulation layer 590. According to some embodiments, the redistribution structure 610 is partially located between the conductive bump 620 and the substrate layer 560. According to some embodiments, the conductive bumps 620 are made of a conductive material, such as solder (e.g., Sn, Ag, or Au).

According to some embodiments, as illustrated in fig. 5H, the carrier substrate 510 is removed. According to some embodiments, the redistribution structure 610 is flipped upside down, as depicted in fig. 5H. According to some embodiments, as depicted in fig. 5H, a portion of the solder resist layer 520 is removed to form an opening 522 in the solder resist layer 520.

According to some embodiments, the opening 522 exposes the conductive pad layer P. According to some embodiments, the opening 522 is formed using a dry etch process or a wet etch process. According to some embodiments, the solder mask layer 520 is made of a photoresist material and the opening 522 is formed using a photolithography process. In some embodiments (not shown), after the opening 522 is formed, the seed layer 530 under the opening 522 is partially removed.

Thereafter, according to some embodiments, as illustrated in fig. 5H, a dicing process is performed to cut through the solder resist layer 520, the substrate layer 560, and the redistribution structure 610 to form the chip package structure 600. For simplicity, fig. 5H illustrates only one of the die package structures 600, according to some embodiments.

According to some embodiments, in the wafer package structure 600, the wafer 130F is completely located in the recess 564 of the substrate layer 560, and thus the size (e.g., height) of the wafer package structure 600 is reduced.

Fig. 6 is a cross-sectional view of a wafer package structure 600A, according to some embodiments. According to some embodiments, as shown in fig. 6, a chip package structure 600A is similar to the chip package structure 600 of fig. 5H, except that the chip package structure 600A further includes a package structure 630 bonded to the conductive pad P of the chip package structure 600 through conductive bumps 640. The die package structure 600A may further include a primer layer 650 formed between the package structure 630 and the solder resist layer 520.

According to some embodiments, forming the package structure 630 and the underfill layer 650 includes, for example, bonding the package structure 630 to the conductive pad layer P of fig. 5H before performing the dicing process; thereafter, a primer layer 650 is formed between the package structure 630 and the solder resist layer 520 of fig. 5H before the cutting process is performed; and then, as shown in fig. 6, a cutting process is performed to cut through the underfill layer 650, the solder resist layer 520, the substrate layer 560, and the redistribution structure 610 to form the chip package structure 600A. For simplicity, fig. 6 illustrates only one of the die package structures 600A, according to some embodiments.

The package structure 630 may include one or more dies (not shown), one or more wiring substrates (not shown), redistribution structures (not shown), conductive bumps (not shown), or other suitable elements. According to some embodiments, the conductive bumps 640 are made of solder such as Sn and Ag or other suitable conductive materials (e.g., gold). According to some embodiments, the make layer 650 is partially located between the package structure 630 and the solder resist layer 520.

According to some embodiments, a method of forming a wafer package structure is provided. The method includes forming conductive pillars over the redistribution structure. The method includes bonding a die to the redistribution structure. The method includes forming a mold seal layer over the redistribution structure. The mold sealing layer surrounds the conductive posts and the wafer, and the conductive posts penetrate through the mold sealing layer. The method includes forming a cap layer over the mold seal layer and the conductive pillars. The cover layer is provided with a through hole exposing the conductive post and comprises fibers. The method includes forming a conductive via structure in the via. The conductive via structure is connected to the conductive pillar. In one embodiment, the method further comprises forming a conductive pad layer and a conductive line on the cap layer after forming the conductive via structure in the via, the conductive pad layer portion being located on and electrically connected to the conductive via structure. In one embodiment, the method further includes forming a solder mask over the cap layer, the conductive pad layer, and the conductive line, the solder mask having an opening exposing the conductive pad layer. In one embodiment, the method further includes forming a conductive bump on the redistribution structure after forming the solder resist layer on the cap layer, the conductive pad layer, and the conductive line, the redistribution structure being between the conductive bump and the mold encapsulation layer. In one embodiment, the cap layer is in direct contact with the mold seal layer. In one embodiment, the cap layer and the molding layer are made of different materials.

According to some embodiments, a method of forming a wafer package structure is provided. The method includes bonding a first die to a substrate. The method includes bonding a second wafer to the redistribution structure. The method includes bonding a substrate to a redistribution structure. The first chip and the second chip are located between the substrate and the redistribution structure. The method includes forming a first molding compound between the substrate and the redistribution structure to encapsulate the first chip and the second chip. In one embodiment, the method further includes bonding a third wafer to a surface of the substrate, the surface facing away from the redistribution structure, after bonding the substrate to the redistribution structure. In one embodiment, the method further includes forming a second molding compound on the surface of the substrate, the second molding compound surrounding the third die. In one embodiment, the first top surface of the second molding layer is substantially coplanar with the second top surface of the third die. In one embodiment, the substrate is bonded to the redistribution structure by conductive bumps. In one embodiment, the method further includes forming a pillar over the redistribution structure prior to bonding the substrate to the redistribution structure, the pillar penetrating the conductive bump after bonding the substrate to the redistribution structure. In one embodiment, a portion of the first film seal layer is located between the first sidewall of the first wafer and the second sidewall of the second wafer. In one embodiment, the method further includes forming an adhesion layer on the first die prior to bonding the substrate to the redistribution structure, the first die being bonded to the redistribution structure through the adhesion layer while bonding the substrate to the redistribution structure. In an embodiment, the substrate comprises fibers.

According to some embodiments, a method of forming a wafer package structure is provided. The method includes forming a conductive pad layer on a carrier substrate. The method includes forming a substrate layer on a carrier substrate. The conductive mat layer is embedded in a substrate layer, and the substrate layer includes fibers. The method includes forming a via in the substrate layer and exposing the conductive pad layer. The method includes forming a conductive pillar in the via. The method includes forming a recess in a substrate layer. The method includes placing a wafer in the recess. The method includes forming a mold seal layer in the recess. The method includes forming a redistribution structure on the substrate layer, the conductive pillars, the molding compound layer, and the wafer. The method includes removing the carrier substrate. In one embodiment, the substrate layer portion is positioned between the wafer and the carrier substrate prior to removing the carrier substrate. In one embodiment, the method further includes forming a solder mask layer on the carrier substrate before forming the conductive pad layer on the carrier substrate, forming the conductive pad layer on the solder mask layer, and forming an opening in the solder mask layer after removing the carrier substrate, the opening exposing the conductive pad layer. In one embodiment, placing the wafer in the recess includes bonding the wafer to a bottom surface of the recess through an adhesion layer. In one embodiment, the method further includes forming a conductive bump on the redistribution structure, the redistribution structure being located between the conductive bump and the substrate layer.

The foregoing outlines features of many embodiments so that those skilled in the art may better understand the embodiments of the present disclosure in various aspects. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. Various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments of the invention as defined by the appended claims. Moreover, while the present invention has been described in terms of several preferred embodiments, it is not intended to be limited to the embodiments disclosed herein, and not all advantages have been described in detail.

Claims

1. A method for forming a chip package structure includes:

forming a conductive pillar over a redistribution structure;

bonding a chip to the redistribution structure;

forming a mold sealing layer on the redistribution structure, wherein the mold sealing layer surrounds the conductive pillar and the chip, and the conductive pillar penetrates through the mold sealing layer;

forming a cover layer on the mold sealing layer and the conductive post, wherein the cover layer has a through hole exposing the conductive post, and the cover layer comprises fibers; and

forming a conductive via structure in the via hole, wherein the conductive via structure is connected to the conductive pillar.