CN110931359A

CN110931359A - Method for manufacturing semiconductor element

Info

Publication number: CN110931359A
Application number: CN201910892072.4A
Authority: CN
Inventors: 吴志强; 刘国安; 杨建伦; 巴拉特·库玛·泰伦迦纳; 林立德; 吴忠纬; 张广兴; 林斌彦
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-09-20
Filing date: 2019-09-20
Publication date: 2020-03-27

Abstract

A method of manufacturing a semiconductor device includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposing sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. The first ion beam is directed to an upper portion of the trench, while a lower portion of the trench is substantially free of the first ion beam incident thereon. During the directing of the first ion beam to the trench, the substrate is moved relative to the first ion beam. A gate structure is formed in the trench.

Description

Method for manufacturing semiconductor element

Technical Field

The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background

Two conventional fabrication processes used in the fabrication of semiconductor devices are deposition and etching processes. For example, the deposition process includes ion beam deposition. These deposition and etching processes are the basic processes for device operation and physical dimensions. Various controls on the deposition and etch processes result in benefits including, for example: enhanced device characteristics, improved device performance, improved device yield, and the like. Accordingly, accurate and precise deposition and etch processes for forming the desired device profiles are required.

Disclosure of Invention

In some embodiments of the present disclosure, a method includes forming a dummy gate over a substrate; forming a pair of gate spacers on opposite sidewalls of the dummy gate; removing the dummy gate to form a trench between the gate spacers; directing a first ion beam to an upper portion of the trench such that a lower portion of the trench is substantially free of the first ion beam incident thereon; moving the substrate relative to the first ion beam during the directing of the first ion beam to the trench; and forming a gate structure in the trench.

Drawings

Some embodiments of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-27 illustrate methods in various stages of fabricating a semiconductor element, according to some embodiments of the present disclosure;

28A-30B illustrate methods in various stages of fabricating a semiconductor element according to some embodiments of the present disclosure;

FIG. 31 is a schematic view of a manufacturing apparatus according to some embodiments of the present disclosure;

FIG. 32 is a flow chart illustrating a method of operating the manufacturing apparatus of FIG. 31 in accordance with some embodiments of the present disclosure;

FIG. 33 is a schematic diagram illustrating operation of the manufacturing apparatus of FIG. 31 during the method of FIG. 31 in accordance with some embodiments of the present disclosure;

FIG. 34 is a schematic diagram illustrating operation of the manufacturing apparatus of FIG. 31 during the method of FIG. 32 in accordance with some embodiments of the present disclosure;

35A-35C are schematic diagrams illustrating operation of the manufacturing apparatus of FIG. 31 during the method of FIG. 32, in accordance with some embodiments of the present disclosure;

FIGS. 36A and 36B are schematic diagrams illustrating operation of the manufacturing apparatus of FIG. 31 during the method of FIG. 32, in accordance with some embodiments of the present disclosure;

FIG. 37 is a flow chart illustrating a method of operating the manufacturing apparatus of FIG. 31 in accordance with some embodiments of the present disclosure;

fig. 38A and 38B are flow diagrams of methods for forming semiconductor elements, according to some embodiments of the present disclosure.

[ notation ] to show

22 cushion layer

24 mask layer

26 photoresist layer

32A groove

32B groove

32C groove

36 spacer layer

37 annealing process

100 manufacturing equipment

120 source

140 grid assembly

141a hole

141b hole

142 grid

142a grid part

142b grid part

142c grid part

144 grid

146 grid

148 bias controller

160 wafer stage

161H high density region

161L Low Density region

180 mechanism

200 manufacturing equipment

305 isolation structure

310 base plate

312 semiconductor fin

314 semiconductor fin

322 dummy dielectric layer

324 dummy gate layer

324A dummy gate

324A-P protrusions

324B dummy gate

324B-P protrusions

324C dummy gate

324R residue

326 first mask

328 second mask

330 protective layer

342 gate spacer

342L lower part

342U upper part

350 source/drain structure

355 Contact Etch Stop Layer (CESL)

360 interlayer dielectric (ILD) layer

370 gate structure

370U part

372 gate dielectric layer

374 work function metal layer

376 filler metal

380 Etch Stop Layer (ESL)

385 interlayer dielectric (ILD) layer

392 contact

394 contact

400 Etch Stop Layer (ESL)

405 an interlayer dielectric (ILD) layer

412 contact

414 contact

3240 side wall

3240A Upper part

3240B lower part

3242 side wall

3246 side wall

A1 first deposition Angle

A2 second deposition Angle

A3 first etch Angle

A4 second etch Angle

I1 first orientation ion

I2 second directed ion

I3 first orientation ion

I4 second directed ion

M1 method

M2 method

M3 method

O1 opening

O2 opening

S102 Block

S104 Block

S106 Block

S108 Block

S109 Block

S112 Block

S114 Block

S116 Block

S118 Block

S119 block

S202 Block

S204 Block

S206 Block

S208 Block

S210 Block

S212 Block

S214 Block

S216 Block

S218 Block

S220 Block

S222 Block

S224 Block

S226 Block

S230 block

S232 square block

S234 Block

S236 Block

S238 block

S240 Block

S242 Block

S244 Block

S246 square block

S248 square block

S250 Square block

S252 Block

S254 Block

S256 Block

S258 block

T1 groove

T2 groove

WF wafer

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Moreover, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Additionally, spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (or elements) or feature (or features) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Examples of elements that may be improved by one or more embodiments of the present application are semiconductor elements. Such devices may be, for example, fin field effect transistor (FinFET) devices. The following disclosure will continue with a FinFET example to illustrate various embodiments of the present application. It will be understood, however, that the application should not be limited to a particular type of element.

The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, a double-patterning or multi-patterning process combines photolithographic and self-aligned processes, allowing for the generation of patterns with pitches that are smaller, for example, than those that could otherwise be obtained using a single, direct light photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the fins may then be patterned using the remaining spacers.

Fig. 1-27 illustrate methods in various stages of fabricating a semiconductor element, according to some embodiments of the present disclosure.

Refer to fig. 1. A wafer WF having a substrate 310 is illustrated. In some embodiments, substrate 310 comprises silicon. Alternatively, substrate 310 may comprise germanium, silicon germanium, gallium arsenide, or other suitable semiconductor materials. Alternatively, the substrate 310 may include an epitaxial layer. For example, the substrate 310 may have an epitaxial layer overlying a bulk semiconductor. Additionally, the substrate 310 may be subjected to strain for performance enhancement. For example, the epitaxial layer may comprise a different semiconductor material than the bulk semiconductor, such as a silicon germanium layer overlying the bulk silicon or a silicon layer overlying the bulk silicon germanium. Such a strained substrate may be formed by Selective Epitaxial Growth (SEG). Further, the substrate 310 may include a Semiconductor On Insulator (SOI) structure. Alternatively, the substrate 310 may include a buried dielectric layer, such as a Buried Oxide (BOX) layer, such as a layer formed by implanted oxygen Separation (SIMOX) techniques, wafer bonding, SEG, or other suitable methods.

A liner layer 22 and a mask layer 24 may be formed on the substrate 310, and then a patterned photoresist layer 26 is formed on the mask layer 24. The liner layer 22 may be a thin film, for example, a film comprising silicon oxide formed using a thermal oxidation process. The pad layer 22 may serve as an adhesion layer between the substrate 310 and the mask layer 24. The liner layer 22 may also serve as an etch stop layer for etching the mask layer 24. In some embodiments, the masking layer 24 is formed of silicon nitride, for example, using Low Pressure Chemical Vapor Deposition (LPCVD). In some other embodiments, the masking layer 24 is formed by thermal silicon nitride, Plasma Enhanced Chemical Vapor Deposition (PECVD), or plasma anodic nitridation. The mask layer 24 may be used as a hard mask during a subsequent photolithography process. In some embodiments, patterned photoresist layer 26 may be formed by, for example: a photoresist layer is deposited over the masking layer 24 by a suitable process, such as a spin-on technique, which may include baking the photoresist layer after coating. The photoresist layer may include a positive type or a negative type of photoresist. For example, the light-blocking layer comprises poly (methyl methacrylate) (PMMA). Subsequently, the photoresist layer is subjected to an exposure process. For example, the photoresist layer is exposed to radiant energy, such as Ultraviolet (UV) radiation, through a mask (reticle or reticle) having a predefined pattern, resulting in the patterned photoresist layer 26 comprising exposed areas of the photoresist layer.

Refer to fig. 2. The mask layer 24, the pad layer 22, and the substrate 310 are patterned. In some embodiments, the mask layer 24 and the liner layer 22 are etched through the photoresist 26, exposing the underlying substrate 310. The exposed substrate 310 is then etched, forming

trenches

32A, 32B, and 32C. The substrate 310

forms semiconductor fins

312 and 314 in the remaining portions between

adjacent trenches

32A, 32B, and 32C. After etching the substrate 310, the photoresist 26 (see fig. 1) is removed. In some embodiments, a cleaning process may be performed to remove the original oxide of the substrate 310. For example, the cleaning process may be performed using dilute Hydrofluoric (HF) acid.

Trench 32A has a width WA, trench 32B has a width WB, and trench 32C has a width WC. In some embodiments, the difference between widths WA and WB is lower than the difference between widths WB and WC. For example, widths WA and WB are substantially the same, and width WC is greater than widths WA and WB. In other words, the trench 32C has a larger lateral size than that of the

trenches

32A and 32B. Herein, the term "substantially the same" indicates that the difference between the widths WA and WB is within 10%.

Refer to fig. 3. The isolation layer 36 is formed over the substrate 310. In some embodiments, the isolation layer 36 substantially fills the trenches 32A-32C. The filling method may be selected from spin coating, Flowable Chemical Vapor Deposition (FCVD), and the like. The isolation layer 36 may comprise a highly flowable material that tends to flow into the trenches 32A-32C so as to substantially fill the trenches 32A-32C.

In some embodiments, the isolation layer 36 comprises spin-on-glass, which may comprise Si-O-N-H. In alternative embodiments, the isolation layer 36 comprises a flowable oxide, which may comprise Si-O-N-H, Si-C-O-N-H, or the like. Highly flowable materials tend (although not necessarily) to have high shrinkage. Thus, the isolation layer 36 may have a high shrinkage when cured, annealed, and/or solidified. In some embodiments, the isolation layer 36 has a shrinkage of greater than about 10%, or between about 10% and about 30%. In other embodiments, the isolation layer 36 has a small shrinkage, e.g., less than about 10%, or less than about 5%, when cured, annealed, and/or solidified.

Refer to fig. 4. An anneal process 37 is performed on the isolation layer 36. The isolation layer 36 solidifies due to the annealing process 37. In an alternative embodiment, the isolation layer 36 is solidified by a curing process separate from the annealing process 37. In some embodiments, the annealing process 37 is performed at a temperature between about 500 ℃ and about 1,200 ℃, although different temperatures may be used. For example, the anneal process 37 may be performed for a period of time between about 30 minutes and about 120 minutes.

Refer to fig. 5. The isolation layer 36 (see fig. 4) is partially removed to form an isolation structure 305 as a Shallow Trench Isolation (STI) between the

semiconductor fins

312 and 314. In some embodiments, a planarization process, such as Chemical Mechanical Polishing (CMP), is performed to remove the isolation layer 36, the mask layer 24, and the liner layer 22 until the top surfaces of the

semiconductor fins

312 and 314 are exposed. Thereafter, an etch-back process is performed to partially remove the isolation layer 36 until the upper portions of the

semiconductor fins

312 and 314 protrude from the top surface of the isolation layer 36. The remaining isolation layer 36 is referred to as an isolation structure 305.

Refer to fig. 6. A dummy dielectric layer 322 is formed over the substrate 310 and covers the

semiconductor fins

312 and 314. Dummy dielectric layer 322 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. Dummy gate layer 324 is formed over dummy dielectric layer 322. Dummy gate layer 324 may be formed over dummy dielectric layer 322 and subsequently planarized, such as by CMP. Dummy gate layer 324 may include polysilicon (poly-Si) or poly silicon germanium (poly-SiGe). In addition, the dummy gate material layer 324 may be doped polysilicon with uniform or non-uniform doping.

A first mask 326 and a second mask 328 may be deposited over dummy gate layer 324. The first mask 326 and the second mask 328 (which are used as hard mask layers during an etching process in a later process) may comprise silicon oxide, silicon nitride and/or silicon oxynitride. The material of the first mask 326 may be different from the material of the second mask 328. For example, the first mask 326 made of silicon oxide may be positioned below the second mask 132 made of silicon nitride.

Referring to fig. 7A and 7B, fig. 7B is a cross-sectional view along line B-B of fig. 7A. Dummy gate layer 324 (see fig. 6) is patterned to form

dummy gates

324A, 324B, and 324C. For example, masks 326 and 328 may be patterned using acceptable photolithography and etching techniques. The pattern of

masks

326 and 328 may be transferred to dummy gate layer 324 (e.g., by using an acceptable etch process) to etch dummy gate layer 324 not covered by

masks

326 and 328 to form

dummy gates

324A, 324B, and 324C. The

dummy gates

324A, 324B, and 324C cover the respective channel areas of the

semiconductor fins

312 and 314. The

dummy gates

324A, 324B, and 324C may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the

semiconductor fins

312 and 314. Dummy dielectric layer 322 and dummy gate layer 324 may include sufficient etch selectivity to the etch process such that dummy dielectric layer 322 remains after dummy gate layer 324 is etched. That is, dummy dielectric layer 322 may include a higher etch resistance to an etchant than dummy gate layer 324. In some embodiments, the

dummy gates

324A, 324B, and 324C are formed by an anisotropic etch, such as a Reactive Ion Etch (RIE) process.

As shown in fig. 7B, after forming dummy gates 324A-324C, a trench T1 is formed between

dummy gates

324A and 324B, and a trench T2 is formed between

dummy gates

324B and 324C, respectively. In some embodiments, the trench T2 has a size greater than the trench T1. For example, the spacing S2 between

dummy gates

324B and 324C is wider than the spacing S1 between

dummy gates

324A and 324B. In other words, the aspect ratio of the trench T2 is lower than that of the trench T1. Herein, the term "aspect ratio" indicates the ratio of the height to the width of the trench. Since the distance between

dummy gates

324A and 324B is less than other regions of the element, spacing S1 may be referred to as a dense region of the element.

In some embodiments,

dummy gates

324A and 324B include protruding portions 324A-P and 324B-P, respectively, exposed to trench T1 after the etching process. This is because the trench T1 has a relatively high aspect ratio, and the etchant used to etch the dummy gate layer 324 is more difficult to flow into the trench T1 than into other wider regions of the device (e.g., trench T2), which results in incomplete patterning of the

dummy gates

324A and 324B. Thus, protruding portions 324A-P and 324B-P are the remaining portions of dummy gate layer 324 due to incomplete removal. In some embodiments, the height of the protruding portions 324A-P and 324B-P is lower than the top surface of the semiconductor fin 312 (drawn in dashed lines).

Referring to fig. 8A and 8B, fig. 8B is a cross-sectional view along line B-B of fig. 8A. A directional deposition process is performed to form a protective layer 330 over the substrate 310. In some embodiments, a protective layer 330 is formed to cover dummy gates 324A-324C and dummy dielectric layer 322. As shown in fig. 8B, however, the protection layer 330 does not coverThe cap protrusion portions 324A-P and 324B-P, and the portion of dummy dielectric layer 322 within trench T1, which will be described in more detail below. In some embodiments, the protective layer 330 may comprise fluorocarbon (e.g., -C-CF)₂) A polymer, or a suitable material that provides sufficient etch selectivity relative to the dummy gates 324A-324C during the directional etch process discussed below.

A directional deposition process is performed using directional ions that are extracted from the plasma and directed at the wafer WF at an oblique angle with respect to the normal direction N (see fig. 31) of the wafer surface, as described in more detail below. For example, an arrow drawn with a dotted line in fig. 8B indicates a direction in which the ion beam is incident on the wafer WF to form the protective layer 330.

FIG. 31 is a schematic diagram of a manufacturing apparatus 100, according to some embodiments of the present disclosure. FIG. 32 is a flow chart of a method M1 of a directional deposition process in accordance with some embodiments of the present disclosure. Refer to fig. 8B, fig. 31, and fig. 32. In some embodiments, the wafer WF may undergo a deposition process in the manufacturing apparatus 100 of fig. 31 and using the method M1 of fig. 32.

Method M1 begins at block S102 where the wafer is placed in a fabrication facility. The manufacturing facility 100 shown in FIG. 31 includes a source 120, a grid assembly 140, a wafer stage 160 disposed about the source 120 and the grid assembly 140, and a mechanism 180. For purposes of illustration, wafer stage 160 is disposed in front of source 120 and grid assembly 140, and grid assembly 140 is disposed between source 120 and wafer stage 160.

In some embodiments, the source 120 is configured to provide at least one ion beam, illustratively including ions to be deposited on a wafer WF positioned on the wafer stage 160. In some embodiments, the source 120 is a plasma source and ions are generated from the plasma source. The grid assembly 140 is configured to direct at least one ion beam provided by the source 120 and deliver the ion beam to a wafer WF positioned on a wafer stage 160. The wafer stage 160 is positioned at a predetermined distance from the grid assembly 140. For example, the wafer stage 160 is positioned in a range of about 0.5cm (centimeters) to about 50cm from the grid assembly 140. The distance between the wafer stage 160 and the grid assembly 140 in fig. 31 is given for illustrative purposes. Various distances between the wafer stage 160 and the grid assembly 140 are within the intended scope of embodiments of the present disclosure.

The method M1 proceeds to block S104 where a first deposition angle is determined. As mentioned above, the directed ions are directed at the wafer WF at an oblique angle with respect to the normal direction N of the wafer surface. Thus, the wafer WF is tilted along the X-axis such that the normal direction N forms a first angle a1 (referred to as a first deposition angle a1, and see fig. 8B) with the directed ions. The deposition angle a1 is greater than 0 and less than about 90 °. For example, wafer stage 160 may be tilted toward grid assembly 140 at an angle ranging from about 0 to about 90, or wafer stage 160 may be tilted away from grid assembly 140 at an angle ranging from about 0 to about 90. The first deposition angle a2 is determined by the aspect ratio of the trench T2. If the first deposition angle a2 is too large, the directional ions may not be able to reach the bottom of the trench T2; if the first deposition angle A2 is too small, directional ions may not be deposited on the sidewalls of the dummy gates 324A-324C.

Fig. 33 is an explanatory diagram illustrating operation of the manufacturing apparatus 100 in fig. 31 during the method M1 in fig. 32. For illustration in fig. 33, each of the dashed rectangles indicates the position of the wafer WF in the view in the X-axis direction. When the wafer stage 160 is rotated in the X-axis direction, the trace of the dotted rectangle is rotated in fig. 33. Fig. 33 further shows that the wafer WF has no offset in the X-axis direction. In other words, the wafer stage 160 can rotate only in the Y-Z plane. The rotational axis of the wafer stage 160 shown in fig. 33 is given for illustrative purposes. It is within the intended scope of embodiments of the present disclosure for the wafer stage 160 to have its respective axis of rotation.

In fig. 33, in some other embodiments, wafer stage 160 does not rotate while wafer WF receives the ion beam. Explained differently, the wafer stage 160 is tilted clockwise at a predetermined angle before the wafer WF starts receiving the ion beam. In some other embodiments, the wafer stage 160 is tilted counterclockwise by a predetermined angle before the wafer WF starts receiving the ion beam. In an alternative embodiment, wafer stage 160 is tilted counterclockwise by a predetermined angle before wafer WF begins to receive the ion beam, and is tilted clockwise by the same predetermined angle before wafer WF receives the ion beam. In some embodiments, the wafer WF does not receive the ion beam as the wafer stage 160 rotates.

Method M1 continues to block S106 where the first directed ions are directed to the wafer. The first directed ion I1 is illustrated in fig. 9B. FIG. 34 is a schematic diagram of operating the manufacturing apparatus 100 of FIG. 31 in accordance with some embodiments of the present disclosure. With respect to the embodiment of fig. 31, like elements in fig. 34 are designated with the same reference numerals for ease of understanding. Refer to fig. 32 and 34. As mentioned above, the source 120 is configured to provide at least one ion beam, including ions to be deposited on the wafer WF, which is positioned on the wafer stage 160 for illustrative purposes. In some embodiments, the source 120 is a plasma source. The ion beam is generated by a source 120. In other words, the ion beam is extracted from the plasma in the source 120. For example, to deposit boron (B), gaseous Boron Fluoride (BF) is used₃) To a source 120. The source 120 employs electrical excitation to form a plasma that may include several ionic species obtained from fractionating source compounds, including the desired species to be deposited (e.g., B)⁺)。

As discussed above, the output and function of source 120 are given for illustrative purposes. The various outputs and functions of source 120 are within the intended scope of embodiments of the present disclosure. For example, in various embodiments, the source 120 provides an ion beam to perform an etching process on the wafer WF to form semiconductor structures having a desired profile on the wafer stage 160.

The grid elements 140 substantially direct the ion beam in the Z-axis direction, which is indicative of the horizontal direction as shown in fig. 31. In some embodiments, grid component 140 includes a number of grids, which include grid 142, grid 144, and grid 146 for purposes of illustration in FIG. 31. Grid 142, grid 144, and grid 146 are disposed with respect to source 120. To illustrate in fig. 31, grid 142 is disposed adjacent source 120, grid 146 is disposed adjacent wafer stage 160, and grid 144 is disposed between grid 142 and grid 146. The amount of grid shown in fig. 31 is given for illustrative purposes. Various amounts of grids in grid assembly 140 are within the intended scope of embodiments of the present disclosure.

In some embodiments, each grid in grid assembly 140 includes grid portions and holes. To illustrate in fig. 31, the grill 142 includes

grill parts

142a, 142b, and 142c separated from each other, a hole 141a disposed between the

grill parts

142a and 142b, and a hole 141b disposed between the grill parts 142b and 142 c. For purposes of illustration in fig. 31,

grids

144 and 146 have the same configuration as grid 142, and thus, the configuration of

grids

144 and 146 is not further detailed herein.

For ease of discussion, fig. 31 shows three grid portions and two holes for each of grid 142, grid 144, and grid 146. The grid portions and the amount of holes in fig. 31 are given for illustrative purposes. Various amounts of grid portions and holes are within the intended scope of embodiments of the present disclosure.

In some embodiments, the grid 142 is configured to be coupled to a positive supply voltage (not shown), and thus the grid 142 is configured to control the potential of the ion beam. In some embodiments, grid 142 is disposed in contact with the plasma as discussed above. Thus, in some embodiments, the grid 142 is referred to as a "curtain". In some embodiments, grid 142 is configured as an electrode that controls the plasma as discussed above. Thus, in some embodiments, grid 142 is also referred to as an "anode.

In some embodiments, the grid 144 is configured to be coupled to a negative supply voltage (not shown), and the grid 144 is configured to direct an ion beam. The ion beam is directed from grid 142 toward grid 144. In some embodiments, the grid 144 is used to accelerate the ion beam according to a negative supply voltage. In some embodiments, grid 144 is referred to as an "accelerator".

In some embodiments, grid 146 is configured to be coupled to ground (not shown), and grid 146 is configured to decelerate an ion beam directed from grid 144. In some embodiments, the grid 146 is referred to as a "retarder". In some other embodiments, the grid 146 is configured to be coupled to an adjustable voltage, as shown in fig. 36A and 36B and discussed below.

To illustrate in fig. 31 and 34, the ion beam travels through the grid 142 via

apertures

141a and 141b, which are arranged between grid portions 142a-142c of the grid 142. Next, the ion beam is accelerated due to the negative voltage applied on the grid 144 and travels through the grid 144 via the holes arranged between the grid portions of the grid 144. Subsequently, the ion beam decelerates due to a ground potential applied on the grid 146 and travels through the grid 146 via the holes arranged between the grid portions of the grid 146. Thus, the ion beam is directed substantially along the Z-axis by the grid assembly 140. In some embodiments, wafer stage 160 is configured to receive wafer WF for performing a process with a directed ion beam.

In some embodiments, the apertures of

grids

142, 144, and 146 are used to optimize confinement of the ion beam while directing the ions extracted from source 120. The hole sizes of

grids

142, 144, and 146 vary from about 0.1mm (millimeters) to about 10 mm. The hole sizes in fig. 31 are given for illustrative purposes. Various sizes of apertures are within the contemplated scope of embodiments of the present disclosure.

In some embodiments, as discussed above, the ion beam is directed by the grid assembly 140 substantially along the Z-axis direction toward the wafer WF held by the wafer stage 160, and thus, the ion beam travels through the apertures of the grid assembly 140 to the wafer WF. Thus, the pattern of the ion beam reaching the wafer WF correlates with the pattern of the apertures of the grid assembly 140. Thus, wafer WF includes high density regions 161H and low density regions 161L associated with the pattern of holes of grid elements 140. There are relatively more ions traveling to the high density region 161H than to the low density region 161L. In other words, the low density region 161L has less arriving ions than the high density region 161H.

In some embodiments, the distribution of high density regions 161H and low density regions 161L on wafer 161 corresponds to the holes of grid elements 140, in relation to the hole size and distance between grid elements 140 and wafer stage 160. The distribution of the high density regions 161H and the low density regions 161L on the wafer 161 shown in fig. 34 is given for illustrative purposes. Various distributions of high density regions 161H and low density regions 161L on the wafer 161 are within the contemplated scope of embodiments of the present disclosure.

For purposes of illustration in fig. 34, the ion beam is directed through a grid assembly 140 and has a small angle from the Z-axis direction. The deviation from the Z-axis of the directed ion beam corresponds to the spacing of

grids

142, 144, and 146 and the distance between grid assembly 140 and wafer stage 160. The deviation from the Z-axis direction of the directed ion beam shown in fig. 34 is given for illustrative purposes. Various deviations from the Z-axis direction of the directed ion beam are within the intended scope of embodiments of the present disclosure.

In some approaches, the wafer stage carrying the wafer is still maintained and is not movable and rotatable while the distribution is performed on the wafer. As such, areas on the wafer having non-uniform processing include high density areas 161H and low density areas 161L as discussed above for the purpose illustrated in fig. 34. Embodiments of the present disclosure solve the problems in the prior art methods by controlling (shifting) the position of the high-density regions 161H and the low-density regions 161L over time, as described in more detail below.

In some embodiments, method M1 proceeds to block S108 where the wafer is moved relative to the grid assembly as the first directional ions are incident on the wafer. Fig. 35A-35C are schematic diagrams illustrating operation of the manufacturing apparatus of fig. 31 during method M1 of fig. 32, according to some embodiments of the present disclosure. Refer to fig. 34 and fig. 35A to 35C. In some embodiments, the wafer stage 160 may be movable in a first direction (e.g., an X direction), a second direction (e.g., a Y direction), or a combination thereof. As the wafer stage 160 moves, the wafer WF positioned on the wafer stage 160 may also move in the X-axis direction (see fig. 35B), the Y-axis direction (see fig. 35A), or a combination thereof. In some embodiments, the wafer stage 160 may be moved in both the X-axis and Y-axis directions (such as the circular movement shown in fig. 35C).

In some embodiments, the wafer stage 160 is coupled to a mechanism 180 that assists in the movement of the wafer stage 160. To illustrate in fig. 34, the wafer WF is moved and/or rotated with the assistance of the mechanism 180. In some embodiments, the mechanism 180 is used to assist the movement of the wafer stage 160 through a linear motion system. For example, the mechanism 180 includes a two-dimensional linear motor system that assists the wafer stage 160 in moving in the X-axis direction and the Y-axis direction. In some other embodiments, the mechanism 180 is used to assist the movement of the wafer stage 160 by a ball screw system. In some further embodiments, the mechanism 180 is used to assist the wafer stage movement through a circular or linear gear system. The mechanism 180 discussed above is for illustrative purposes, and various mechanisms 180 are within the intended scope of embodiments of the present disclosure. For example, the mechanism includes a combination of a linear motor system, a ball screw, and a circular gear to assist in the movement and rotation of the wafer stage 160.

In some other embodiments, grid assembly 140 may be movable in a first direction (X-direction), a second direction (Y-direction), a third direction (Z-direction), or a combination thereof. Wafer stage 160 may thus move or be stationary as grid assembly 140 moves. Embodiments are within the scope of the present disclosure as long as wafer WF moves relative to grid assembly 140.

Compared to the above-mentioned method, the wafer stage 160 carrying the wafer WF in the embodiment of the present disclosure may move while keeping the notches of the wafer WF in the same orientation (see fig. 35A to 35C), and thus, have a more uniform ion distribution on the wafer WF. For example, with the wafer stage 160 being movable and/or rotatable, the location of the low density region 161L is spatially moved to the location of the high density region 161H as discussed above. Thereby, the low density region 161L can be moved to a position where more ions are received and further processed, so that the wafer WF can be uniformly processed.

For illustration in fig. 35A, each dashed circle indicates a corresponding position of the wafer WF in the Z-axis direction view in fig. 34. When the wafer stage 160 moves in the Y-axis direction, the trace of the dotted circle moves up and down in fig. 35A. Fig. 35A further shows that the wafer WF has no offset in the X-axis direction or the Z-axis direction. In other words, the wafer stage 160 is movable only in the Y-axis direction in fig. 34. In some embodiments, the wafer stage 160 carrying the wafer WF is continuously and linearly moved back and forth in the Y-axis direction with respect to the wafer WF to be processed by the ion beam, and thus, the movement of the wafer stage 160 is referred to as "Y-axis linear scanning" in some embodiments. In some embodiments, the distance of movement of wafer stage 160 is shorter, equal, or longer than the distance between holes arranged in the grid portion of grid assembly 140 as discussed above.

For illustration in fig. 35B, each dashed circle indicates a corresponding position of the wafer WF in the Z-axis direction view in fig. 34. When the wafer stage 160 moves in the X-axis direction, the trace of the dotted circle moves left and right in fig. 35B. Fig. 35B further shows that the wafer WF has no offset in the Y-axis direction or the Z-axis direction. In other words, the wafer stage 160 is movable only in the X-axis direction in fig. 34. In some embodiments, the wafer stage 160 carrying the wafer WF is continuously and linearly moved back and forth in the X-axis direction with respect to the wafer WF to be processed by the ion beam, and thus, the movement of the wafer stage 160 is referred to as "X-axis linear scanning" in some embodiments. In some embodiments, the distance of movement of wafer stage 160 is shorter, equal, or longer than the distance between holes arranged in the grid portion of grid assembly 140 as discussed above.

For illustration in fig. 35C, each dashed circle indicates the position of the wafer WF in the Z-axis direction view in fig. 34. The trace of the dashed circle in fig. 35C further shows that the wafer WF has no offset in the Z-axis direction. In other words, the wafer stage 160 is movable only in the X-axis direction, the Y-axis direction, or a combination thereof. In some embodiments, the wafer stage 160 carrying the wafer WF moves circularly in the XY plane, off the Z axis for illustration purposes, with respect to the wafer WF to be processed by the ion beam, and thus, movement of the wafer stage 160 is referred to as "off-axis wafer rotation" in some embodiments. In some embodiments, wafer stage 160 moves circularly in a circle having a radius that is shorter, equal, or longer than the inter-aperture distance arranged in the grid portion of grid element 140 discussed above.

In some embodiments, in the semiconductor element, a longitudinal direction of the gate structure is perpendicular to a longitudinal direction of the semiconductor fin. Thus, the term "X-axis" discussed in fig. 35A-35C may be considered to be aligned with the longitudinal direction of the gate structure, such as the longitudinal direction of

dummy gates

324A, 324B, and 324C. On the other hand, the term "Y-axis" may be considered to be aligned with the longitudinal direction of the semiconductor fins, such as the longitudinal direction of

semiconductor fins

312 and 314. Thus, in fig. 35A, the wafer stage 160 carrying the wafer WF may be considered to move along the longitudinal direction of the semiconductor fins, but not along the longitudinal direction of the gate structures. Similarly, in fig. 35B, the wafer stage 160 carrying the wafer WF may be considered to move along the longitudinal direction of the gate structure, but not along the longitudinal direction of the semiconductor fins.

For purposes of illustration, the above movements, including linear, circular, and/or rotational movements, are shown in the respective embodiments. The above movements are given for illustrative purposes and can be performed independently or in combination. Further, the above configuration of the manufacturing apparatus 100 is given for the purpose of illustration. Various configurations of the manufacturing apparatus 100 are within the contemplated scope of embodiments of the present disclosure. For example, in various embodiments, the manufacturing apparatus 100 or grid assembly 140 further includes a bias controller 148 to bias the grid portion of the grid 146, as will be discussed below with reference to fig. 36A-36B.

In some other embodiments, method M1 proceeds to block S109 where the bias voltage of the grid portion of the grid is tuned when the first directed ions are incident on the wafer. Fig. 36A and 36B are schematic diagrams of a manufacturing apparatus 200, according to various embodiments of the present disclosure. With respect to the embodiment of fig. 31, like elements in fig. 36A and 36B are designated with the same reference numerals for ease of understanding.

In some embodiments, grid assembly 140 further includes a bias controller 148. The bias controller 148 is used to bias the grid assembly 140. In some embodiments, the bias controller 148 is configured to provide a bias voltage on every two adjacent portions of the grid portion. In some embodiments, the bias controller 148 is configured to provide an Alternating Current (AC) bias voltage on each two adjacent portions of the grid portion. For convenience of explanation, only one bias controller 148 is illustrated in fig. 36A and 36B. In some embodiments, the bias controller 148 is configured to provide an adjustable voltage on every two adjacent portions of the grid portion. For illustration in fig. 36A and 36B, a bias controller 148 is used to control the bias on the grid 146.

The construction discussed above in fig. 36A and 36B is given for illustrative purposes. Various configurations of grid assembly 140 or manufacturing apparatus 200 are within the intended scope of embodiments of the present disclosure. In other words, for convenience of explanation, only one bias controller 148 is illustrated and is constructed as in fig. 36A and 36B. However, those skilled in the art will appreciate that various quantities and configurations of the bias controller 148 are within the intended scope of the embodiments of the present disclosure. For example, there are two bias controllers 148, each bias controller providing bias to two adjacent portions of the grid portion of the grid 146 as shown in fig. 36A and 36B.

For purposes of illustration in fig. 36A and 36B, the bias controller 148 is coupled to the grid 146. The bias controller 148 provides an alternating bias voltage on each two adjacent grid sections of the grid 146. As shown in fig. 36A, the ion beam in the upper side of the grid 146 is deviated due to the potential difference on the grid portion of the grid 146. The ion beam tends to be directed toward the grid portion having the lower potential. Correspondingly, the ion beam in the lower side of the grid 146 is also deflected due to the potential difference across the grid portion of the grid 146.

As shown in fig. 36B, the ion beam in the upper side of the grid 146 is deviated due to the potential difference on the grid portion of the grid 146. The ion beam tends to be directed toward the grid portion having the lower potential. Correspondingly, the ion beam in the lower side of the grid 146 is also deflected due to the potential difference across the grid portion of the grid 146.

The potential distribution of grid assembly 140 discussed above is given for illustrative purposes. Various distributions of the potential on grid element 140 are within the intended scope of embodiments of the present disclosure.

Similarly, the bias controller 148 controls/tunes the potential of the grid portion (see fig. 36A and 36B), and thus, has a more uniform ion distribution on the wafer WF. For example, as the potential of the grid portion changes periodically, the portion of the low-density region 161L as discussed above moves spatially to the portion of the high-density region 161H. Thus, the low density region 161L can be moved to a position to receive and further process more ions, so that the wafer WF can be uniformly processed.

The method M2 proceeds to block S112 where the source stops providing the first directed ions. In some embodiments, the source 120 stops the deposition process when the first directional ions I1 are deposited on one side of the sidewalls of the dummy gates 324A-324C to form a portion of the protection layer 320, and there are no ions generated by the source 120.

The method M2 proceeds to block S114 where a second deposition angle A2 is determined. In some embodiments, the first deposition angle a1 and the second deposition angle a2 have the same value but opposite directions. That is, A2 is substantially equal to-A1. In some embodiments, as shown in fig. 33, the wafer WF may be tilted again such that the normal N and subsequently formed second directional ions I2 form a second deposition angle a 2. In some other embodiments, as shown in fig. 34, the wafer WF may be rotated about 180 degrees along the Z-axis direction such that the normal N and the subsequently formed second directional ions I2 form a second deposition angle a 2.

Method M2 proceeds to block S116 where second directed ions are directed to the wafer. A second directional ion I2 is illustrated in fig. 8B. In some embodiments, method M1 proceeds to block S118 where the wafer is moved relative to the grid assembly as the second directed ions are incident on the wafer. In some other embodiments, method M1 proceeds to block S119 where the bias voltage of the grid portion of the grid is tuned when the second directed ions are incident on the wafer. Since the details of blocks S118 and S119 are similar to those described in blocks 108 and 109 of method M1, the detailed description thereof is not repeated herein.

As mentioned above, the trench T1 is relatively narrower compared to other regions of the wafer WF (e.g., the trench T2). As such, the

dummy gates

324A and 324B may block the incident ion beam such that the first and second directional ions I1 and I2 may not reach the bottom of the trench T1. In other words, the bottom of the trench T1 is shielded by the

dummy gates

324A and 324B. As an example shown in fig. 9B, the first and second directional ions I1 and I2 may not reach the protruding portions 324A-P and 324B-P, and the portion of the dummy dielectric layer 322 within the trench T1. Accordingly, because the incident ion beam does not reach this area to cause deposition, the protruding portions 324A-P and 324B-P and the portion of the dummy dielectric layer 322 within the trench T1 are not covered by the protection layer 330. In other words, the directional deposition process may also be referred to as a selective deposition process.

In some embodiments of the present disclosure, a directional deposition process is performed by applying first directional ions I1 and second directional ions I2 to direct such directional ions to the wafer about an oblique angle perpendicular to the wafer surface. The first directional ion I1 and the second directional ion I2 may be blocked by structures on the wafer so that deposition will not occur at certain areas on the wafer. Thus, selective deposition can be achieved.

Referring to fig. 9A and 9B, fig. 9B is a cross-sectional view along line B-B of fig. 9A. An etching process is performed to remove the protruding portions 324A-P and 324B-P of the

dummy gates

324A and 324B (see fig. 8A and 8B). In some embodiments, the protection layer 330 has a higher resistance to an etchant of an etching process so as to protect an underlying layer covered by the protection layer 330. As mentioned above, the portions of the protruding portions 324A-P and 324B-P and the dummy dielectric layer 322 in the trench T1 are not covered by the protection layer 330, so that the exposed portions 324A-P and 324B-P and the portion of the dummy dielectric layer 322 in the trench T1 can be removed by the etchant of the etching process. After the etching process, a portion of the isolation structure 305 is exposed by the trench T1, while other portions of the isolation structure 305 remain covered by the dummy dielectric layer 322. In some embodiments, the etching process described in fig. 9A and 9B is an isotropic etching process, such as a wet etch.

Reference is made to fig. 9C, where fig. 9C has a cross-section as in fig. 9B. In some other embodiments,

dummy gates

324A and 324B may be overetched during etching of raised portions 324A-P and 324B-P (see fig. 8A and 8B), and the resulting structure is illustrated in fig. 9C. A sidewall 3240 of dummy gate 324A facing dummy gate 324B has an upper portion 3240A and a lower portion 3240B. After the etching process, the upper portion 3240A of the sidewall 3240 is substantially straight and perpendicular to the substrate 310, since this upper portion is protected by the protection layer 330 during the etching process. However, due to the etching process, the lower portion 3240B of the sidewall 3240 has a concave surface. On the other hand, after the etching process, the sidewall 3242 of the dummy gate 324A facing away from the dummy gate 324B is completely straight and perpendicular to the substrate 310 because the sidewall 3242 is protected by the protection layer 330 during the etching process. In other words, dummy gate 324A includes an upper portion and a lower portion below the upper portion, wherein the minimum width of the upper portion is greater than the width of the lower portion. Thus, sidewalls 3240 and 3242 of dummy gate 324A have an asymmetric profile. Similarly, dummy gate 324B has a sidewall 3244 facing dummy gate 324A and a sidewall 3246 facing away from dummy gate 324A. Sidewalls 3244 and 3246 of dummy gate 324B have similar characteristics to sidewalls 3240 and 3242 of dummy gate 324A, and thus the relevant structural details will not be repeated later. Opposing sidewalls of dummy gate 324C have substantially symmetrical profiles.

In some embodiments, because the raised portions 324A-P and 324B-P are formed in dense areas of the wafer WF, the distance between the raised portions 324A-P and 324B-P may be too tight to cause shorting problems in subsequent processes. Accordingly, a directional deposition process is performed to form a protective layer that selectively covers some areas of the wafer WF while exposing the protruding portions 324A-P and 324B-P, and thus an etching process may be performed to selectively remove the undesired protruding portions 324A-P and 324B-P while leaving other areas of the wafer WF substantially intact.

Refer to fig. 10. Protection layer 330 is removed to expose dummy gates 324A-324C and dummy dielectric layer 322. In some embodiments, the protection layer 330 may be removed by a suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a hydrofluoric acid (dilute HF) solution is used during the process of removing the protection layer 330. The above etchants for removing the protective layer 330 are given for illustrative purposes. Various etchants for removing the protective layer 170 are within the intended scope of embodiments of the present disclosure.

Refer to fig. 11. Portions of the dummy dielectric layer 322 not covered by the dummy gates 324A-324C are removed to expose the

semiconductor fins

312 and 314. Dummy dielectric layer 322 may be removed by a suitable process, such as a dry etch process, a wet etch process, a multi-step etch process, or combinations thereof.

Refer to fig. 12. A plurality of gate spacers 342 are formed on opposing sidewalls of dummy gates 324A-324C. The gate spacers 342 may comprise a dielectric material, such as SiO₂、Si₃N₄、SiO_xN_ySiC, SiCN film, SiOC, SiOCN film, and/or combinations thereof. In some embodiments, the gate spacer 342 comprises multiple layers, such as a main spacer, a liner layer, and the like. In some embodiments, for example, gate spacers 342 may be formed by depositing a spacer blanket layer over substrate 310 and then an etch process to remove horizontal portions of the spacers, and the portions of the spacers remaining on the sidewalls of dummy gates 324A-324C are referred to as gate spacers 342. In some embodiments, the gate spacers 342 may be formed by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, or other suitable processes.

Refer to fig. 13. A plurality of source/drain structures 350 are formed over the substrate 310. For example,

semiconductor fins

312 and 314 are partially removed by a suitable process, such as etching. Thereafter, a plurality of source/drain structures 350 are formed over the remaining

semiconductor fins

312 and 314, respectively. The source/drain structure 350 may be formed by performing an epitaxial growth process that provides an epitaxial material over the

semiconductor fins

312 and 314. In various embodiments, source/drain structure 350 may comprise Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material.

Referring to fig. 14A and 14B, fig. 14B is a cross-sectional view along line B-B of fig. 14A. A Contact Etch Stop Layer (CESL)355 and an interlayer dielectric (ILD) layer 360 are formed. For example, a Contact Etch Stop Layer (CESL)355 is blanket formed over the structure shown in fig. 13, and subsequently, an interlayer dielectric (ILD) layer 360 is formed over the CESL 355. Thereafter, a CMP process may optionally be performed to remove excess material of ILD layer 360 and CESL355 to expose dummy gates 324A-324C. In some embodiments, a CMP process may planarize the top surface of ILD layer 360 and the top surfaces of dummy gates 324A-324C, gate spacers 342, and CESL 355. CESL355 may be a dielectric layer comprising silicon nitride, silicon oxynitride, or other suitable material. CESL355 may be formed using, for example, plasma enhanced CVD, low pressure CVD, ALD, or other suitable techniques. ILD layer 360 may comprise a different material than CESL 355. In some embodiments, the ILD layer 360 may comprise silicon oxide, silicon nitride, silicon oxynitride, Tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and/or other suitable dielectric materials. Examples of low dielectric constant dielectric materials include, but are not limited to, Fluorinated Silicon Glass (FSG), carbon-doped silicon oxide, amorphous carbon fluoride, parylene, bis-benzocyclobutene (BCB), or polyimide. ILD layer 360 may be formed using, for example, CVD, ALD, spin-on-glass (SOG), or other suitable techniques.

Reference is made to fig. 15, where fig. 15 has the same cross-sectional location as fig. 14B. Dummy dielectric layer 322 and

dummy gates

324A, 324B, and 324C are removed such that a gate trench TG is formed between a pair of gate spacers 342. In some embodiments, dummy dielectric layer 322 and

dummy gates

324A, 324B, and 324C may be removed by a suitable process, such as dry etching, wet etching, or a combination thereof.

Refer to fig. 16. A directional etch process is performed to round the corners of the gate spacers 342. The directional etch process may be performed using, for example, the

fabrication apparatuses

100 and 200 as discussed in fig. 31 and 33-36B. The arrow with the broken line in fig. 16 indicates the direction in which the ion beam is incident on the wafer WF. More specifically, the directed ions are directed at the wafer WF at an oblique angle with respect to the normal to the wafer surface. In some embodiments, the ion beam may be directed to the upper portion 342U of the gate spacer 342 so as to partially remove the material of the upper portion 342U of the gate spacer 342, which in turn will round the corners of the upper portion 342U of the gate spacer 342. On the other hand, as shown in fig. 16, the upper portion 342U of the gate spacer 342 also blocks the ion beam so that the ion beam does not reach the lower portion 342L of the gate spacer 342, and thus the etching process will not remove material of the lower portion 342L of the gate spacer 342. In other words, the lower portion 342L of the gate spacer 342 is shielded by the upper portion 342U of the gate spacer 342 to prevent it from being etched.

After the etch process, the gate spacers 342 have rounded top corners. In addition, the gate trench TG is enlarged due to the etching process. However, because the etch process is performed to partially remove the upper portion 342U of the gate spacer 342 while keeping the lower portion 342L of the gate spacer 342 substantially intact, the top of the gate trench TG has a width that is greater than the width of the bottom of the gate trench TG. The upper portion 342U is thinner than the lower portion 342L. In other words, the gate trench TG tapers toward the semiconductor fin 312. Further, the gate spacer 342 protrudes facing the sidewall of the trench TG. In some embodiments, the top 342U has a curved sidewall that contacts a gate structure (e.g., gate structure 370 in fig. 19) formed in a later step, and has a straight sidewall opposite the curved sidewall.

In some embodiments of the present disclosure, a directional etch process may be used to partially remove the gate spacers in order to enlarge the width of the gate trenches between the gate spacers, which will improve gap filling in later operations.

FIG. 37 is a flowchart of a method M2 of a directional etch process, according to some embodiments of the present disclosure. Refer to fig. 16, 31, and 37. The method M2 proceeds to block S102 where the wafer is placed in a fabrication facility. The method M2 proceeds to block S104 where a first etch angle is determined. A first etch angle a3 is illustrated in fig. 16. In addition, the first etching angle a3 is determined by the depth-to-width ratio of the gate trench TG. If the first etch angle a3 is too large, the directional ions may not etch the gate spacers 342 to the desired profile; if the first etching angle a3 is too small, the directional ions may cause the bottom of the gate trench TG to be etched. Method M2 proceeds to block S106 where the first directional ions are directed to wafer WF. The first directional ion I3 is illustrated in fig. 16. In some embodiments, method M2 proceeds to block S108, where the wafer is moved relative to the grid assembly as the first directed ions are incident on the wafer. In some other embodiments, method M2 proceeds to block S109 where the bias voltage of the grid portion of the grid is tuned when the first directed ions are incident on the wafer. Since the details of blocks S102, S104, S106, S108, and S109 are described in method M1, the detailed description thereof is not repeated herein.

The method M2 proceeds to block S112 where the source stops providing the first directed ions. In some embodiments, the source 120 stops the deposition process when the first directional ion I3 etches the gate spacer 342 on the left side in fig. 16, and there are no ions generated by the source 120.

The method M2 proceeds to block S114 where a second etch angle A4 is determined. In some embodiments, the first etch angle A3 and the second etch angle a4 have the same value but opposite directions. That is, A4 is substantially equal to-A3. In some embodiments, as shown in fig. 33, the wafer WF may be tilted again such that the second etching ions I4 formed normal N and below form a second deposition angle a 4. In some other embodiments, as shown in fig. 34, the wafer WF may be rotated about 180 degrees along the Z-axis direction such that the normal N and the subsequently formed second directional ions I4 form a second deposition angle a 4.

Method M2 proceeds to block S116 where second directed ions are directed to the wafer. A second directed ion I4 is illustrated in fig. 16. In some embodiments, method M2 proceeds to block S118 where the wafer is moved relative to the grid assembly as the second directed ions are incident on the wafer. In some other embodiments, method M3 proceeds to block S119 where the bias voltage of the grid portion of the grid is tuned when the second directed ions are incident on the wafer. Since the details of blocks S118 and S119 are similar to those described in blocks S108 and 109 of method M1, the detailed description thereof is not repeated herein.

Refer to fig. 17. Gate dielectric layer 372 on gateA pole trench TG is formed in and over ILD layer 360. The gate dielectric layer 372 may comprise a high-k dielectric, such as TiO₂、HfZrO、Ta₂O₃、 HfSiO₄、ZrO₂、ZrSiO₂、LaO、AlO、ZrO、TiO、Ta₂O₅、Y₂O₃、SrTiO₃(STO)、 BaTiO₃(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、 HfTiO、(Ba,Sr)TiO₃(BST)、Al₂O₃、Si₃N₄Oxynitride (SiON), combinations thereof, or other suitable materials.

Refer to fig. 18. A directional etching process is performed to etch back the gate dielectric layer 372. The directional etch process may be performed using the method M2 in fig. 37 using, for example, the

manufacturing apparatus

100 and 200 discussed in fig. 31 and 33-36B. The arrow with the broken line in fig. 18 indicates the direction in which the ion beam is incident on the wafer WF. In more detail, the directed ions are directed at the wafer WF at an oblique angle with respect to the normal to the wafer surface. In some embodiments, an ion beam may be directed to an upper portion of the dielectric layer 372 (see fig. 17) so as to remove the upper portion of the dielectric layer 372 to expose the upper portion 342U of the gate spacer 342 and the ILD layer 360. On the other hand, as shown in fig. 18, the upper portion 342U of the gate spacer 342 also blocks the ion beam so that the ion beam does not reach the lower portion of the gate dielectric 372, and thus the etching process will not remove material of the lower portion of the gate dielectric 372. In other words, the lower portion of the gate dielectric layer 372 is shielded by the upper portion 342U of the gate spacer 342 from being etched. In fig. 18, the gate dielectric layer 372 has a lower height than the height of the gate spacers 342. In addition, the top of the gate dielectric layer 372 tapers away from the substrate. In some embodiments, the gate dielectric layer 372 has a height H1 and the portion of the gate spacer 342 above the semiconductor fin 312 has a height H2, wherein H1/H2 is greater than about 0.5 and less than 1. If H1/H2 is less than about 0.5, the source/drain structure 350 and subsequently formed gate may have shorting problems.

In some embodiments of the present disclosure, a directional etch process may be used to etch back the gate dielectric layer without an additional mask, which will reduce processing time and further reduce cost.

Refer to fig. 19. A work function metal layer 374 and a fill metal 376 are formed in the gate trench TG (see fig. 18). The workfunction metal layer 374 and the fill metal 376 are formed by depositing a workfunction material and a gate electrode layer in the gate trench TG and over the ILD layer 360, and then performing a CMP process to remove excess workfunction material and gate electrode layer until the ILD layer 360 is exposed. The gate dielectric layer 372, the work function metal layer 374, and the fill metal 376 may be collectively referred to as a gate structure 370. As gate dielectric layer 372 is partially removed, a subsequently formed work function metal layer 374 contacts gate dielectric layer 372 and upper portion 342U of gate spacer 342. In addition, a work function metal layer 374 covers the top of the gate dielectric layer 372.

As discussed above with respect to fig. 16. Because the gate trench TG is enlarged by the directional etching process, the gate structure 370 has a tapered profile due to the enlargement of the gate trench TG. On the other hand, the widest width of the fill metal 376 (e.g., portion 370U in fig. 19) is larger than the widest width of the gate dielectric 372 along the longitudinal direction of the semiconductor fin 312. The gate structure 370 contacts the curved sidewalls of the upper portion 342U of the gate spacer 342. The work function metal layer 374 is closer to the straight sidewalls of the gate spacer 342 than the gate dielectric 372.

The work function metal layer 374 may include an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi₂、MoSi₂、TaSi₂、NiSi₂WCN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include a plurality of layers. In some embodiments, the fill metal 376 may include tungsten (W). In some other embodiments, the fill metal 376 includes aluminum (Al), copper (Cu), or other suitable conductive material.

Refer to fig. 20. An Etch Stop Layer (ESL)380 and an inter-layer dielectric (ILD) layer 385 are deposited over ILD layer 360. The ESL 380 may be formed using, for example, plasma enhanced CVD, low pressure CVD, ALD, or other suitable techniques. ILD layer 385 may comprise a different material than CESL 380. ILD layer 385 may be formed using, for example, CVD, ALD, spin-on-glass (SOG), or other suitable techniques. In some embodiments, ESL 380 and ILD layer 385 are similar to CESL355 and ILD layer 360, respectively. Accordingly, the relevant structural details will not be repeated hereinafter. The ESL 380 is in contact with the fill metal 376, the work function metal layer 374, and the gate spacer 342, but is separated from the gate dielectric layer 372.

Refer to fig. 21. ILD layer 385, ESL 380, ILD layer 360, and CESL355 are etched to form openings O1 and O2. Accordingly, opening O1 exposes gate structure 370, and opening O2 exposes source/drain structure 350. The openings O1 and O2 may be formed simultaneously in the same process or in separate processes. The openings may be formed using acceptable photolithography and etching techniques.

Refer to fig. 22. A directional etch process is performed to round the corners of ILD layer 385 to enlarge openings O1 and O2. The directional etch process may be performed using, for example, the

manufacturing equipment

100 and 200 as discussed in fig. 31 and 33-37. The arrow with a broken line in fig. 22 indicates the direction in which the ion beam is incident on the wafer WF. In more detail, the directional ions are directed to the wafer WF at an oblique angle relative to the normal to the wafer surface. In some embodiments, the ion beam may be directed to an upper portion of ILD layer 385 to partially remove material of upper ILD layer 385, which in turn will round the corners of upper ILD layer 385. On the other hand, as shown in fig. 22, upper ILD layer 385 also blocks the ion beam so that the ion beam does not reach lower ILD layer 385, and thus the etch process will not remove material of lower ILD layer 385. In other words, a lower portion of ILD layer 385 is masked by upper ILD layer 385 to prevent etching. ILD layer 385 has rounded top corners after the etch process. Thus, the openings O1 and O2 are enlarged due to the etching process, which will improve the gap filling in the subsequent steps.

Refer to fig. 23.

Contacts

392 and 394 are formed in openings O1 and O2 (see fig. 22), respectively. In some embodiments, each of

contacts

392 and 394 can include a pad and a conductive material. For example, a liner (such as a diffusion barrier layer, an adhesion layer, or the like) and a conductive material are formed in the openings O1 and O2. In some embodiments, the liner may comprise titanium, titanium nitride, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of ILD layer 385. The remaining pad and conductive

material form contacts

392 and 394 in openings O1 and O2, respectively. An anneal process may be performed to form silicide at the interface between the source/drain structures 350 and the contacts 384, respectively. Contact 394 is physically and electrically coupled to source/drain structure 350 and contact 392 is physically and electrically coupled to gate structure 370. In fig. 23, each of

contacts

392 and 394 includes a top portion having curved (convex) sidewalls.

Refer to fig. 24. An Etch Stop Layer (ESL)400 and an inter-layer dielectric (ILD) layer 405 are deposited over ILD layer 385. In some embodiments, ESL 400 and ILD layer 405 are similar to CESL355 and ILD layer 360, respectively. Accordingly, the relevant structural details will not be repeated hereinafter.

Refer to fig. 25. ILD layer 405 and ESL 400 are etched to form openings O3 and O4. Accordingly, opening O3 exposes contact 392, and opening O4 exposes contact 394. The openings O3 and O4 may be formed using acceptable photolithography and etching techniques.

Refer to fig. 26. A directional etch process is performed to round the corners of ILD layer 405 to enlarge openings O3 and O4. The directional etch process is similar to that described in fig. 22, and therefore relevant details will not be repeated later.

Refer to fig. 27.

Contacts

412 and 414 are formed in openings O3 and O4 (see fig. 26), respectively. Accordingly, contact 414 is physically and electrically coupled to contact 394, and contact 412 is physically and electrically coupled to contact 392. In some embodiments,

contacts

412 and 414 are similar to

contacts

392 and 394, and thus, relevant structural details will not be repeated later.

Figures 28A-30B illustrate methods in various stages of fabricating a semiconductor element, according to some embodiments of the present disclosure.

Referring to fig. 28A and 28B, fig. 28A is a cross-sectional view along line B-B of fig. 28A. Fig. 28A is similar to fig. 4, and the difference between fig. 28 and fig. 4 is that the semiconductor fin 314 in fig. 28A is bent due to the annealing process. As discussed above with respect to fig. 4, when the isolation layer 36 is made of a flowable material, the isolation layer 36 may shrink due to the annealing process 37. However, because trench 32C is wider than trench 32B, the amount of isolation layer 36 within trench 32C is greater than the amount of isolation layer 36 within trench 32B, which results in greater shrinkage of isolation layer 36 within trench 32C than within trench 32B. Thus, because the tensile force of isolation layer 36 within trench 32C is greater than the tensile force of isolation layer 36 within trench 32B, the unbalanced shrinkage of isolation layer 36 on opposite sides of semiconductor fin 314 may cause semiconductor fin 314 to bend (or bow). On the other hand, because

trenches

32A and 32B have substantially the same size, the amount of isolation layer 36 on opposite sides of semiconductor fin 314 is substantially the same, which results in substantially the same shrinkage of isolation layer 36 within

trenches

32A and 32B. As such, the curvature of the semiconductor fin 312 may be less severe than the curvature of the semiconductor fin 314.

Referring to fig. 29A and 29B, fig. 29A is a cross-sectional view along line B-B of fig. 29A. Fig. 29A is similar to fig. 7A, and the difference between fig. 29A and 7A is that after forming dummy gates 324A-324C, a residue 324R of dummy gate layer 324 (see fig. 3) remains on one side of the bent semiconductor fin 314. As mentioned above, because dummy dielectric layer 322 is etch resistant to the etchant that etches dummy gate layer 324, dummy dielectric layer 322 may serve as a mask to protect the portion of dummy gate layer 324 vertically below bent semiconductor fin 314 from being etched. A portion of dummy gate layer 324 remains under bent semiconductor fin 314, referred to as a residue 324R of dummy gate layer 324.

Referring to fig. 30A and 30B, fig. 30A is a cross-sectional view along line B-B of fig. 30A. A directional etch process is performed to remove the residue 324R on the sidewalls of the bent semiconductor fin 314 (see fig. 29A and 29B). The directional etch process may be performed using the

manufacturing apparatus

100 and 200, such as discussed in fig. 31 and 33-37. The arrow with the broken line in fig. 30B indicates the direction in which the ion beam is incident on the wafer WF. In more detail, the directed ions are directed to the wafer WF at an oblique angle with respect to the normal to the wafer surface.

FIGS. 38A and 38B illustrate a method M3 of forming a memory element, according to some embodiments. While method M3 is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited by the illustrated ordering or acts. Thus, in some embodiments, the actions may be performed in a different order than shown, and/or may be performed concurrently. Additionally, in some embodiments, illustrated acts or events may be sub-divided into multiple acts or events, which may be performed separately or concurrently with other acts or sub-acts. In some embodiments, some acts or events shown may be omitted, and other acts or events not shown may be included.

At block S202, a liner layer, a mask layer, and a patterned photoresist layer are formed over a substrate. Fig. 1 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S202.

At block S204, the mask layer, the liner layer, and the substrate are patterned to form semiconductor fins. Fig. 2 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S204.

At block S206, an isolation layer is formed over the substrate. Fig. 3 illustrates a cross-sectional view of some embodiments corresponding to the actions in block S206.

At block S208, an annealing process is performed on the substrate. Fig. 4, 28A, and 28B illustrate cross-sectional views of some embodiments corresponding to the acts in block S208.

At block 210, the isolation layer is partially removed to form an isolation structure. Fig. 5 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S210.

At block S212, a dummy dielectric layer and a dummy gate layer are formed over the substrate. Fig. 6 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S212.

At block S214, the dummy gate layer is patterned to form a dummy gate. Fig. 7A, 7B, 29A, and 29B illustrate cross-sectional views of some embodiments corresponding to the actions in block S214.

At block S216, a directional etch process is performed to remove residues on the sidewalls of the semiconductor fins. Fig. 30A and 30B illustrate cross-sectional views of some embodiments corresponding to the acts in block S216.

At block S218, a directional deposition process is performed to form a protective layer over the substrate. Fig. 8A and 8B illustrate cross-sectional views of some embodiments corresponding to the acts in block S218.

At block S220, an etch process is performed to remove the protruding portion of the dummy gate. Fig. 9A-9C illustrate cross-sectional views of some embodiments corresponding to the acts in block S220.

At block S222, the passivation layer is removed. Fig. 10 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S222.

At block S224, the portion of the dummy dielectric layer not covered by the dummy gate is removed. Fig. 11 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S224.

At block S226, gate spacers are formed on opposing sidewalls of the dummy gate. Fig. 12 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S226.

At block S230, a plurality of source/drain structures are formed over the substrate. Fig. 13 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S230.

At block S232, a Contact Etch Stop Layer (CESL) and a first inter-layer dielectric (ILD) layer are formed. Fig. 14A and 14B illustrate cross-sectional views of some embodiments corresponding to the acts in block S232.

At block S234, the dummy dielectric layer and the dummy gate are removed. Fig. 15 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S234.

At block S236, a directional etch process is performed to round the corners of the gate spacers. Fig. 16 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S236.

At block S238, a gate dielectric layer is formed in the gate trench and over the first ILD layer. Fig. 17 illustrates a cross-sectional view of some embodiments corresponding to the act in block S238.

At block S240, a directional etching process is performed to etch back the gate dielectric layer. Fig. 18 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S240.

At block S242, a workfunction metal layer and a fill metal are formed in the gate trench. Figure 19 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S242.

At block S244, a first Etch Stop Layer (ESL) and a second inter-layer dielectric (ILD) layer are deposited over the first ILD layer. Fig. 20 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S244.

At block S246, the second ILD layer, the first ESL, the first ILD layer, and the CESL are etched to form an opening. Fig. 21 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S246.

At block S248, a directional etch process is performed to round the corners of the second ILD layer to enlarge the opening. Fig. 22 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S248.

At block S250, contacts are formed in the openings, respectively. Figure 23 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S250.

At block S252, a second Etch Stop Layer (ESL) and a third inter-layer dielectric (ILD) layer are deposited over the second ILD layer. Fig. 24 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S252.

At block 254, the third ILD layer and the second ESL are etched to form an opening. Fig. 25 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S254.

At block S256, a directional etch process is performed to round the corners of the third ILD layer to enlarge the opening. Fig. 26 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S256.

At block S258, contacts are formed in the openings, respectively. FIG. 27 illustrates a cross-sectional view of some embodiments corresponding to the acts in block S258.

In some embodiments of the present disclosure, a method comprises: forming a dummy gate over a substrate; forming a pair of gate spacers on opposing sidewalls of the dummy gate; removing the dummy gate to form a trench between the gate spacers; directing the first ion beam to an upper portion of the trench such that a lower portion of the trench is substantially free of the first ion beam incident thereon; moving the substrate relative to the first ion beam during the directing of the first ion beam to the trench; and forming a gate structure in the trench.

According to some embodiments of the present disclosure, wherein forming the gate structure in the trench comprises forming a gate dielectric in the trench and over sidewalls of the gate spacers after directing the first ion beam; and directing a second ion beam at an upper portion of the gate dielectric to remove the upper portion of the gate dielectric such that a lower portion of the gate dielectric is substantially free from the second ion beam.

According to some embodiments of the present disclosure, forming a work function metal layer over the gate dielectric such that the work function metal layer is in contact with sidewalls of the gate spacers after directing the second ion beam is further included.

According to some embodiments of the present disclosure, further comprising forming an interlayer dielectric (ILD) layer over the gate spacers; forming an opening in the ILD layer; and directing a second ion beam to an upper portion of the opening such that a lower portion of the opening is substantially free from the second ion beam.

According to some embodiments of the present disclosure, wherein moving the substrate relative to the first ion beam includes moving the substrate in a linear direction during directing the first ion beam.

According to some embodiments of the present disclosure, wherein the linear direction is aligned with a longitudinal direction of the semiconductor fin.

In accordance with some embodiments of the present disclosure, wherein moving the substrate relative to the first ion beam includes moving the substrate in a circular direction during directing the first ion beam.

In some embodiments of the present disclosure, a method comprises: forming a semiconductor fin over a substrate; forming an isolation layer over the substrate and covering the semiconductor fin; performing an annealing process on the isolation layer such that the semiconductor fin is bent after the annealing process is performed; partially removing the isolation layer such that the bent semiconductor fin protrudes from a top surface of the remaining isolation layer; forming a dummy gate material over the semiconductor fin; patterning the dummy gate material to form a dummy gate, wherein a residue of the dummy gate material remains on the first sidewalls of the bent semiconductor fins after patterning the dummy gate material; and performing a directional etch process to remove the residue of the dummy gate material.

In accordance with some embodiments of the present disclosure, forming a dummy dielectric layer prior to forming the dummy gate material, wherein the dummy dielectric layer is between the second semiconductor fin and a residue of the dummy gate material after patterning the dummy gate material.

According to some embodiments of the present disclosure, wherein performing the directional etch process comprises directing an ion beam onto the substrate at an oblique angle with respect to a normal to a top surface of the substrate.

According to some embodiments of the present disclosure, wherein the substrate is positioned on a wafer stage; and directing an ion beam through the grid onto the substrate, wherein performing the directional etch process further comprises applying a bias voltage on the grid and varying the bias voltage during directing the ion beam onto the substrate.

Some embodiments according to the present disclosure further comprise moving the substrate along a longitudinal direction of the dummy gate during performing the directional etch process.

In some embodiments of the present disclosure, a semiconductor device includes a substrate having a semiconductor fin, a gate structure, a gate spacer, and an epitaxial structure. A gate structure is formed over the semiconductor fin, wherein the gate structure has a tapered profile and comprises a gate dielectric, a work function metal layer over the gate dielectric, and a fill metal over the work function metal layer. The gate spacer is along a sidewall of the gate structure, wherein the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. The epitaxial structure is over the semiconductor fin.

According to some embodiments of the present disclosure, wherein a top portion of the gate spacer is thinner than a bottom portion of the gate spacer.

According to some embodiments of the present disclosure, further comprising an etch stop layer over the gate structure, wherein the gate dielectric is separated from the etch stop layer by the work function metal layer.

According to some embodiments of the present disclosure, the top of the gate dielectric is tapered away from the substrate.

According to some embodiments of the present disclosure, the widest width of the fill metal is wider than the widest width of the gate dielectric.

According to some embodiments of the present disclosure, wherein the top of the gate spacer has a curved sidewall in contact with the gate structure.

According to some embodiments of the present disclosure, wherein the top of the gate spacer has a straight sidewall opposite the curved sidewall.

According to some embodiments of the present disclosure, the work function metal layer is closer to the straight sidewalls of the gate spacers than to the gate dielectric.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the embodiments of the present disclosure. Those skilled in the art should appreciate that they can readily use the disclosed embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a dummy gate over a semiconductor fin of a substrate;

forming a pair of gate spacers on opposing sidewalls of the dummy gate;

removing the dummy gate to form a trench between the gate spacers;

directing a first ion beam to an upper portion of the trench such that a lower portion of the trench is substantially free from the first ion beam incident thereon;

moving the substrate relative to the first ion beam during the directing of the first ion beam to the trench; and

a gate structure is formed in the trench.