CN110929271A - Chip tamper-proofing method, system, terminal and storage medium - Google Patents
Chip tamper-proofing method, system, terminal and storage medium Download PDFInfo
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- CN110929271A CN110929271A CN201911048554.8A CN201911048554A CN110929271A CN 110929271 A CN110929271 A CN 110929271A CN 201911048554 A CN201911048554 A CN 201911048554A CN 110929271 A CN110929271 A CN 110929271A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/64—Protecting data integrity, e.g. using checksums, certificates or signatures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
Abstract
The invention provides a chip tamper-proofing method, a system, a terminal and a storage medium, comprising the following steps: randomly generating unique manufacturing parameters for the chip IP core; after the manufacturing parameters are set, carrying out electronic signature encryption to obtain encryption parameters; sending the encryption parameters and the public key to the provisioning link end; and receiving the chip returned by the supply chain end and verifying whether the manufacturing parameters of the chip are unchanged, wherein if the manufacturing parameters of the chip are not changed, the chip is not tampered. The invention can be realized by only utilizing the cryptographic technology and improving the supply chain flow in the chip manufacturing process without adding additional hardware module overhead in the chip, has operability and flexibility, can ensure the intellectual property of developers and ensures the safety of the production process between the developers and a production plant and between the developers and an assembly plant.
Description
Technical Field
The invention relates to the technical field of chip production, in particular to a chip tamper-proofing method, a chip tamper-proofing system, a chip tamper-proofing terminal and a chip tamper-proofing storage medium.
Background
Due to reliability and security issues, counterfeit Integrated Circuit (IC) chips are a major source in the supply chain of electronic components, affecting industries such as medical, aerospace, national defense, automotive, banking, energy/smart grid, and posing a significant threat to the supply chain of electronic components. As the complexity of the counterfeiting technology increases, it becomes more and more difficult to discover counterfeit integrated circuits. The major problems facing the IC chip supply chain are: re-labeling the chip for refurbishment, illegal copying, chip recovery from used circuit boards, and the like. Therefore, it is necessary to perform security control on the chip supply chain to ensure the security of the chip supply process.
At present, developers directly deliver intellectual property cores (IPs) developed by themselves to a manufacturing plant or an assembly plant for wafer production and chip packaging. The manufacturing process of the chip by a production factory and an assembly factory is invisible to a developer, so that the production process of the chip can be tampered or additional information is added, and the intellectual property IP core of the developer cannot be safely guaranteed.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a method, a system, a terminal and a storage medium for preventing chip tampering, so as to solve the above-mentioned technical problems.
In a first aspect, the present invention provides a chip tamper-proofing method, including:
randomly generating unique manufacturing parameters for the chip IP core;
after the manufacturing parameters are set, carrying out electronic signature encryption to obtain encryption parameters;
sending the encryption parameters and the public key to the provisioning link end;
and receiving the chip returned by the supply chain end and verifying whether the manufacturing parameters of the chip are unchanged, wherein if the manufacturing parameters of the chip are not changed, the chip is not tampered.
Further, the encrypting the electronic signature after the setting of the manufacturing parameters to obtain the encrypted parameters includes:
modifying the manufacturing parameters by a preset modification mode, and outputting the modified manufacturing parameters;
and carrying out electronic signature encryption on the modified manufacturing parameters by using a private key of the device to obtain encrypted parameters.
Further, the sending the encryption parameters and the public key to the supply chain end includes:
sending the encryption parameters and the public key to a production end and an assembly end;
and sending the final encrypted parameters obtained by encrypting the electronic signature of the manufacturing parameters to the packaging end.
In a second aspect, the present invention provides a chip tamper-resistant system, comprising:
the parameter generating unit is configured for randomly generating unique manufacturing parameters for the chip IP core;
the parameter encryption unit is configured to encrypt the electronic signature after the manufacturing parameters are set to obtain encryption parameters;
a parameter sending unit configured to send the encryption parameter and the public key to the supply link end;
and the parameter verification unit is configured for receiving the chip returned by the supply chain end and verifying whether the manufacturing parameters of the chip are unchanged, and if not, the chip is not tampered.
Further, the parameter encryption unit includes:
the parameter modification module is configured to modify the manufacturing parameters by using a preset modification mode and output the modified manufacturing parameters;
and the signature encryption module is configured to perform electronic signature encryption on the modified manufacturing parameters by using a private key of the signature encryption module to obtain encrypted parameters.
Further, the parameter sending unit includes:
the process sending module is configured for sending the encryption parameters and the public key to the production end and the assembly end;
and the final sending module is configured to send final encrypted parameters obtained by encrypting the electronic signature of the manufacturing parameters to the packaging end.
In a third aspect, a terminal is provided, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.
In a fourth aspect, a computer storage medium is provided having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.
The beneficial effect of the invention is that,
according to the chip tamper-proofing method, the chip tamper-proofing system, the chip tamper-proofing terminal and the chip tamper-proofing storage medium, the cryptographic technology is utilized in the wafer manufacturing and testing process, in the wafer testing process of a production plant based on the IP core provided by a developer and the chip packaging process of an assembly plant based on the wafer, if the manufacturer has any unauthorized tampering, the developer can know, through the method, the intellectual property of the developer can be effectively protected, and the legal rights and interests of the developer can be maintained. The invention can be realized by only utilizing the cryptographic technology and improving the supply chain flow in the chip manufacturing process without adding additional hardware module overhead in the chip, has operability and flexibility, can ensure the intellectual property of developers and ensures the safety of the production process between the developers and a production plant and between the developers and an assembly plant.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
FIG. 2 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The execution body in fig. 1 may be a chip tamper-resistant system.
As shown in fig. 1, the method 100 includes:
after the manufacturing parameters are set, carrying out electronic signature encryption to obtain encryption parameters;
sending the encryption parameters and the public key to the provisioning link end;
and receiving the chip returned by the supply chain end and verifying whether the manufacturing parameters of the chip are unchanged, wherein if the manufacturing parameters of the chip are not changed, the chip is not tampered.
Optionally, as an embodiment of the present invention, the encrypting the electronic signature after the setting of the manufacturing parameter to obtain the encrypted parameter includes:
modifying the manufacturing parameters by a preset modification mode, and outputting the modified manufacturing parameters;
and carrying out electronic signature encryption on the modified manufacturing parameters by using a private key of the device to obtain encrypted parameters.
Optionally, as an embodiment of the present invention, the sending the encryption parameter and the public key to the supply chain end includes:
sending the encryption parameters and the public key to a production end and an assembly end;
and sending the final encrypted parameters obtained by encrypting the electronic signature of the manufacturing parameters to the packaging end.
In order to facilitate understanding of the present invention, the chip tamper-proofing method provided by the present invention is further described below with reference to the principle of the chip tamper-proofing method of the present invention and the process of performing secure production management on the chip in the embodiment.
Specifically, the chip tamper-proofing method includes:
and S1, randomly generating unique manufacturing parameters for the chip IP core.
The chip IP core, i.e. intellectual property core, designs some functional blocks which are commonly used in digital circuits but are relatively complex, such as FIR filter, SDRAM controller, PCI interface, etc., into modules which can modify parameters. And the chip developer develops the IP core and sends the IP core to manufacturers, assemblers and packagers of a supply chain to realize the production and the manufacture of the chip. In order to avoid the supply chain party to tamper the IP core in the chip production process, the manufacturer randomly generates a unique manufacturing parameter random for the IP core of the developer, sends the manufacturing parameter to the developer, checks whether the same manufacturing parameter exists locally before sending the developer, and if so, needs to be re-generated once (since the manufacturer may produce chips with multiple IP cores, the checking and the deduplication are needed).
In other embodiments, a unique manufacturing parameter may be generated for the IP core by the developer itself.
The IP core and the manufacturing parameters are bound, and if the configuration parameters of the IP core change, the manufacturing parameters of the IP core are found to change when the development is in acceptance.
And S2, setting the manufacturing parameters and then encrypting the electronic signature to obtain encrypted parameters.
Before sending a supply chain side to produce and Test chips, a developer modifies random in a way only known by the developer, changes the random into random1 and adds a digital signature of the developer to form an encryption parameter Test _ Key.
Before sending the supply chain side for chip packaging, the developer adds the manufacturing parameter random to its own digital signature to form the final encryption parameter.
S3, sending the encryption parameters and the public key to the provisioning link end. And receiving the chip returned by the supply chain end and verifying whether the manufacturing parameters of the chip are unchanged, wherein if the manufacturing parameters of the chip are not changed, the chip is not tampered.
The developer sends the encrypted parameters and the public Key to the production plant, the production plant decrypts the Test Key Test _ Key by using the public Key of the developer to obtain random1, and the wafer is tested based on random 1. And the developer confirms the test result, and if the test is passed, the chip packaging process is started. If random1 is tampered with by the manufacturer, the test result will not pass. In this way, the supply chain between the developer and the production plant is ensured to be safe.
The developer sends the encrypted parameters and the public Key to the side of assembling the chip, the assembly factory decrypts the Test _ Key by using the public Key and then recovers random1, and verification testing before packaging is carried out based on random1, and if the random1 is tampered by the assembly factory, the testing cannot pass. In this way, the supply chain between the developer and the assembly plant is secured.
And the developer sends the Final encryption parameters and the public Key to an assembly factory for packaging the chip, and the assembly factory writes the Final Key Final _ Key into the wafer for packaging to obtain a Final chip. Since the Key Final _ Key is digitally signed by the developer, it cannot be tampered with by the assembly plant.
As shown in fig. 2, the system 200 includes:
a parameter generation unit 210 configured to randomly generate a unique manufacturing parameter for the chip IP core;
a parameter encryption unit 220 configured to encrypt the electronic signature after setting the manufacturing parameters to obtain encrypted parameters;
a parameter sending unit 230 configured to send the encryption parameter and the public key to the supply chain end;
and the parameter verification unit 240 is configured to receive the chip returned by the supply chain end and verify whether the manufacturing parameters of the chip are unchanged, and if not, the chip is not tampered.
Optionally, as an embodiment of the present invention, the parameter encryption unit includes:
the parameter modification module is configured to modify the manufacturing parameters by using a preset modification mode and output the modified manufacturing parameters;
and the signature encryption module is configured to perform electronic signature encryption on the modified manufacturing parameters by using a private key of the signature encryption module to obtain encrypted parameters.
Optionally, as an embodiment of the present invention, the parameter sending unit includes:
the process sending module is configured for sending the encryption parameters and the public key to the production end and the assembly end;
and the final sending module is configured to send final encrypted parameters obtained by encrypting the electronic signature of the manufacturing parameters to the packaging end.
Fig. 3 is a schematic structural diagram of a terminal system 300 according to an embodiment of the present invention, where the terminal system 300 may be used to execute the chip tamper-proofing method according to the embodiment of the present invention.
The terminal system 300 may include: a processor 310, a memory 320, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 320 may be used for storing instructions executed by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 320, when executed by processor 310, enable terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 320 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 310 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Therefore, the invention utilizes the cryptographic technology in the wafer manufacturing and testing process, and the developers can know that the developers can effectively protect the intellectual property rights of the developers and maintain the legal rights of the developers if the manufacturers have any unauthorized tampering in the wafer testing process based on the IP core provided by the developers in a production factory and the chip packaging process based on the wafers in an assembly factory. The invention can be realized by only utilizing the cryptographic technology and improving the supply chain flow in the chip manufacturing process without adding additional hardware module overhead in the chip, has operability and flexibility, can ensure the intellectual property of developers and the safety of the production process between the developers and a production plant and between the developers and an assembly plant, and can achieve the technical effect which is referred to the description above and is not repeated herein.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A method of tamper-proofing a chip, comprising:
randomly generating unique manufacturing parameters for the chip IP core;
after the manufacturing parameters are set, carrying out electronic signature encryption to obtain encryption parameters;
sending the encryption parameters and the public key to the provisioning link end;
and receiving the chip returned by the supply chain end and verifying whether the manufacturing parameters of the chip are unchanged, wherein if the manufacturing parameters of the chip are not changed, the chip is not tampered.
2. The method for preventing the chip from being tampered according to claim 1, wherein the step of encrypting the electronic signature after setting the manufacturing parameters to obtain the encrypted parameters comprises:
modifying the manufacturing parameters by a preset modification mode, and outputting the modified manufacturing parameters;
and carrying out electronic signature encryption on the modified manufacturing parameters by using a private key of the device to obtain encrypted parameters.
3. The chip tamper-proofing method of claim 1, wherein the sending the encryption parameters and the public key to the supply chain end comprises:
sending the encryption parameters and the public key to a production end and an assembly end;
and sending the final encrypted parameters obtained by encrypting the electronic signature of the manufacturing parameters to the packaging end.
4. A chip tamper-resistant system, comprising:
the parameter generating unit is configured for randomly generating unique manufacturing parameters for the chip IP core;
the parameter encryption unit is configured to encrypt the electronic signature after the manufacturing parameters are set to obtain encryption parameters;
a parameter sending unit configured to send the encryption parameter and the public key to the supply link end;
and the parameter verification unit is configured for receiving the chip returned by the supply chain end and verifying whether the manufacturing parameters of the chip are unchanged, and if not, the chip is not tampered.
5. The chip tamper-resistant system according to claim 4, wherein the parameter encryption unit includes:
the parameter modification module is configured to modify the manufacturing parameters by using a preset modification mode and output the modified manufacturing parameters;
and the signature encryption module is configured to perform electronic signature encryption on the modified manufacturing parameters by using a private key of the signature encryption module to obtain encrypted parameters.
6. The chip tamper-resistant system according to claim 4, wherein the parameter transmission unit includes:
the process sending module is configured for sending the encryption parameters and the public key to the production end and the assembly end;
and the final sending module is configured to send final encrypted parameters obtained by encrypting the electronic signature of the manufacturing parameters to the packaging end.
7. A terminal, comprising:
a processor;
a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the method of any one of claims 1-3.
8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-3.
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| CN201911048554.8A CN110929271A (en) | 2019-10-31 | 2019-10-31 | Chip tamper-proofing method, system, terminal and storage medium |
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| CN201911048554.8A CN110929271A (en) | 2019-10-31 | 2019-10-31 | Chip tamper-proofing method, system, terminal and storage medium |
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| US10353823B2 (en) * | 2004-04-08 | 2019-07-16 | Texas Instruments Incorporated | Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making |
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| US10353823B2 (en) * | 2004-04-08 | 2019-07-16 | Texas Instruments Incorporated | Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making |
| CN103562922A (en) * | 2011-03-30 | 2014-02-05 | 耶德托公司 | Establishing unique key during chip manufacturing |
| CN106991340A (en) * | 2017-03-17 | 2017-07-28 | 广州小微电子技术有限公司 | Chip encryption method |
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