CN110928355A - On-chip passive power supply compensation circuit and arithmetic unit, chip, force calculation board and computing equipment using same - Google Patents
On-chip passive power supply compensation circuit and arithmetic unit, chip, force calculation board and computing equipment using same Download PDFInfo
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Abstract
The invention provides an on-chip passive power supply compensation circuit, and an arithmetic unit, a chip, a force calculation board and computing equipment using the same. The on-chip passive power supply compensation circuit comprises two or more voltage domains to be supplied, wherein the voltage domains to be supplied are connected between a power supply and the ground in series; the power supply device comprises two or more isolation regions, a power supply voltage domain and a power supply voltage domain, wherein the isolation regions are formed in the isolation regions and used for isolating the power supply voltage domain; the isolation regions are connected in series between the power supply and the ground; the power compensation unit is connected between the voltage domain to be supplied and the isolation area and used for providing power compensation for the voltage domain to be supplied. The on-chip passive power supply compensation circuit can effectively reduce power consumption, reduce design difficulty, save chip area and reduce production cost.
Description
Technical Field
The invention relates to a multi-voltage-domain power supply circuit, in particular to a circuit for compensating a power supply voltage based on a substrate reference, and an arithmetic unit, a chip, a calculation board and a calculation device applying the circuit.
Background
Virtual currency (e.g., bitcoin, ethernet) is a digital currency in the form of P2P, which has received much attention since the 2009 bitcoin system. The system constructs the distributed shared general ledger based on the block chain, thereby ensuring the safety, reliability and decentralization of the system operation.
In hashing and proof of workload, bitcoin is the only correct hash value calculated to prove the workload to obtain accounting packed block right and thus the reward, which is proof of workload (Pow). At present, no effective algorithm is available for hash operation except for brute force calculation. For a new generation of computing devices for mining virtual digital currency, the mining process is a logical computing pipeline that performs a large number of iterations.
The core of this computing device design is that performance to power consumption ratio, higher performance and lower power consumption represent a higher efficiency of mining, while meaning that more computing power can be achieved at the same power consumption.
In addition, a large number of repetitive logic calculations require a large current to be supplied to the computing device, which results in a large additional power consumption of the computing device in addition to the power consumption required for the logic calculations. Therefore, there is a need to reduce the operating current of a computing device, thereby reducing its additional power consumption.
CN206039425U discloses a serial power supply circuit, as shown in fig. 1, a plurality of package units are serially connected between a power supply terminal VCC and ground, each package unit includes one or more groups of elements, each group of elements includes a chip to be powered and an auxiliary power supply unit, and a signal level conversion unit is serially connected between chips to be powered in two adjacent groups of elements. Although the series power supply circuit can provide low power supply voltage for each chip to be powered, the series power supply circuit aims at providing series power supply for different packaging units on a printed circuit board and cannot provide series power supply between different voltage domains in the chip.
Multi-voltage domain (Multi-voltage domain) power supply technology is increasingly widely applied to System-on-chip (SoC) and multiprocessor computing structures. In a chip applying multiple voltage domain technology, the chip usually contains multiple independent voltage domains or voltage islands, and the modules under each voltage domain operate at the proper power supply voltage according to the requirements of their timing. Generally, for a module with critical timing, it usually operates under high supply Voltage (VDDH) to meet the speed performance requirement of the chip; for non-critical circuit modules, the circuit module is operated at a low supply Voltage (VDDL) or even a sub-threshold supply voltage to reduce the power consumption and energy consumption of the chip.
CN206523836U discloses an internal serial power supply system of chips, as shown in fig. 2, in the serial power supply chip, each unit to be powered may include a chip core (core), or each unit to be powered may include a plurality of chip cores connected in parallel. The circuit of the chip core of each level of voltage domain comprises a P-channel Metal Oxide Semiconductor (PMOS) tube and an N-channel Metal Oxide Semiconductor (NMOS) tube respectively. The chip core of each level of voltage domain, the substrate of the PMOS tube of the chip core is connected with the power supply voltage or the working Voltage (VDD) of the voltage domain, the VDD of the voltage domain is connected with the ground (VSS) of the voltage domain of the previous level, in the series power supply chip, the chip core also comprises n deep wells for realizing the isolation between different voltage domains, the n deep wells are mutually independently arranged and not connected, each unit to be powered in the n units to be powered is respectively positioned in one deep well, thereby realizing the isolation between different voltage domains on the same chip and effectively avoiding the short circuit formed between different voltage domains. Although the serial power supply system inside the chip realizes serial power supply among different voltage domains inside the chip, each voltage domain needs to additionally provide auxiliary voltage sources VDD _1, VDD _2 and the like besides power supply VDD, so that the auxiliary voltage sources are difficult to design, occupy a large amount of chip area and generate large power consumption.
Disclosure of Invention
In order to solve the problems, the invention provides an on-chip passive power supply compensation circuit based on a substrate reference, which not only reduces the power consumption, but also reduces the design difficulty, saves the chip area and reduces the production cost.
In order to achieve the above object, the present invention provides an on-chip passive power compensation circuit, including:
the power supply system comprises two or more voltage domains to be supplied, wherein the voltage domains to be supplied are connected between a power supply and the ground in series;
the power supply device comprises two or more isolation regions, a power supply voltage domain and a power supply voltage domain, wherein the isolation regions are formed in the isolation regions and used for isolating the power supply voltage domain;
the isolation regions are connected in series between the power supply and the ground;
the power compensation unit is connected between the voltage domain to be supplied and the isolation area and used for providing power compensation for the voltage domain to be supplied.
In the above on-chip passive power compensation circuit, the power compensation unit provides power compensation to the voltage domain to be supplied by operating in a saturation state.
In the above on-chip passive power compensation circuit, a first power end and a first ground end are formed at two ends of each isolation region, and the first power end and/or the first ground end are used for providing a reference voltage for the power compensation unit.
In the above on-chip passive power compensation circuit, a second power end and a second ground are formed at two ends of each to-be-powered voltage domain, and the power compensation unit provides power compensation for the second power end and/or the second ground.
In the above on-chip passive power compensation circuit, when the voltage variation range of the second power end and/or the second ground end exceeds the threshold of the power compensation unit, the power compensation unit operates in the saturation state based on the reference voltage.
In the above on-chip passive power compensation circuit, the power compensation unit is a switching transistor.
In the above on-chip passive power compensation circuit, the switch transistor is a PMOS switch transistor and/or an NMOS switch transistor.
In the above on-chip passive power compensation circuit, one or more of the PMOS switch transistor and/or the NMOS switch transistor may be provided.
The on-chip passive power compensation circuit described above, wherein one or more semiconductor devices are formed in the voltage domain to be supplied, and the second power supply terminal and/or the second ground terminal provide a substrate bias voltage to the semiconductor devices.
The above on-chip passive power compensation circuit, wherein the semiconductor device comprises a PMOS transistor and/or an NMOS transistor, the second power supply terminal provides a substrate bias voltage to the PMOS transistor, and the second ground terminal provides a substrate bias voltage to the NMOS transistor.
In order to achieve the above object, the present invention further provides a data operation unit, wherein the data operation unit includes a control circuit, an operation circuit, a storage circuit, and one or more on-chip passive power compensation circuits, which are connected to each other, and the on-chip passive power compensation circuit is any one of the above on-chip passive power compensation circuits.
In order to achieve the above object, the present invention further provides a chip, wherein the chip includes any one of the data operation units described above.
In order to achieve the above object, the present invention further provides a force calculation board for a computing device, wherein the force calculation board includes any one of the above chips.
In order to achieve the above object, the present invention further provides a computing device, which includes a power board, a control board, a connecting board, a heat sink, and a plurality of force calculation boards, wherein the control board is connected to the force calculation boards through the connecting board, the heat sink is disposed around the force calculation boards, and the power board is configured to provide power to the connecting board, the control board, the heat sink, and the force calculation boards are any one of the force calculation boards.
By adopting the on-chip passive power supply compensation circuit, the stable working voltage can be provided for the voltage domain to be supplied on the premise of not needing an auxiliary power supply. Not only reduces the power consumption, but also reduces the design difficulty, saves the chip area and reduces the production cost.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
FIG. 1 is a schematic diagram of a conventional series power supply circuit;
FIG. 2 is a schematic diagram of a conventional series power supply system inside a chip;
FIG. 3 is a schematic diagram of a series power supply circuit without an on-chip passive power compensation circuit according to the present invention;
FIG. 4 is a schematic diagram of an on-chip passive power compensation circuit according to an embodiment of the invention;
FIG. 5 is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention;
FIG. 7 is a schematic diagram of an on-chip passive power compensation circuit according to yet another embodiment of the present invention;
FIG. 8 is a schematic diagram of a data operation unit according to the present invention;
FIG. 9 is a diagram of a chip according to the present invention;
FIG. 10 is a schematic view of a force computation plate according to the present invention;
FIG. 11 is a schematic diagram of a computing device of the present invention.
Wherein, the reference numbers:
10: series power supply circuit
100: on-chip passive power supply compensation circuit
101-1, 101-2,.. 101-n: voltage domain
102-1, 102-2,.. 102-n: deep N-well
103-1, 103-2,.. 103-n: p well
104-1, 104-2,.. 104-n: n-well
105. 105': switching transistor
106: bulk resistor
VDD1, VDD2, page. Power supply terminal of voltage domain
VSS1, VSS2, a. Ground terminal of voltage domain
VPP1, VPP2,.... VPPn: power supply terminal of deep N-well
VBB1, VBB2,.. VBBn: ground terminal of deep N well
VDD: a system power supply GND: ground of system
S: a source terminal D: drain terminal
G: a gate terminal B: liner end
700-data arithmetic unit 701-control circuit
702-arithmetic circuit 703-memory circuit
800: chip 801: control unit
900: force calculation board 1000: computing device
1001: connecting plate 1002: control panel
1003: the heat sink 1004: power panel
Detailed Description
The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:
certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function. Like reference numerals refer to like elements throughout the specification.
In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "connected" is intended to encompass any direct or indirect electrical connection. Indirect electrical connection means include connection by other means.
FIG. 3 is a schematic diagram of a series power supply circuit without an on-chip passive power compensation circuit according to the present invention. As shown in fig. 3, taking the chip substrate as a P-type substrate as an example, n voltage domains 101-1, 101-2.. 101-n to be powered are formed in the series power supply circuit 10, where n is a positive integer greater than 1. Each voltage domain 101-1, 101-2.. 101-N is isolated from the other voltage domains by a corresponding deep N-well 102-1, 102-2.. 102-N, respectively, to prevent short circuits between the different voltage domains. A number of P-wells 103-1, 103-2.. 103-N and N-wells 104-1, 104-2.... 104-N are formed within the deep N-wells 102-1, 102-2.... 102-N, respectively.
101-n have PMOS transistors and/or NMOS transistors formed therein, and if necessary, other types of devices such as resistors and capacitors may be formed therein. Wherein the PMOS transistors are formed in N-wells 104-1, 104-2.. 104-N and the NMOS transistors are formed in P-wells 103-1, 103-2.. 103-N. The PMOS transistor and the NMOS transistor are used to implement various functions of the chip.
The voltage domains 101-1, 101-2 to be supplied with power are connected in series between a system power supply VDD and a system ground GND in turn. The power supply terminal VDD1 of the voltage domain 101-1 is connected to the system power supply VDD, the ground terminal VSS1 of the voltage domain 101-1 is connected to the power supply terminal VDD2 of the next-stage voltage domain 101-2, the ground terminal VSS2 of the voltage domain 101-2 is connected to the power supply terminal VDD3 of the next-stage voltage domain 101-3, and is connected to the system ground GND in series in sequence towards the next stage, and the ground terminal VSSn of the voltage domain 101-n is connected to the system ground GND. Thereby forming n voltage domains of the series supply.
The PMOS transistor or the NMOS transistor has four S/D/G/B ports, which are respectively called a source terminal, a drain terminal, a gate terminal and a substrate terminal. Typically, the PMOS transistors within each voltage domain 101-1, 101-2.. cndot.101-n have their substrate terminals and source terminals connected together to the voltage domain power terminals VDD1, vdd2.. cndot.vddn, and the NMOS transistors have their substrate terminals and source terminals connected together to the voltage domain ground terminals VSS1, VSS2.. cndot.vssn. When the voltage between the gate terminal and the substrate terminal exceeds the threshold voltage, a source-to-drain conductive channel is formed in the substrate so that carriers can flow in the substrate between the source and drain terminals, forming a current.
When n voltage domains supplied in series normally operate, the potentials of the power supply terminals VDD1, vdd2.... cndot.vddn and the ground terminals VSS1, VSS2.. cndot.vssn of each voltage domain substantially maintain a stable state. When a large current is generated in one voltage domain 101-m (m is greater than or equal to 1 and less than or equal to n) of n voltage domains supplied in series, due to the self resistance of the voltage domain 101-m, a large voltage difference is formed between two ends of the voltage domain 101-m, so that voltages at two ends of other voltage domains without large current are affected to generate power supply voltage drift, the drift is continuously generated along with the change of the current, and the drift and the current magnitude form a positive correlation relationship, thereby possibly causing the function failure of the chip.
In order to avoid the above situation, it is generally improved by adding an auxiliary power supply, that is, adding an auxiliary power supply to each voltage domain to supply power to the voltage domain. The invention provides an on-chip passive power supply compensation circuit based on substrate reference, which can reduce the voltage drift at two ends of a voltage domain under the condition of not increasing an auxiliary power supply.
Example one
Fig. 4 is a schematic diagram of an on-chip passive power compensation circuit according to an embodiment of the invention. As shown in fig. 4, taking the chip substrate as a P-type substrate as an example, n voltage domains 101-1, 101-2.. 101-n to be powered are formed in the on-chip passive power compensation circuit 100 of the present invention, where n is a positive integer greater than 1. Each voltage domain 101-1, 101-2.. 101-N is isolated from the other voltage domains by a corresponding deep N-well 102-1, 102-2.. 102-N, respectively, to prevent short circuits between the different voltage domains. A number of P-wells 103-1, 103-2.. 103-N and N-wells 104-1, 104-2.... 104-N are formed within the deep N-wells 102-1, 102-2.... 102-N, respectively.
101-n have PMOS transistors and/or NMOS transistors formed therein, and if necessary, other types of devices such as resistors and capacitors may be formed therein. Wherein, PMOS transistor is formed in N trap 104-1, 104-2. The PMOS transistor and the NMOS transistor are used to implement various functions of the chip.
The voltage domains 101-1, 101-2 to be supplied with power are connected in series between a system power supply VDD and a system ground GND in turn. The power supply terminal VDD1 of the voltage domain 101-1 is connected to the system power supply VDD, the ground terminal VSS1 of the voltage domain 101-1 is connected to the power supply terminal VDD2 of the next-stage voltage domain 101-2, the ground terminal VSS2 of the voltage domain 101-2 is connected to the power supply terminal VDD3 of the next-stage voltage domain 101-3, and is connected to the system ground GND in series in sequence towards the next stage, and the ground terminal VSSn of the voltage domain 101-n is connected to the system ground GND. N voltage domains are thus formed, which are supplied in series, the supply terminals of each voltage domain 101-1, 101-2.
The deep N-wells 102-1, 102-2. In addition to forming the series power supply path described above, the present invention also uses the bulk resistance 106 of the P-well and/or N-well to divide the system power supply VDD, creating a voltage division across the deep N-wells 102-1, 102-2. The power supply terminal VPP1 of the deep N-well 102-1 is connected to a system power supply VDD, the ground terminal VBB1 of the deep N-well 102-1 is connected to the power supply terminal VPP2 of the next deep N-well 102-2, the ground terminal VBB2 of the deep N-well 102-2 is connected to the power supply terminal VPP3 of the next deep N-well 102-3, and the power supply terminals VPP1 and the power supply terminal VBB2 are sequentially connected in series to the next deep N-well; the ground terminal VBBn of the deep N-well 102-N is connected to the system ground GND. Deep N wells which are sequentially connected in series and have relatively stable potentials at two ends are formed between a system power supply VDD and a ground GND, the power supply ends of the deep N wells 102-1 and 102-2.
Ideally, the voltages of the power source terminals VDD1, vdd2.. cndot.101-N of the voltage domains 101-1, 101-2.. cndot.101-N are the same as the voltages of the power source terminals VPP1, VPP2.. cndot.102-N of the deep N wells 102-1, 102-2.. cndot.102-N, respectively, and the voltages of the ground terminals vbvss 1, VSS2.. cndot.vssn of the voltage domains 101-1, 101-2.. cndot.101-N are the same as the voltages of the ground terminals VBB1, VBB2.. cndot.vbbn of the deep N wells 102-1, 102-2.. cndot.102-N, respectively.
In the present embodiment, the source terminals of the PMOS transistors within each voltage domain 101-1, 101-2.... 101-N are connected to the power supply terminals VDD1, vdd2.. VDDn of that voltage domain, and the substrate terminals of the PMOS transistors are connected to the power supply terminals VPP1, VPP2.. cndot.vppn of the deep N-wells 102-1, 102-2.. cndot.102-N; the source terminals of the NMOS transistors within each voltage domain 101-1, 101-2.... 101-N are connected to the ground terminals VSS1, VSS2.... VSSn of that voltage domain, and the substrate terminals of the NMOS transistors are connected to the ground terminals VBB1, VBB2.... VBBn of the deep N-wells 102-1, 102-2.... 102-N.
In addition, the on-chip passive power compensation circuit of the invention further comprises a switch transistor 105, wherein the switch transistor 105 is an NMOS transistor and is formed in the voltage domain 101-2, 101-3. Taking the voltage domain 101-2 as an example, the drain terminal D of the switching transistor 105 in the voltage domain 101-2 is connected to the power source terminal VDD1 of the upper level voltage domain 101-1, the source terminal S of the switching transistor 105 is connected to the power source terminal VDD2 of the present level voltage domain 101-2, the gate terminal G of the switching transistor 105 is connected to the power source terminal VPP2 of the present level deep N-well 102-2, and the substrate terminal B of the switching transistor 105 is connected to the ground terminal VBB2 of the present level deep N-well 102-2.
The gate terminal G and the substrate terminal B of the switching transistor 105 are connected to VPP2 and VBB2, respectively, and no current flows between the gate and the substrate due to the influence of the gate capacitance and the substrate bulk capacitance, so that the potential of VPP2 is kept stable. Ideally, the voltage VPP2 at the gate terminal G of the switching transistor 105 is greater than the voltage VBB2 at the substrate terminal B, thereby forming a conduction channel in the substrate. However, since the voltage VDD1 of the drain terminal D of the switching transistor is greater than the voltage VPP2 of the gate terminal G, the voltage VPP2 of the gate terminal G is the same as the voltage VDD2 of the source terminal S, i.e., Vd＞Vg＝VsI.e. Vgs0, a conductive channel formed in the substrate pinches off, and no current flows between the source terminal S and the drain terminal D.
When the power supply VDD2 of the present voltage domain is not sufficiently powered, the voltage drop of VDD2, i.e. the voltage drop of the source terminal S of the switch transistor 105, will form V because the voltage VPP2 of the gate terminal G remains unchangedgsA state > 0. Due to Vds＞VgsWhen V isgs＝VthAt this time, the switching transistor 105 is turned on and operates in a saturation region, and at this time, the source terminal S and the drain terminal of the switching transistor 105The current between D is: i isDS＝[K*(W/L)*(Vgs-Vth)2]/2. At this point, VDD1 at the drain terminal D gives VDD2 at the source terminal S sufficient charge to replenish, the potential of VDD2 will be clamped (VPP 2-V)th) And will not be further reduced.
For the same reason, when the drain terminal D of the switch transistor 105 is connected to the ground terminal VSS1 of the previous stage voltage domain and the source terminal S is connected to the ground terminal VSS2 of the current stage voltage domain, the potential of the current stage voltage domain VSS2 can be clamped (VSS 2-V)th) Within the range.
Example two
Fig. 5 is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the invention. As shown in fig. 5, the present embodiment is different from the first embodiment in the type and connection manner of the switching transistor 105'.
In the present embodiment, the on-chip passive power compensation circuit 100 also includes a switching transistor 105 ', and the switching transistor 105' is a PMOS transistor and is formed in the voltage domain 101-2, 101-3. Taking the voltage domain 101-2 as an example, the drain terminal D of the switching transistor 105 'in the voltage domain 101-2 is connected to the ground terminal VSS3 of the next-stage voltage domain 101-3, the source terminal S of the switching transistor 105' is connected to the ground terminal VSS2 of the current-stage voltage domain 101-2, the gate terminal G of the switching transistor 105 'is connected to the ground terminal VBB2 of the current-stage deep N-well 102-2, and the substrate terminal B of the switching transistor 105' is connected to the power terminal VPP2 of the current-stage deep N-well 102-2.
The gate terminal G and the substrate terminal B of the switching transistor 105' are connected to VBB2 and VPP2, respectively, and no current flows between the gate and the substrate due to the influence of the gate capacitance and the substrate bulk capacitance, so that the potentials of VBB2 and VPP2 are kept stable. Ideally, the voltage VBB2 at the gate terminal G of the switching transistor 105' is less than the voltage VPP2 at the substrate terminal B, thereby forming a conducting channel in the substrate. However, since the voltage VSS3 of the drain terminal D of the switching transistor 105' is lower than the voltage VBB2 of the gate terminal G, the voltage VBB2 of the gate terminal G is the same as the voltage VSS2 of the source terminal S, i.e., Vd＞Vg＝VsI.e. Vgs0, a conductive channel formed in the substrate pinches off, at the source S and drain terminalsNo current flows between D.
When the VSS2 in the voltage domain of the current stage forms an over-current, the voltage of VSS2 rises, i.e., the source terminal S of the switch transistor 105' rises, and V is formed because the voltage VBB2 of the gate terminal G remains unchangedgsA state of < 0. The threshold voltage of the switching transistor 105' is VthDue to Vds＞VgsWhen V isgs＝VthAt this time, the switching transistor 105 'is turned on and operates in a saturation region, and at this time, the current between the source terminal S and the drain terminal D of the switching transistor 105' is: i isDS＝[K*(W/L)*(Vgs-Vth)2]/2. At this time, VSS3 at the drain terminal D gives VSS2 at the source terminal S sufficient charge drain, and the potential of VSS2 will be clamped at (VSS2+ V)th) Within the range, it does not rise further.
For the same reason, when the drain terminal D of the switch transistor 105' is connected to the power source terminal VDD3 of the next stage voltage domain and the source terminal S is connected to the power source terminal VDD2 of the current stage voltage domain, the potential of the power source terminal VDD2 of the current stage voltage domain can be clamped to (VDD2+ V)th) Within the range.
EXAMPLE III
The first embodiment and the second embodiment only show the case where the switching transistors formed in the same voltage domain are of one type, either PMOS transistors or NMOS transistors, and in different cases, both PMOS transistors and NMOS transistors may be formed in each voltage domain as the switching transistors.
FIG. 6 is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the invention. As shown in fig. 6, taking the mth voltage domain 101-m of the on-chip passive power compensation circuit 100 as an example, the switching transistor 105 and the switching transistor 105' are formed in the voltage domain 101-m. The switch transistor 105 is an NMOS transistor, and the connection method of the switch transistor 105 is the same as that of the switch transistor 105 in the first embodiment; the switching transistor 105 'is a PMOS transistor, and is connected in the same manner as the switching transistor 105' in the second embodiment.
Example four
Embodiment three shows a case where one PMOS transistor and one NMOS transistor are formed at the same time in the same voltage domain as the switching transistor. If only one set of switching transistors 105, 105' is provided, it can quickly compensate when there is a large current change in its adjacent circuits. However, when the circuit at a position far away from the circuit generates a large current change, the circuit cannot compensate in time, and the power supply voltage of the whole voltage domain may change along with the working current, so that the circuit of the whole voltage domain cannot work normally. In actual design and production, the number of switching transistors may be set to be plural.
FIG. 7 is a schematic diagram of an on-chip passive power compensation circuit according to still another embodiment of the invention. As shown in fig. 7, a plurality of switching transistors 105, 105' are formed in each stage of the voltage domain 101 of the on-chip passive power compensation circuit 100.
Each stage of the voltage domain 101 has a certain spare area except for the area where necessary devices are formed. In order to quickly provide power compensation to adjacent circuits and improve power compensation capability, as many switching transistors 105, 105' as possible may be formed in the vacant regions in the voltage domain 101, and the specific number may be determined according to the size of the vacant regions in the voltage domain 101. The plurality of switching transistors 105 and 105' may be uniformly or non-uniformly arranged.
The invention also provides a data operation unit, and fig. 8 is a schematic diagram of the data operation unit of the invention. As shown in fig. 8, the data operation unit 700 includes a control circuit 701, an operation circuit 702, a memory circuit 703, and one or more on-chip passive power compensation circuits 100, which are interconnected.
The invention also provides a chip, and fig. 9 is a schematic diagram of the chip of the invention. As shown in fig. 9, chip 800 includes one or more data arithmetic units 700.
The invention also provides a force calculating board, and fig. 10 is a schematic diagram of the force calculating board. As shown in fig. 10, each computing board 900 includes one or more chips 800 for performing hash operations on the work data sent from the mine.
The invention also provides a computing device which is preferably used for the operation of mining the virtual digital currency, and the computing device can be used for any other massive operations. FIG. 11 is a schematic diagram of a computing device of the present invention. As shown in fig. 11, each computing device 1000 includes a connection board 1001, a control board 1002, a heat sink 1003, a power board 1004, and one or more computing boards 900. The control board 1002 is connected to the force calculation board 900 through a connection board 1001, and the heat sink 1003 is disposed around the force calculation board 900. The power board 1004 is used to provide power to the connection board 1001, the control board 1002, the heat sink 1003, and the computing board 900.
It should be noted that in the description of the present invention, the terms "lateral", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
While embodiments of the invention have been described above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the invention pertains, and further modifications may readily be made by those skilled in the art, it being understood that the invention is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.
In other words, the present invention may have other embodiments, and those skilled in the art can make various corresponding changes and modifications according to the present invention without departing from the spirit and the essence of the present invention, and these corresponding changes and modifications should fall within the protection scope of the appended claims.
Claims (14)
1. An on-chip passive power compensation circuit, comprising:
the power supply system comprises two or more voltage domains to be supplied, wherein the voltage domains to be supplied are connected between a power supply and the ground in series;
the power supply device comprises two or more isolation regions, a power supply voltage domain and a power supply voltage domain, wherein the isolation regions are formed in the isolation regions and used for isolating the power supply voltage domain;
the isolation regions are connected in series between the power supply and the ground;
the power compensation unit is connected between the voltage domain to be supplied and the isolation area and used for providing power compensation for the voltage domain to be supplied.
2. The on-chip passive power compensation circuit of claim 1, wherein: the power supply compensation unit provides power supply compensation for the voltage domain to be supplied by working in a saturation state.
3. The on-chip passive power compensation circuit of claim 2, wherein: and forming a first power supply end and a first ground end at two ends of each isolation region, wherein the first power supply end and/or the first ground end are/is used for providing reference voltage for the power supply compensation unit.
4. The on-chip passive power compensation circuit of claim 3, wherein: and forming a second power supply end and a second ground end at two ends of each voltage domain to be supplied with power, wherein the power supply compensation unit provides power supply compensation for the second power supply end and/or the second ground end.
5. The on-chip passive power compensation circuit of claim 4, wherein: and when the voltage variation range of the second power supply end and/or the second ground end exceeds the threshold value of the power supply compensation unit by taking the reference voltage as a reference, the power supply compensation unit works in the saturation state.
6. The on-chip passive power compensation circuit of claim 5, wherein: the power supply compensation unit is a switching transistor.
7. The on-chip passive power compensation circuit of claim 6, wherein: the switch transistor is a PMOS switch transistor and/or an NMOS switch transistor.
8. The on-chip passive power compensation circuit of claim 7, wherein: the number of the PMOS switch transistor and/or the NMOS switch transistor is one or more.
9. The on-chip passive power compensation circuit of claim 8, wherein: one or more semiconductor devices are formed in the voltage domain to be powered, and the first power supply terminal and/or the first ground terminal provide a substrate bias voltage for the semiconductor devices.
10. The on-chip passive power compensation circuit of claim 9, wherein: the semiconductor device comprises a PMOS transistor and/or an NMOS transistor, the first power supply terminal provides a substrate bias voltage for the PMOS transistor, and the first ground terminal provides a substrate bias voltage for the NMOS transistor.
11. A data arithmetic unit comprises a control circuit, an arithmetic circuit, a storage circuit and one or more on-chip passive power compensation circuits which are connected with each other, and is characterized in that: the on-chip passive power compensation circuit is as claimed in any one of claims 1-10.
12. A chip comprising at least one data arithmetic unit as claimed in any one of claim 11.
13. A computing board for use in a computing device, comprising a plurality of said chips of any one of claim 12.
14. A computing device, comprising a power board, a control board, a connecting board, a heat sink and a plurality of computing boards, wherein the control board is connected with the computing boards through the connecting board, the heat sink is disposed around the computing boards, and the power board is used for providing power to the connecting board, the control board, the heat sink and the computing boards, wherein the computing boards are any one of the computing boards in claim 13.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811103945.0A CN110928355A (en) | 2018-09-20 | 2018-09-20 | On-chip passive power supply compensation circuit and arithmetic unit, chip, force calculation board and computing equipment using same |
| US17/251,659 US11442517B2 (en) | 2018-09-20 | 2019-06-06 | On-chip passive power supply compensation circuit and operation unit, chip, hash board and computing device using same |
| PCT/CN2019/090434 WO2020057180A1 (en) | 2018-09-20 | 2019-06-06 | On-chip passive power supply compensation circuit and operational unit applying same, and chip, hashboard and computing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811103945.0A CN110928355A (en) | 2018-09-20 | 2018-09-20 | On-chip passive power supply compensation circuit and arithmetic unit, chip, force calculation board and computing equipment using same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110928355A true CN110928355A (en) | 2020-03-27 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811103945.0A Pending CN110928355A (en) | 2018-09-20 | 2018-09-20 | On-chip passive power supply compensation circuit and arithmetic unit, chip, force calculation board and computing equipment using same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110928355A (en) |
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2018
- 2018-09-20 CN CN201811103945.0A patent/CN110928355A/en active Pending
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