CN110912881A - Honeypot scrambling method for cryptographic algorithm IP core - Google Patents
Honeypot scrambling method for cryptographic algorithm IP core Download PDFInfo
- Publication number
- CN110912881A CN110912881A CN201911131143.5A CN201911131143A CN110912881A CN 110912881 A CN110912881 A CN 110912881A CN 201911131143 A CN201911131143 A CN 201911131143A CN 110912881 A CN110912881 A CN 110912881A
- Authority
- CN
- China
- Prior art keywords
- interface
- data
- cryptographic algorithm
- core
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/14—Network architectures or network communication protocols for network security for detecting or protecting against malicious traffic
- H04L63/1441—Countermeasures against malicious traffic
- H04L63/1491—Countermeasures against malicious traffic using deception as countermeasure, e.g. honeypots, honeynets, decoys or entrapment
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention belongs to the technical field of digital chip design, and particularly relates to a honeypot scrambling method for an IP core of a cryptographic algorithm. The honeypot scrambling method detects whether the current cryptographic algorithm IP core is attacked or not during application, and returns scrambled data when the current cryptographic algorithm IP core is attacked, so that the security of the cryptographic algorithm IP core is enhanced. The invention has the beneficial effects that when the cryptographic algorithm IP core is attacked, sensitive data such as a protection key and the like are not easy to steal, thereby enhancing the security of the cryptographic algorithm IP core.
Description
Technical Field
The invention belongs to the technical field of digital chip design, and particularly relates to a honeypot scrambling method for an IP core of a cryptographic algorithm.
Background
The cryptographic algorithm IP core is the most core functional part in the information security chip and can provide security functions such as key generation, data encryption and identity authentication. However, the cryptographic algorithm IP core, as a slave device in the chip architecture, usually does not have an active protection function, so once the information system is cracked, the cryptographic algorithm IP core can only passively respond to an operation request of an attacker, so that a secret key and sensitive data are revealed.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to provide a technical scheme applied to a cryptographic algorithm IP core, the sensitive data is protected from being stolen when the cryptographic algorithm IP core is attacked.
(II) technical scheme
In order to solve the above technical problem, the present invention provides a honeypot scrambling method for a cryptographic algorithm IP core, where the honeypot scrambling method is implemented based on a honeypot module, and the cryptographic algorithm IP core acted by the honeypot module includes: an interface module and an algorithm module;
the honeypot module includes: the device comprises a request filtering unit, an address filtering unit, a control unit and a data protection unit, wherein the request filtering unit, the address filtering unit, the control unit and the data protection unit are used for realizing the protection of an IP core of a cryptographic algorithm through the cooperative work of the request filtering unit, the address filtering unit, the control unit and the data protection unit;
the honeypot scrambling method comprises the following steps:
step 1: the request filtering unit receives the interface request information from the interface module, judges whether the current interface request information is legal or not, generates an interface request judgment result and outputs the interface request judgment result to the control unit, and simultaneously sends the interface request information from the interface module to the algorithm module;
step 2: the address filtering unit receives the interface address information requested by the interface module, judges whether the current interface address information is legal or not, generates an interface address judgment result and outputs the interface address judgment result to the control unit, and simultaneously sends the interface address information from the interface module to the algorithm module;
and step 3: the control unit receives the judgment result of the interface request, and sends a trigger instruction for starting protection to the data protection unit if the request is illegal;
and 4, step 4: the control unit receives the judgment result of the interface address, judges whether the current cryptographic algorithm IP core is in a debugging mode if the address is illegal, and sends a trigger instruction for starting protection to the data protection unit if the current cryptographic algorithm IP core is not in the debugging mode;
and 5: after receiving the trigger instruction of starting protection, the data protection unit calls a random number generation unit in the data protection unit to generate a random number, and carries out scrambling operation on data content in data output from the algorithm module.
The interface module receives a data read or write request from the outside, generates interface request information and sends the interface request information to the request filtering unit, and the request filtering unit judges whether the transmission type, the data bit width, the burst type and the protection type of the interface request information are types supported by the IP core of the cryptographic algorithm, so that an interface request judgment result is generated.
The address filtering unit judges whether the requested interface address information is legal or not, and the illegal type is defined as the address change caused by abnormal use conditions including border crossing of an access address, unauthorized register address and continuous access of adjacent addresses.
The debugging mode of the cryptographic algorithm IP core is only used for chip factory test, and cannot be configured by a common user.
Wherein the random number generated by the data protection unit is replaced once every time data is output.
And the data protection unit outputs the original text of the state content irrelevant to the data safety in the data output of the algorithm module.
The state content comprises various state information including state machine information, error information, busy information and interrupt information of the algorithm.
After receiving a trigger instruction for opening protection, the data protection unit records a state for opening protection through a nonvolatile storage device in the data protection unit, and the state can be cleared only through a debugging mode.
Wherein the data content in the data output from the algorithm module comprises: and operation information including a key, an encryption result, and a decryption result.
The interface module represents a part of the cryptographic algorithm IP core connected with the outside and is used for data interaction with the outside; the algorithm module represents a part of the cryptographic algorithm IP core operation function and is used for realizing the logic functions of key generation, data encryption and identity authentication.
(III) advantageous effects
Compared with the prior art, the invention provides a honeypot scrambling method applied to a cryptographic algorithm IP core, which is used for detecting whether the current cryptographic algorithm IP core is attacked or not during application and returning scrambled data when the current cryptographic algorithm IP core is attacked, so that the security of the cryptographic algorithm IP core is enhanced. The invention has the beneficial effects that when the cryptographic algorithm IP core is attacked, sensitive data such as a protection key and the like are not easy to steal, thereby enhancing the security of the cryptographic algorithm IP core.
Drawings
Fig. 1 is a block diagram showing the overall structure of the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
In order to solve the technical problem, the invention provides a honeypot scrambling method for a cryptographic algorithm IP core, the honeypot technology is a technology for cheating an attacker, and false information is returned when the honeypot module detects the attack, so that the attacker is confused to protect real data.
The honeypot scrambling method is implemented based on a honeypot module, and a cryptographic algorithm IP core acted by the honeypot module comprises the following steps: an interface module and an algorithm module;
as shown in fig. 1, the honeypot module includes: the device comprises a request filtering unit, an address filtering unit, a control unit and a data protection unit, wherein the request filtering unit, the address filtering unit, the control unit and the data protection unit are used for realizing the protection of an IP core of a cryptographic algorithm through the cooperative work of the request filtering unit, the address filtering unit, the control unit and the data protection unit;
the honeypot scrambling method comprises the following steps:
step 1: the request filtering unit receives the interface request information from the interface module, judges whether the current interface request information is legal or not, generates an interface request judgment result and outputs the interface request judgment result to the control unit, and simultaneously sends the interface request information from the interface module to the algorithm module;
step 2: the address filtering unit receives the interface address information requested by the interface module, judges whether the current interface address information is legal or not, generates an interface address judgment result and outputs the interface address judgment result to the control unit, and simultaneously sends the interface address information from the interface module to the algorithm module;
and step 3: the control unit receives the judgment result of the interface request, and sends a trigger instruction for starting protection to the data protection unit if the request is illegal;
and 4, step 4: the control unit receives the judgment result of the interface address, judges whether the current cryptographic algorithm IP core is in a debugging mode if the address is illegal, and sends a trigger instruction for starting protection to the data protection unit if the current cryptographic algorithm IP core is not in the debugging mode;
and 5: after receiving the trigger instruction of starting protection, the data protection unit calls a random number generation unit in the data protection unit to generate a random number, and carries out scrambling operation on data content in data output from the algorithm module.
The interface module receives a data read or write request from the outside, generates interface request information and sends the interface request information to the request filtering unit, and the request filtering unit judges whether the transmission type, the data bit width, the burst type and the protection type of the interface request information are types supported by the IP core of the cryptographic algorithm, so that an interface request judgment result is generated.
The address filtering unit judges whether the requested interface address information is legal or not, and the illegal type is defined as the address change caused by abnormal use conditions including border crossing of an access address, unauthorized register address and continuous access of adjacent addresses.
The debugging mode of the cryptographic algorithm IP core is only used for chip factory test, and cannot be configured by a common user.
Wherein the random number generated by the data protection unit is replaced once every time data is output.
And the data protection unit outputs the original text of the state content irrelevant to the data safety in the data output of the algorithm module.
The state content comprises various state information including state machine information, error information, busy information and interrupt information of the algorithm.
After receiving a trigger instruction for opening protection, the data protection unit records a state for opening protection through a nonvolatile storage device in the data protection unit, and the state can be cleared only through a debugging mode.
Wherein the data content in the data output from the algorithm module comprises: and operation information including a key, an encryption result, and a decryption result.
The interface module represents a part of the cryptographic algorithm IP core connected with the outside and is used for data interaction with the outside; the algorithm module represents a part of the cryptographic algorithm IP core operation function and is used for realizing the logic functions of key generation, data encryption and identity authentication.
In addition, the invention also provides a honeypot module for the cryptographic algorithm IP core, the honeypot technology is a technology for cheating an attacker, and false information is returned when the honeypot module detects the attack, so that the attacker is confused to protect real data.
The cryptographic algorithm IP core acted by the honeypot module comprises: an interface module and an algorithm module;
as shown in fig. 1, the honeypot module includes: the device comprises a request filtering unit, an address filtering unit, a control unit and a data protection unit, wherein the request filtering unit, the address filtering unit, the control unit and the data protection unit are used for realizing the protection of an IP core of a cryptographic algorithm through the cooperative work of the request filtering unit, the address filtering unit, the control unit and the data protection unit;
the request filtering unit is used for receiving the interface request information from the interface module, judging whether the current interface request information is legal or not, generating an interface request judgment result and outputting the interface request judgment result to the control unit, and meanwhile, sending the interface request information from the interface module to the algorithm module;
the address filtering unit is used for receiving the interface address information requested by the interface module, judging whether the current interface address information is legal or not, generating an interface address judgment result and outputting the interface address judgment result to the control unit, and meanwhile, sending the interface address information from the interface module to the algorithm module;
the control unit is used for receiving the judgment result of the interface request, and sending a trigger instruction for starting protection to the data protection unit if the request is illegal;
the control unit is also used for receiving the interface address judgment result, judging whether the current cryptographic algorithm IP core is in a debugging mode if the address is illegal, and sending a trigger instruction for starting protection to the data protection unit if the current cryptographic algorithm IP core is not in the debugging mode;
and the data protection unit is used for calling the random number generation unit in the data protection unit to generate a random number after receiving a trigger instruction for starting protection, and scrambling the data content in the data output from the algorithm module.
The interface module receives a data read or write request from the outside, generates interface request information and sends the interface request information to the request filtering unit, and the request filtering unit judges whether the transmission type, the data bit width, the burst type and the protection type of the interface request information are types supported by the IP core of the cryptographic algorithm, so that an interface request judgment result is generated.
The address filtering unit judges whether the requested interface address information is legal or not, and the illegal type is defined as the address change caused by abnormal use conditions including border crossing of an access address, unauthorized register address and continuous access of adjacent addresses.
The debugging mode of the cryptographic algorithm IP core is only used for chip factory test, and cannot be configured by a common user.
Wherein the random number generated by the data protection unit is replaced once every time data is output.
And the data protection unit outputs the original text of the state content irrelevant to the data safety in the data output of the algorithm module.
The state content comprises various state information including state machine information, error information, busy information and interrupt information of the algorithm.
After receiving a trigger instruction for opening protection, the data protection unit records a state for opening protection through a nonvolatile storage device in the data protection unit, and the state can be cleared only through a debugging mode. If the implementation process of the cryptographic algorithm IP core does not support the internal nonvolatile storage device, the information can be recorded by using the nonvolatile storage device or the key storage space of the chip.
Wherein the data content in the data output from the algorithm module comprises: and operation information including a key, an encryption result, and a decryption result.
The interface module represents a part of the cryptographic algorithm IP core connected with the outside and is used for data interaction with the outside; the algorithm module represents a part of the cryptographic algorithm IP core operation function and is used for realizing the logic functions of key generation, data encryption and identity authentication. The interface module and the algorithm module are functional modules of the cryptographic algorithm IP core, which are not the design provided by the invention, and if the cryptographic algorithm IP core has no honeypot module, the interface module and the algorithm module are directly interconnected. The interface request, the interface address, the interface write data and the interface read data in the interface module, and the data input, data processing and data output part in the algorithm module only represent related functions used when the algorithm module is interconnected with the honeypot module.
Example 1
The working principle and the working flow of the honeypot module for the cryptographic algorithm IP core are as follows:
step 1: the interface module receives an external data reading or writing request, a request filtering unit of the honeypot module judges whether control information such as a transmission type, a data bit width, a burst type and a protection type of the request is a type supported by a cryptographic algorithm IP core, and sends a judgment result to the control unit, and meanwhile sends an original interface request to the algorithm module;
step 2: the address filtering unit of the honeypot module judges whether the requested address information is legal or not, the illegal type is defined as address change caused by abnormal use conditions such as border crossing of an access address, unauthorized register addresses, continuous access of adjacent addresses and the like, the judgment result is sent to the control unit, and meanwhile, the original interface address is sent to the algorithm module;
and step 3: the control unit of the honeypot module receives the judgment result of the request filtering unit, and if the request is illegal, the result of starting protection is sent to the data protection unit; receiving a judgment result of the address filtering unit, if the address is illegal, judging whether the current cryptographic algorithm IP core is in a debugging mode (the debugging mode is only used for chip delivery test and cannot be configured by a common user), and if the current cryptographic algorithm IP core is not in the debugging mode, sending a protection starting result to the data protection unit;
and 4, step 4: the data protection unit of the honeypot module judges whether the data protection unit is in an open protection state or not, when the data protection unit is in the open protection state or receives open protection information of the control unit, a random number generation function in the data protection unit is called to generate a random number, scrambling operation is carried out on data content in data output of the algorithm module (the data content comprises operation information such as a secret key, an encryption result and a decryption result), and the random number is replaced once during each data output; and outputting original text of state contents irrelevant to data safety in the data output of the algorithm module (the state contents comprise state machine information, error information, busy information, interrupt information and other state information of the algorithm).
And 5: once the honeypot module detects an illegal attack, the honeypot module records an open state by using a nonvolatile storage device in the data protection unit, and the open state can be cleared only through a debugging mode. (if the implementation process of the cryptographic algorithm IP core does not support the internal nonvolatile storage device, the information can be recorded using the chip's nonvolatile storage device or key storage space)
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. Honeypot scrambling method for cryptographic IP cores, the honeypot scrambling method being implemented based on a honeypot module, the cryptographic IP core acted on by the honeypot module comprising: an interface module and an algorithm module;
the honeypot module includes: the device comprises a request filtering unit, an address filtering unit, a control unit and a data protection unit, wherein the request filtering unit, the address filtering unit, the control unit and the data protection unit are used for realizing the protection of an IP core of a cryptographic algorithm through the cooperative work of the request filtering unit, the address filtering unit, the control unit and the data protection unit;
the honeypot scrambling method comprises the following steps:
step 1: the request filtering unit receives the interface request information from the interface module, judges whether the current interface request information is legal or not, generates an interface request judgment result and outputs the interface request judgment result to the control unit, and simultaneously sends the interface request information from the interface module to the algorithm module;
step 2: the address filtering unit receives the interface address information requested by the interface module, judges whether the current interface address information is legal or not, generates an interface address judgment result and outputs the interface address judgment result to the control unit, and simultaneously sends the interface address information from the interface module to the algorithm module;
and step 3: the control unit receives the judgment result of the interface request, and sends a trigger instruction for starting protection to the data protection unit if the request is illegal;
and 4, step 4: the control unit receives the judgment result of the interface address, judges whether the current cryptographic algorithm IP core is in a debugging mode if the address is illegal, and sends a trigger instruction for starting protection to the data protection unit if the current cryptographic algorithm IP core is not in the debugging mode;
and 5: after receiving the trigger instruction of starting protection, the data protection unit calls a random number generation unit in the data protection unit to generate a random number, and carries out scrambling operation on data content in data output from the algorithm module.
2. The honey pot scrambling method for the cryptographic algorithm IP core according to claim 1, wherein the interface module receives a data read or write request from outside, generates interface request information and sends the interface request information to the request filtering unit, and the request filtering unit judges whether a transmission type, a data bit width, a burst type, and a protection type of the interface request information are types supported by the cryptographic algorithm IP core, thereby generating an interface request judgment result.
3. The honey pot scrambling method for cryptographic algorithm IP cores of claim 1, wherein the address filtering unit judges whether the requested interface address information is legal, and the illegal type is defined as an address change occurring in an abnormal use case including an access address out-of-bounds, an unauthorized register address, a consecutive access neighbor address.
4. The honey pot scrambling method for cryptographic algorithm IP cores of claim 1, wherein the debugging mode of the cryptographic algorithm IP core is only used for chip factory test and cannot be configured by a common user.
5. The honey pot scrambling method for cryptographic algorithm IP cores of claim 1, wherein the random number generated by the data protection unit is replaced with a random number every time data is output.
6. The honey pot scrambling method for cryptographic algorithm IP cores of claim 1, characterized in that the data protection unit performs textual output of state content of the data output of the algorithm module that is not related to data security.
7. The honey scrambling method for cryptographic algorithm IP cores of claim 6, characterized in that the status content comprises various status information including state machine information, error information, busy information, interrupt information of the algorithm.
8. The honey scrambling method for cryptographic algorithm IP cores of claim 1, characterized in that the data protection unit, after receiving a trigger instruction to turn on protection, will also record the state of turning on protection through its internal non-volatile storage device, which can only be cleared through debug mode.
9. The honey scrambling method for cryptographic algorithm IP cores of claim 1, wherein the data content in the data output from the algorithm module comprises: and operation information including a key, an encryption result, and a decryption result.
10. The honey pot scrambling method for cryptographic algorithm IP core of claim 1, wherein the interface module represents a portion of the cryptographic algorithm IP core connected with the outside for data interaction with the outside; the algorithm module represents a part of the cryptographic algorithm IP core operation function and is used for realizing the logic functions of key generation, data encryption and identity authentication.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911131143.5A CN110912881B (en) | 2019-11-19 | 2019-11-19 | Honeypot scrambling method for cryptographic algorithm IP core |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911131143.5A CN110912881B (en) | 2019-11-19 | 2019-11-19 | Honeypot scrambling method for cryptographic algorithm IP core |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110912881A true CN110912881A (en) | 2020-03-24 |
| CN110912881B CN110912881B (en) | 2022-04-05 |
Family
ID=69817849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911131143.5A Active CN110912881B (en) | 2019-11-19 | 2019-11-19 | Honeypot scrambling method for cryptographic algorithm IP core |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110912881B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110113392A1 (en) * | 2009-11-09 | 2011-05-12 | Rajat Subhra Chakraborty | Protection of intellectual property (ip) cores through a design flow |
| CN104182696A (en) * | 2014-08-15 | 2014-12-03 | 浪潮电子信息产业股份有限公司 | Design method based on Avalon interface for IP core of AES algorithm |
| CN104484583A (en) * | 2014-12-15 | 2015-04-01 | 天津大学 | Protection method of IP (internet protocol) core with determined validity |
| EP3214613A1 (en) * | 2016-03-01 | 2017-09-06 | Siemens Aktiengesellschaft | Protecting the content of different ip cores in a system on chip using pufs |
| US20180349650A1 (en) * | 2017-06-06 | 2018-12-06 | Intel Corporation | Security policy management for a plurality of dies in a system-on-chip |
-
2019
- 2019-11-19 CN CN201911131143.5A patent/CN110912881B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110113392A1 (en) * | 2009-11-09 | 2011-05-12 | Rajat Subhra Chakraborty | Protection of intellectual property (ip) cores through a design flow |
| CN104182696A (en) * | 2014-08-15 | 2014-12-03 | 浪潮电子信息产业股份有限公司 | Design method based on Avalon interface for IP core of AES algorithm |
| CN104484583A (en) * | 2014-12-15 | 2015-04-01 | 天津大学 | Protection method of IP (internet protocol) core with determined validity |
| EP3214613A1 (en) * | 2016-03-01 | 2017-09-06 | Siemens Aktiengesellschaft | Protecting the content of different ip cores in a system on chip using pufs |
| US20180349650A1 (en) * | 2017-06-06 | 2018-12-06 | Intel Corporation | Security policy management for a plurality of dies in a system-on-chip |
Non-Patent Citations (4)
| Title |
|---|
| JOHANNASEP´ULVEDA: ""Towards Protected MPSoC Communication for Information Protection against a Malicious NoC"", 《INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE》 * |
| 张龙飞: ""IPSec协议下加密IP核的设计与FPGA实现"", 《万方》 * |
| 范明俊: ""一种安全可靠性高的全新IP 核保护方法"", 《微电子学》 * |
| 韩军: ""信息安全芯片的防御攻击技术研究"", 《万方》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110912881B (en) | 2022-04-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108055133B (en) | Key security signature method based on block chain technology | |
| CN104392188B (en) | A kind of secure data store method and system | |
| EP3314808B1 (en) | Binding a trusted input session to a trusted output session | |
| CN105260663B (en) | A kind of safe storage service system and method based on TrustZone technologies | |
| TW382681B (en) | Securely generating a computer system password by utilizing an external encryption algorithm | |
| CN104951409B (en) | A kind of hardware based full disk encryption system and encryption method | |
| CN101533445B (en) | Microprocessor device for providing secure execution environment and method for executing secure code thereof | |
| TWI471754B (en) | Support for secure objects in a computer system | |
| KR100970040B1 (en) | A secure terminal, a routine and a method of protecting a secret key | |
| CN107908574B (en) | Safety protection method for solid-state disk data storage | |
| CN101795261A (en) | Information protection system and method based on mobile data safety | |
| CN103440462A (en) | Embedded control method for improving security and secrecy performance of security microprocessor | |
| JP2005346182A (en) | Information processor, tamper resistant method, and tamper resistant program | |
| CN101727558A (en) | Method for clearing password of computer, computer and server | |
| CN110765470A (en) | Method and device for realizing safety keyboard, computer equipment and storage medium | |
| CN110837634A (en) | Electronic signature method based on hardware encryption machine | |
| CN110912881B (en) | Honeypot scrambling method for cryptographic algorithm IP core | |
| CN110837662B (en) | Honeypot module for cryptographic algorithm IP core | |
| CN102034040A (en) | Log implementation method in encryption card | |
| US8095805B2 (en) | Security flash memory, data encryption device and method for accessing security flash memory | |
| CN102880818A (en) | Software protection method | |
| CN105828323A (en) | Privacy protection method and system for common database of Android mobile phone | |
| CN111563269A (en) | Sensitive data security protection method and system based on shadow system | |
| CN114048502B (en) | Lightweight trusted channel and communication control method thereof | |
| KR100740658B1 (en) | A Method for Handling Crypto-Algorithm and a Crypto-Module, Supporting Polymorphism and Tamper-proof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |