CN110911431A

CN110911431A - Shallow trench textured areas and related methods

Info

Publication number: CN110911431A
Application number: CN201911004626.9A
Authority: CN
Inventors: H·哈达; J·蒋
Original assignee: SiOnyx LLC
Current assignee: SiOnyx LLC
Priority date: 2013-06-29
Filing date: 2013-11-19
Publication date: 2020-03-24
Also published as: CN105849907A; CN105849907B

Abstract

A photosensitive device and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having a plurality of doped regions forming at least one junction; a textured region coupled to the semiconductor layer and interacting with electromagnetic radiation. The textured region may form a series of shallow trench isolation features.

Description

Shallow trench textured areas and related methods

The application is a divisional application, and the parent application is an application with the invention name of 'shallow groove texture region and related method' and the application number of 201380079262.5, which is submitted in 2013 at 11 and 19 th (priority date: 2013 at 6 and 29 th).

Background

Description of the background

Semiconductor materials with optical interactions are a major innovation. Silicon imaging devices are used in different technologies, such as digital cameras, optical mice, video cameras, mobile phones, etc. Charge-coupled devices (CCDs) are widely used in digital imaging and are later developed into metal-oxide semiconductor (CMOS) imagers with improved performance. Many conventional CMOS imagers utilize Front Side Illumination (FSI). In this case, the electromagnetic radiation is projected onto the semiconductor surface containing the CMOS devices and circuits. Back-illuminated (BSI) CMOS imagers are also used, and in many designs, electromagnetic radiation is projected onto a semiconductor surface opposite the CMOS devices and circuitry. CMOS sensors are typically fabricated from silicon and are capable of phase-shifting visible incident light to photocurrent and ultimately to digital images. Although silicon-based techniques for detecting projected electromagnetic radiation in the infrared have problems, because silicon is an indirect bandgap semiconductor with a bandgap of about 1.1 eV. Thus, the absorption of electromagnetic radiation with wavelengths longer than 1100nm is very low in silicon.

Disclosure of Invention

The present disclosure provides an optoelectronic device having enhanced light absorption characteristics, including systems incorporating the device and various related methods. In one aspect, for example, optoelectronic devices with enhanced absorption of electromagnetic radiation are provided. The apparatus may include a semiconductor layer coupled to a support substrate; and a set of shallow trench isolation surface features located between the semiconductor layer and the support substrate, the surface features positioned to interact with electromagnetic radiation passing through the semiconductor layer. In one aspect, the semiconductor layer is monocrystalline silicon. In another aspect, a device layer is coupled to the semiconductor layer opposite the surface feature.

In an aspect, a first bonding layer may be coupled between the semiconductor layer and the support substrate. While various configurations are contemplated, in one aspect, a first adhesive layer can be coupled between the support substrate and the surface feature. In another aspect, a second bonding layer may be positioned between the first bonding layer and the surface feature. In another aspect, a reflector layer can be disposed between the first and second adhesive layers.

Surface features can have various configurations and can be formed at various locations between the semiconductor layer and the semiconductor support. For example, in one aspect, the surface features may be formed on the support substrate. In another aspect, the surface features can be formed in the semiconductor layer. Further, in an aspect, the surface features may be arranged according to a preset pattern. In a particular aspect, the predetermined pattern is an at least substantially uniform grid. In a particular aspect, the predetermined pattern is a non-uniform arrangement. Further, in an aspect, the surface features can have an at least substantially uniform height. In another aspect, the surface features are non-uniform in height.

In addition, various structural arrangements are contemplated. For example, in one aspect, the device may be structurally configured as a front-lit optoelectronic device. In another aspect, the device may be structurally configured as a backlit optoelectronic device.

In another aspect, a method of making an optoelectronic device is provided. The method may include the steps of generating a set of surface features in the semiconductor layer using a shallow trench isolation etch; and bonding the set of surface features between the support substrate and the semiconductor layer. In another aspect, the step of generating the set of surface features can further include generating the set of surface features on at least a portion of a surface of the semiconductor layer. In another aspect, the step of generating the set of surface features can further include generating the set of surface features on at least a portion of the surface of the support substrate. Further, in one aspect, bonding the set of surface features between the support substrate and the semiconductor layer can further include depositing a first bonding layer on the semiconductor layer; and bonding the first bonding layer to a second bonding layer deposited on the support substrate. In some aspects, a reflector layer may be deposited on at least one of the first adhesive layer or the second adhesive layer prior to bonding the semiconductor layer to the support substrate. In a further aspect, the method can include thinning the semiconductor layer opposite the support substrate to a thickness of 1 micron to 10 microns to create an original thin surface; and forming a device layer on the thin surface. The semiconductor may then be further processed to form the desired photovoltaic device.

Brief description of the drawings

For a further understanding of the nature and advantages of the present disclosure, reference should be made to the following examples and accompanying drawings.

FIG. 1 is a wavelength function showing data of light absorption of textured silicon compared to standard silicon according to one embodiment of the present disclosure;

FIG. 2 is a cross-sectional view illustrating an image sensor according to another embodiment of the present disclosure;

FIG. 3 is a cross-sectional view illustrating an image sensor according to another embodiment of the present disclosure;

FIG. 4 is a cross-sectional view illustrating a textured layer of a substrate according to another embodiment of the present invention;

FIG. 5 is a cross-sectional view illustrating a textured layer of a substrate according to another embodiment of the invention; and

FIG. 6 is a cross-sectional view illustrating a textured area of a substrate according to another embodiment of the present layer.

Detailed description of the invention

Before the present disclosure is described herein, it is to be understood that this disclosure is not limited to the particular structures, processes, or materials disclosed herein and that equivalents thereof may be extended by those of ordinary skill in the relevant art. It is also to be understood that the terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting.

Definition of

The following terms will be used with the definitions below.

It should be noted that the singular forms "a," "an," and "the" in this specification and the appended claims include the plural forms unless the context clearly discloses otherwise. Thus, for example, reference to "a dopant" includes one or more of that dopant, and reference to "the layer" includes reference to one or more of that layer.

As used herein, the terms "light" and "electromagnetic radiation" are used interchangeably and may relate to electromagnetic radiation in the ultraviolet, visible, near infrared and infrared spectrums. The term may more broadly include electromagnetic radiation, such as radio waves, microwaves, X-rays, and gamma rays. Thus, the term "light" is not limited to electromagnetic radiation in the visible spectrum. Many of the examples of light described herein relate particularly to electromagnetic radiation in the visible and infrared (and/or near infrared) spectra. For the purposes of this disclosure, the region of visible wavelengths is considered to be about 350nm to 800nm, and the non-visible wavelengths are considered to be longer than about 800nm or shorter than about 350 nm. Furthermore, the infrared spectrum is considered to include portions of the near infrared spectrum including wavelengths of about 800 to 1000nm, portions of the short wavelength infrared spectrum including wavelengths of about 1100nm to 3 microns, and portions of the medium long wavelength infrared (or thermal infrared) spectrum including wavelengths greater than 3 microns to 30 microns. Unless otherwise indicated, these are generally referred to collectively as the "infrared" portion of the electromagnetic spectrum.

As used herein, the term "detection" refers to the induction, absorption, and/or collection of electromagnetic radiation.

As used herein, the term "back-side illumination" relates to a structural design of a device in which electromagnetic radiation is projected onto a surface of a semiconductor material, which is opposite to a surface containing circuitry of the device. In other words, the electromagnetic radiation is transmitted through the semiconductor material before contacting the device circuitry.

As used herein, the term "front side illumination" relates to a structural design of a device in which electromagnetic radiation is projected onto a surface of a semiconductor material, the surface containing device circuitry. In other words, the electromagnetic radiation impinges thereon and passes through the device circuitry area before contacting the semiconductor material.

As used herein, the term "absorptivity" refers to the grading of the projected electromagnetic radiation absorbed by a material or device.

As used herein, the terms "texture layer" and "textured surface" are used interchangeably and refer to a surface having a topology that varies from a nanometer to a micrometer scale surface. The surface topology may consist of various known STI techniques. It should be noted that laser ablation techniques are specifically abandoned in at least one aspect. The surface characteristics may vary depending on the materials and technology employed, and in one aspect, the surface may comprise micron-scale structures (e.g., about 1 μm to 10 μm). In another aspect, the surface can include nano-scale and/or micro-scale structures of about 5 μm to 10 μm. In another aspect, the surface structure can be from about 100 μm to 1 micron. Various standards may be used to measure the structure dimensions. For example, for a cone-type structure, the above ranges are measured from the top of the structure to the trough formed between the structure and the adjacent structure. For structures like nanopores, the above ranges may be approximate diameters. Furthermore, the surface structures may be spaced apart from each other at different average distances. In one aspect, adjacent structures may be spaced apart by a distance of about 50nm to 2 μm. The spacing may be from a center point of one structure to a center point of an adjacent structure.

As used herein, the term "substantially" refers to a complete or nearly complete degree or degree of an action, property, feature, state, structure, item, or result. For example, an object is "substantially" enclosed, meaning that the object is either completely enclosed or almost completely enclosed. The exact allowable deviation from absolute completeness may sometimes depend on the particular context. However, in general, near-unity will have the same result if absolute and full completions are obtained. The use of "substantially" is equally applicable when used in a negative sense to refer to the absence of an action, property, feature, state, structure, item, or result that is complete or nearly complete. For example, a combination of "substantially free" of particles either completely lacks particles, or almost completely lacks particles, which acts as if it completely lacked particles. In other words, when a combination is "substantially free of" components or elements, items may still be actually contained as long as the measurement is not affected therein.

As used herein, the term "about" is used to provide flexibility to the end points of a numerical range by providing that known values can be "above" or "below" the end points.

As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, an individual member of such list should not be construed as an equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary.

The degree of aggregation, amount, and other numerical data may be expressed or provided in a range format. It is to be understood that such a range format is used merely for convenience and brevity and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical range and sub-range is explicitly recited. As a list, a numerical range of "about 1 to 5" should be interpreted to include not only the explicitly recited values of about 1 to 5, but also include individual values and sub-ranges within the indicated range. Thus, independent values included within this numerical range are, for example, 2,3, and 4 and subranges such as 1 to 3, 2 to 4, and 3 to 5, etc., as well as 1,2,3,4, and 5, individually.

This same principle applies to ranges reciting only one numerical value, either similarly minimum or maximum. Furthermore, the interpretation is not dependent on the magnitude of the range or the described characteristics when applied.

The disclosure of the invention

Conventional silicon photodetection imagers have limited light absorption/detection properties. For example, the silicon-based detector is generally transparent to infrared light, particularly with a thin silicon layer. In some cases, other materials, such as indium gallium arsenide InGaAs, may be used to detect infrared light having wavelengths greater than about 1000nm, with silicon still being used to detect wavelengths within the visible spectrum (e.g., visible, 350nm to 800 nm). Conventional silicon materials require a large number of optical path lengths to detect photons from electromagnetic radiation having wavelengths longer than 700 nm. As a result, visible light may be absorbed at shallower silicon depths, and the absorbance at longer wavelengths (e.g., 900nm) is weaker at silicon at standard wafer depths (e.g., about 750 μm). The thickness of the silicon layer is increased to allow for longer wavelength absorption, thus greatly increasing the thickness of the photodetection imager.

In accordance with some aspects of the present disclosure, optoelectronic devices exhibit increased absorption of light due to an increased effective optical path length for longer wavelengths of light as compared to conventional devices. The absorption depth in a conventional silicon detector is the depth of silicon, where the radiation intensity is reduced to about 36% of the value at the semiconductor surface. The increased photon optical path length of the silicon material of the present invention results in a significant reduction in absorption depth, or a significant or effective reduction in absorption depth. For example, the effective absorption depth of silicon may be reduced so that these longer wavelengths may be absorbed in a silicon layer less than 850 microns thick. In other words, by increasing the optical path length, these devices can absorb longer wavelengths (e.g., greater than 1000nm for silicon) within thinner silicon materials. In addition to absorption of light having longer wavelengths in thin silicon materials (e.g., less than 30 microns thick compared to 700 microns thick), the rate or speed of reaction can also be increased by using the thin materials.

The optoelectronic devices of the present disclosure may be Front Side Illumination (FSI) or Back Side Illumination (BSI) devices. In a typical FSI imager, the projected light enters the semiconductor device through a first pass of transistors and metal circuitry. However, light may be dispersed in transistors and circuits before entering the light sensing portion of the imager, thus causing optical loss and noise. The lens may be arranged in the upper part of the FSI pixel and direct and focus the projection light to the light sensing active area of the device, thus avoiding, at least partly, electrical circuitry. Various lenses and lens configurations are contemplated, however, in one aspect the lenses may be microlenses.

In another aspect, the BSI imager is configured so that the projected light enters the device through a photosensitive region opposite the circuitry and is mostly absorbed before reaching the circuitry, thus greatly reducing dispersion and/or noise. BSI design also enables the imager to have greater sensitivity, smaller pixel structures, and high fill ratios. Additionally, it should be understood that devices according to the present disclosure, whether FSI or BSI, may be incorporated into a Complementary Metal Oxide Semiconductor (CMOS) imager structure, or a Charge Coupled Device (CCD) imager structure.

In general, the present disclosure provides various optoelectronic devices, such as, for example, broadband photodiodes, pixels, and imagers capable of detecting visible light as well as infrared electromagnetic radiation, including, but not limited to, related methods of making the devices. In certain aspects, for example, optoelectronic devices are provided having enhanced absorption of electromagnetic radiation. The apparatus may include a semiconductor layer coupled to a support substrate and a set of shallow trench isolation surface features positioned between the semiconductor layer and the support substrate, the surface features positioned to interact with electromagnetic radiation passing through the semiconductor layer.

Thus, it has been found that the set of shallow trench isolation surface features, positioned in a structurally appropriate manner, can greatly increase the light absorption of the silicon material. As shown in fig. 1, for example, in the electromagnetic spectrum range of at least about 700nm to 1100nm, the textured regions may increase the light absorption of silicon compared to non-textured silicon.

As can be seen in FIG. 2, for example, the FSI device 200 is shown having a semiconductor layer 202 coupled to a support substrate 204, wherein the semiconductor layer may include one or more doped regions 206,208 that form at least one junction. The textured layer 210 includes one or more STI surface features positioned between the semiconductor layer 202 and the support substrate 204. The circuit layer 212 is coupled to the semiconductor layer 202 opposite the support substrate 204. Light 214 is shown striking device 200 and passing through circuit layer 212 before contacting semiconductor layer 202. The light 214 is not absorbed and passes through the semiconductor layer 202 to contact the textured layer 210 and is redirected back to the semiconductor layer 202, thereby causing the light to be absorbed in subsequent passes. Thus, the textured layer 210 effectively increases the optical path length of the light 214 as it passes through the device. In one aspect, the semiconductor layer can be monocrystalline silicon.

In fig. 3, a BSI device 300 is shown having a semiconductor layer 302 coupled to a support substrate 304, where the semiconductor layer may include one or more doped regions 306,308 that form at least one junction. In this case, the support substrate 304 may be a circuit layer or a bulk substrate including a circuit layer. The textured layer 310 includes one or more surface features positioned between the semiconductor layer 302 and the support substrate 304. Light 312 is shown impinging on device 300 and not contacting any circuit elements that may be positioned in or on support substrate 304, thereby passing through semiconductor layer 302. Light 312 is not absorbed and passes through semiconductor layer 302 to contact texture layer 310 and is redirected back into semiconductor layer 302. As with the FSI device shown in fig. 2, the textured layer 310 effectively increases the optical path length of the light 312 as it passes through the device. In one aspect, the semiconductor layer can be monocrystalline silicon.

Depending on the device, the multiple doped regions for FSI and BSI may have the same doping profile or different doping profiles. Further, any number or configuration of doped regions is considered to be within the present scope. In some aspects, the semiconductor layer may be doped and, therefore, may be considered a doped region.

In addition, the device may include Deep Trench Isolation (DTI), separate imagers and provide light capture functionality. In some aspects, in addition to supporting the substrate, the apparatus can include a silicon handle wafer that facilitates handling of the apparatus. In some aspects, the support substrate may be a silicon handle wafer. One technique for coupling a silicon handle wafer to a semiconductor layer includes oxide bonding. Further details regarding the substrate, bonding, and various imager details are shown in U.S. patent application No. 13/069,135, which is incorporated herein by reference.

According to some aspects of the present disclosure, an optoelectronic device may include a photodiode or pixel capable of absorbing electromagnetic radiation within a given range of wavelengths. The imager may be a Passive Pixel Sensor (PPS), an Active Pixel Sensor (APS), a digital pixel sensor imager (DPS), or the like. The device may also be structurally configured as a three or four transistor active pixel sensor (3T APS or 4T APS). In addition, devices having more than 4 transistors are also within the scope. The device may also include a photodiode structure for a CMOS imager. Also, optoelectronic devices may be used for time of flight (TOF) applications, as well as various structured light applications. It is also contemplated that the device may also be configured as a rolling shutter or global shutter readout device.

In some aspects, the device may include a passivation layer between the textured layer and the doped region. In some aspects, the passivation layer may be doped to form a surface region, and is described in detail below. It should be noted that with or without passivation regions, the textured region may be located on the light-projecting side of the semiconductor material, the side of the semiconductor material opposite the light-projecting side, or both the light-projecting side and the light-projecting side opposite the side. In addition, the apparatus may further include an electrical transmission element coupled to the semiconductor layer and operable to transmit an electrical signal from the doped region. Further, the electrical transmission element may include various devices including, but not limited to, a transistor, a sensing node, a transmission gate, a transfer electrode, and the like.

As described, the textured layer is comprised of a plurality of surface features, wherein the surface features are formed in an array or grouping across an interface between the semiconductor layer and the support substrate. In some aspects, the textured region may cover the entire interface between the semiconductor layer and the support substrate, while in other aspects, the textured region may cover only a portion of the interface between the semiconductor layer and the support substrate. For example, in one aspect, the textured layer may cover the interface between the materials, at least in the region where light will contact the interface through the semiconductor layer. In another aspect, the textured layer may cover the interface between the materials only in areas where light passing through the semiconductor layer will contact the interface. Thus, it should be understood that the footprint of the textured layer may depend on the design of the device, as well as the pattern required for light capture and/or light redirection. It is therefore intended that the scope of the present disclosure is not limited by the extent to which the textured layer is included.

Further, in some aspects, one or more intermediate layers may be present between the semiconductor layer and the support substrate. The layer may be useful for promoting adhesion, for reflecting light, for various other purposes. In an aspect, for example, one or more bonding layers may be utilized to facilitate bonding of the semiconductor layer to the support substrate. In this case, applying the first adhesive layer to the semiconductor layer and the second adhesive layer may be advantageous for the support substrate as an adhesive mechanism. The bonding layer may include a material capable of bonding between the support substrate and the semiconductor layer. Non-limiting examples may include silicon oxide, silicon nitride, amorphous silicon, and the like. The thickness of a given bonding layer may vary depending on the manufacturing technique used and the preference of the designer. However, in one aspect, the bonding layer may be thick enough to facilitate bonding and thin enough to minimize waveguide effects within the device. In another aspect, the bonding layer can have a thickness from 30nm to 3 microns. In another aspect, the bonding layer can have a thickness from 40nm to 2 microns.

The position of the texture layer may be influenced by the coupled support substrate and the semiconductor layer, as well as the position at which the texture layer is formed. In an aspect, the texture layer may be formed within or on the semiconductor layer. In another aspect, the textured layer may be formed in or on the support substrate. For the case where a textured layer is formed in or on the semiconductor layer, one or more tie layers may be coupled between the support substrate and the textured layer. If two or more adhesive layers are used, a first adhesive layer may be formed on the texture layer, a second adhesive layer may be formed on the support substrate, and then the first and second adhesive layers may be bonded together.

For the case where the texture layer is formed in or on the support substrate, one or more bonding layers may be coupled between the semiconductor layer and the texture layer. For example, in an aspect, one or more adhesive layers may be coupled between the support substrate and the surface feature. If two or more adhesive layers are used, a first adhesive layer can be formed on the textured layer, a second adhesive layer can be formed on the semiconductive layer, and then the first and second adhesive layers can be bonded together.

As described, the light reflecting layer can be placed between any two layers or materials referenced above. For example, in one aspect, a reflective layer may be applied to one side of the texture layer. In another aspect, a reflective layer may be applied to either side of the adhesive layer. In a particular aspect, a reflective layer can be positioned between the first and second adhesive layers. The reflective layer may comprise any material capable of returning reflected light back to the semiconductor layer. Non-limiting examples may include metals, ceramics, oxides, glasses, distributed bragg reflector stacks, and the like, including alloys and compositions.

The surface features of the textured layer may be made by any process that is capable of being etched in a repeatable and predictable manner. In one aspect, however, the surface features may be formed by any number of Shallow Trench Isolation (STI) techniques. Such fabrication techniques are known and have previously been used to fabricate electrically isolated regions between circuit elements. Thus, the implementation is utilized at the edge of the circuit element. Although, the present scope is directed to creating a set of surface features that interact with light within a location. Through this interaction, light may be redirected, diffused, focused, or otherwise manipulated by the array of surface features.

In addition, STI techniques can be used to form surface features having various shapes, patterns, etc. For example, in one aspect, the surface features may be arranged in an array according to a predetermined pattern. In a particular aspect, the predetermined pattern may be a uniform or substantially uniform grid. Furthermore, the predetermined pattern may be an organized, ordered, or periodic pattern. In another aspect, the predetermined pattern may be a non-uniform or substantially non-uniform pattern. The surface feature array pattern may also be disordered, quasi-periodic, random, and the like.

As described, the textured layer may function to diffusely reflect light, redirecting light, and thereby increase the quantum efficiency of the device. In some cases, a portion of the light contacts the textured layer through the semiconductor layer. The surface features of the textured layer are beneficial for increasing the effective optical path length of the semiconductor layer. The surface features may be on the micro-scale and/or nano-scale and may be any shape or structure formed by STI techniques. Non-limiting examples of shapes and configurations may include cones, pillars, pyramids, inverted features, trenches, gratings, protrusions, and the like, including combinations thereof. In addition, the texture layer may be tuned for a particular wavelength or range of wavelengths, as may factors such as feature size, specifications, material type, dopant profile, texture location, etc. of operation. In an aspect, the tuning device may allow a particular compensation or range of wavelengths to be absorbed. In another aspect, the tuning device may cause a particular wavelength or range of wavelengths to be reduced or eliminated by filtering.

According to some aspects of the present disclosure, the textured layer may allow the semiconductor layer to undergo multiple light transmissions within the device, particularly at longer wavelengths (i.e., infrared). Internal reflection can increase the effective optical path length, allowing silicon-like materials to absorb light at thicknesses less than standard silicon. As described, this increases the effective optical path length of the electromagnetic radiation in the silicon, increasing the quantum efficiency of the device, resulting in an improved signal to noise ratio.

The material used to make the textured layer may depend on different designs of the device and the desired characteristics. Thus, any material that may be utilized in the construction of the textured regions is considered within the present scope. In an aspect, the textured region can be formed directly on the semiconductor layer (e.g., silicon epitaxial layer). In another aspect, additional materials may be deposited on the semiconductor layer to support formation of the textured layer. Non-limiting examples of materials include semiconductor materials, dielectric materials, silicon, polysilicon, amorphous silicon, transparent conductive oxides, and the like, including composite materials and combinations thereof. In a particular aspect, the textured layer can be a textured polysilicon layer. Thus, a polycrystalline layer may be deposited on a semiconductor layer, either directly or on an intermediate passivation layer, and then textured to form textured regions. In another aspect, the textured layer may be a textured dielectric layer. In this case, the texture layer may be a portion of a dielectric layer disposed on the semiconductor layer forming the passivation region. In another aspect, the textured layer may be a transparent conductive oxide or another semiconductor material. In the case of a dielectric layer, the textured layer may be a textured portion of the passivation layer, or the textured layer may be formed from other dielectric materials deposited on the passivation layer.

Different methods may be used to form the STI features and any shallow trench formation technique is considered to be within the scope. It should be noted that, in one aspect, texturing techniques involving laser ablation are expressly excluded from the present scope.

In some cases, the texture layer may be formed by using pattern masking and photolithography, followed by etching to define a particular structure or pattern. In an aspect, STI techniques may be used to form textured regions. Various STI techniques are performed, and any such technique is considered to be within the present scope. In one non-limiting example, an oxide material is deposited over the material to etch the shallow trench. A uniform coating of nitride material is deposited over the oxide material and then used as a mask by a patterned coating of resist material. Thus, the pattern of masking will define the pattern of future texture regions. Any etching process may be applied to the entire layered material. As a result, areas of the layered material under the resist are protected from etching, while areas of the layered material not under the resist are etched in the process. This process is continued to create shallow trenches (or holes) that are etched in the unprotected areas between the resist materials, through the nitride material, the oxide material, and into the substrate. Following the etching of the shallow trench, the resist material may be removed by any suitable process. It should be noted that although the term "shallow trench" is used to describe the etching process, the etching pattern results are not limited to trenches, but also include holes, pits, cones, etc.

In some aspects, the etched areas may be left as open spaces. In other aspects, further processing may be performed to fill the etched area. For example, oxide material may be deposited on both sides and bottom of the trench, similar to an oxide layer. Such may be deposited by a thermal oxidation process, direct oxide deposition, or any other useful process. Once the etched areas are sufficiently filled, the resulting surface can be further processed by techniques such as CMP processing, and then, once exposed, the nitride layer can be removed.

In another aspect, the etched region may be highly doped along the sidewalls and/or bottom with a dopant profile, creating a surface region. The back surface region may act to impede the movement of photogenerated carriers from the junction to the textured layer and accordingly tailor the corresponding dopant profile. The use of a back surface region in the etched region may be used to electrically passivate the area around the textured layer.

The surface features can have a variety of configurations, structures, and sizes, depending on the desired characteristics of the final device. In one aspect, for example, as shown in fig. 4, surface features 402 are formed within a material layer 404, e.g., a semiconductor layer. The surface features in this case are uniformly arranged in a uniform grid pattern, constituting a series of spaces or holes 406 and lines 408 or posts. Various uniform grid patterns are contemplated and, in one aspect, the pattern may include uniform spaces surrounding the series of pillars by spaces or vice versa depending on whether the pattern is viewed from the top or bottom of the etched material. In another aspect, the uniform grid pattern may include a series of lines, surrounding a series of evenly spaced intervals, or holes cut between the lines, or vice versa.

Further, as described, the etched pattern of surface features may be a pre-set non-uniform pattern. As shown in fig. 5, for example, the spaces 506 etched into the material layer 504 are of substantially the same size and shape, and the lines or pillars 508 are of different widths. Fig. 6 shows that the etch pattern is different for the spaces 606 and the lines or pillars 608. It should be noted that various etch patterns are contemplated, and the scope should not be limited thereto. With respect to non-uniform patterns, in some aspects, the pattern can be random, or lines or pillars, spaces, or both.

In addition to the pattern being formed by the STI process, the depth of the etch may also have an effect on light absorption. For example, in one aspect, the surface features can have a uniform or substantially uniform thickness or height. While the depth or height may vary depending on the use and design of the device, in one aspect, the height or depth may be about 50nm to 2 microns. It should be noted that in standard STI processing, the process depth is about 0.35 microns, which is also considered to be within the present range. In another aspect, the surface features may have non-uniform depths or heights, thereby diversifying across the surface of the textured layer. In some cases, the variation in depth may be random, and in other cases non-random, depending on the design requirements of the device. In one aspect, the depth or height may be about 50nm to 2 microns. In some aspects, discrete degrees of depth may be utilized. For example, in one aspect, one level may have a depth of 0.35 microns, while another level may have a depth of 0.7 microns. By using different masks, levels of different depths can be obtained. Similarly, subsequent levels may be etched to create a third level, a fourth level, or more. It should be noted that in some aspects, the etch level may have a thickness of about 50nm to 2 microns.

As described, various devices may exhibit increased absorption compared to conventional photosensitive devices, according to some aspects of the present disclosure. For example, according to some aspects of the present disclosure, the active semiconductor layer has a thickness of about 1 to 10 microns, and the absorption characteristics may be as follows: in one aspect, the semiconductor layer may absorb about 60% to 80% of the projected 700nm light; in another aspect, the semiconductor layer may absorb about 40% to 60% of the projected 850nm light; while on the other hand, the semiconductor layer may absorb about 25% to 40% of the projected 940nm light; in another aspect, the semiconductor layer may absorb about 15% to 30% of the projected 1000nm light; on the other hand, the semiconductor layer may absorb about 5% to 10% of the projected 1064nm light. Further, according to some aspects of the present disclosure, depending on the structure, the device may exhibit an External Quantum Efficiency (EQE) of about 1% to 5%, less than the absorption values described above for a given wavelength of light. Further note that the device of the present disclosure has at least approximately the same dark current as a standard EPI device without textured areas.

Although the present disclosure focuses on silicon materials, it should be understood that various semiconductor materials are also contemplated for use and should be considered within the present scope. Non-limiting examples of such semiconductor materials can include group iv element materials, compounds and alloys composed of group ii and group iii element materials, compounds and alloys composed of group iii and group v element materials, and combinations thereof. More specifically, exemplary group iv element materials can include silicon, carbon (e.g., diamond), germanium, and combinations thereof. Various example combinations of group iv element materials may include silicon carbide (SiC) and silicon germanium (SiGe). In a particular aspect, the semiconductor material may be or include silicon. Example silicon materials can include amorphous silicon (a-Si), microcrystalline silicon, polycrystalline silicon, and single crystal silicon, among other crystal types. In another aspect, the semiconductor material may include at least one of silicon, carbon, germanium, aluminum nitride, gallium nitride, indium gallium arsenide, aluminum gallium arsenide, and combinations thereof. In another aspect, the semiconductor material may comprise any material useful in fabricating imagers, including Si, SiGe, InGaAs, and the like, including combinations thereof.

The silicon semiconductor layer may be of any thickness that allows for electromagnetic radiation detection and conversion functions, and thus any such thickness of silicon material is considered to be within the present scope. In some aspects, the textured layer increases the efficiency of the device, e.g., the silicon material may be thinner than before. The thickness of the silicon material is reduced, reducing the amount of silicon required to fabricate the device. In one aspect, for example, the silicon material has a thickness of about 500nm to 50 μm. In another aspect, the silicon material has a thickness less than or equal to about 100 μm. In another aspect, the silicon material has a thickness of about 1 μm to 10 μm. In another aspect, the silicon material may have a thickness of about 5 μm to 50 μm. In another aspect, the silicon material may have a thickness of about 5 μm to 10 μm.

Various doping materials are contemplated for forming the plurality of doped regions and creating surface regions in the shallow trench regions, and any dopant that may be used in this process is considered to be within the present scope. It should be noted that the particular dopant used may be doped according to the different materials, and the intended use of the final material.

The dopant may be a charge-transferring or receiving dopant species. More specifically, electron-transporting or hole-transporting species can cause regions to become more or less active in polarity than semiconductor layers. In one aspect, for example, the doped region can be p-doped. In another aspect, the doped region may be n-doped. A highly doped region may also be formed on or near the doped region to create a fixed diode. In one non-limiting example, the semiconductor layer may be passive in polarity, and the doped and highly doped regions may be doped p + and n, respectively. In some aspects, n (-), n (+), p (-), or p (+ +) type doping of various regions may be used. In one aspect, non-limiting examples of doping materials can include S, F, B, P, N, As, Se, Te, Ge, Ar, Ga, In, Sb, and combinations thereof.

Claims

1. An optoelectronic device with enhanced absorption of electromagnetic radiation, comprising:

a semiconductor layer coupled to a support substrate;

a first adhesive layer coupled between the semiconductor layer and the support substrate;

a set of shallow trench isolation surface features located between the semiconductor layer and the support substrate, the surface features positioned to interact with electromagnetic radiation passing through the semiconductor layer.

2. The optoelectronic device of claim 1, wherein the semiconductor layer is monocrystalline silicon.

3. The optoelectronic device of claim 1, wherein the first adhesive layer is coupled between the support substrate and the surface feature.

4. The optoelectronic device of claim 1, wherein the surface features are formed in the support substrate.

5. The optoelectronic device of claim 1, wherein the surface features are formed in the semiconductor layer.

6. The optoelectronic device of claim 1, wherein the surface features have at least substantially uniform height.

7. The optoelectronic device of claim 1, wherein the surface features are non-uniform in height.

8. The optoelectronic device of claim 1, further comprising:

a device layer coupled to the semiconductor layer opposite the surface feature.

9. An optoelectronic device according to claim 1, wherein the device is structurally configured as a front-lit optoelectronic device.

10. An optoelectronic device according to claim 1, wherein the device is structurally configured as a back-illuminated optoelectronic device.

11. The optoelectronic device of claim 1, further comprising a second adhesive layer between the first adhesive layer and the support substrate.

12. The optoelectronic device of claim 11, further comprising a reflector layer disposed between the first and second adhesive layers.

13. The optoelectronic device of claim 1, wherein the surface features are arranged according to a preset pattern.

14. The optoelectronic device of claim 13, wherein the predetermined pattern is an at least substantially uniform grid.

15. The optoelectronic device of claim 9, wherein the predetermined pattern is a non-uniform arrangement.

16. A method of making an optoelectronic device comprising the steps of:

using shallow trench isolation etching to generate a set of surface features in the semiconductor layer; and is

The set of surface features is bonded between the support substrate and the semiconductor layer.

17. The method of claim 16, wherein the step of generating a set of surface features further comprises:

a set of surface features is generated on at least a portion of a surface of a semiconductor layer.

18. The method of claim 16, wherein the step of generating the set of surface features further comprises:

generating the set of surface features on at least a portion of the support substrate surface.

19. The method of claim 16, further comprising the steps of:

thinning the semiconductor layer opposite the support substrate to a thickness of about 2 microns to about 10 microns to create an original thin surface; and

a device layer is formed on the thin surface.

20. The method of claim 16, wherein bonding the set of surface features between the support substrate and the semiconductor layer further comprises:

depositing a first bonding layer on the semiconductor layer; and

bonding the first bonding layer to a second bonding layer deposited on the support substrate.

21. The method of claim 20, further comprising the steps of:

depositing a reflector layer on at least one of the first or second adhesive layers prior to bonding the semiconductor layer to the support substrate.

22. A method of making an optoelectronic device comprising the steps of:

generating a set of surface features on at least a portion of a surface of a support substrate using a shallow trench isolation etch; and is

Bonding the set of surface features between the support substrate and the semiconductor layer.

23. The method of claim 22, wherein bonding the set of surface features between the support substrate and the semiconductor layer further comprises:

depositing a first bonding layer on the semiconductor layer; and

24. An optoelectronic device with enhanced absorption of electromagnetic radiation, comprising:

a semiconductor layer having a light incident surface and an opposite surface, the semiconductor layer having a plurality of doped regions forming at least one junction;

a textured region comprising a plurality of shallow trench isolation surface features located at a light entrance face of the semiconductor layer and configured to interact with incident electromagnetic radiation;

a support substrate coupled to the semiconductor layer; and

a first adhesive layer disposed between the semiconductor layer and the support substrate,

wherein the optoelectronic device is an imager capable of detecting visible and infrared electromagnetic radiation.

25. The optoelectronic device of claim 24, wherein the semiconductor layer is monocrystalline silicon.

26. The optoelectronic device of claim 24, wherein the shallow trench isolation surface features are formed in the semiconductor layer.

27. The optoelectronic device of claim 24, wherein the shallow trench isolation surface features have a substantially uniform height.

28. The optoelectronic device of claim 24, wherein the shallow trench isolation surface features are non-uniform in height.

29. An optoelectronic device according to claim 24, further comprising a device layer coupled to the semiconductor layer opposite the light entrance facet.

30. The optoelectronic device of claim 24, wherein the first adhesion layer comprises any one of silicon oxide, silicon nitride, and amorphous silicon.

31. The optoelectronic device of claim 24, wherein the semiconductor layer has a thickness of about 1 micron to about 10 microns.

32. The optoelectronic device of claim 24, wherein the bonding layer has a thickness of about 30 nanometers to about 3 micrometers.

33. The optoelectronic device of claim 1, wherein the bonding layer has a thickness of about 40 nanometers to about 2 micrometers.

34. The optoelectronic device of claim 24, wherein the plurality of shallow trench isolation surface features have a height of about 50 nanometers to about 20 micrometers.

35. The optoelectronic device of claim 24, wherein the shallow trench isolation surface features comprise pyramids.

36. An optoelectronic device according to claim 24, wherein the plurality of shallow trench isolation surface features are formed by pattern masking and photolithography followed by etching.

37. The optoelectronic device of claim 24, wherein the plurality of shallow trench isolation surface features comprises a plurality of etch levels.

38. The optoelectronic device of claim 24, wherein the textured region enhances absorption of electromagnetic radiation within the semiconductor layer.

39. The optoelectronic device of claim 24, wherein the textured region increases light absorption within the semiconductor layer in an electromagnetic spectrum range of at least about 700 nanometers to about 1100 nanometers.

40. An optoelectronic device according to claim 24, wherein the textured region increases the effective optical path length of light as it passes through the semiconductor layer.

41. The optoelectronic device of claim 24, wherein the textured region allows the semiconductor layer to pass through multiple passes of light.

42. The optoelectronic device of claim 24, further comprising a second adhesive layer between the first adhesive layer and the support substrate.

43. The optoelectronic device of claim 42, further comprising a reflector layer disposed between the first and second adhesive layers.

44. The optoelectronic device of claim 24, wherein the shallow trench isolation surface features are configured according to a pattern.

45. An optoelectronic device according to claim 44, wherein the pattern is an at least substantially uniform grid.

46. The optoelectronic device of claim 44, wherein the pattern is a non-uniform arrangement.

47. A method of making an optoelectronic device comprising the steps of:

bonding a semiconductor layer to a support substrate, wherein bonding the semiconductor layer to the support substrate comprises:

depositing a first bonding layer on the semiconductor layer; and

bonding the first bonding layer to a second bonding layer deposited on the support substrate; and

a plurality of shallow trench isolation surface features are formed on a light incident surface of the semiconductor layer.

48. The method of claim 47 wherein forming the plurality of shallow trench isolation surface features comprises creating a set of surface features using a shallow trench isolation etch.

49. The method of claim 47, further comprising deep trench isolation for isolating the device.

50. The method of claim 49, wherein the deep trench isolation provides a light harvesting function.

51. An optoelectronic device with enhanced absorption of electromagnetic radiation, comprising:

a support substrate coupled to the semiconductor layer; and

a first adhesive layer disposed between the semiconductor layer and the support substrate;

a second adhesive layer between the first adhesive layer and the support substrate; and

a reflector layer disposed between the first and second adhesive layers.

52. The optoelectronic device of claim 51, wherein the shallow trench isolation surface features comprise pyramids.

53. An optoelectronic device according to claim 51, wherein the plurality of shallow trench isolation surface features are formed by pattern masking and photolithography followed by etching.

54. The optoelectronic device of claim 51, wherein the semiconductor layer has a thickness from about 1 micron to about 10 microns.

55. The optoelectronic device of claim 51, wherein the shallow trench isolation surface features have a substantially uniform height.

56. The optoelectronic device of claim 51, wherein the shallow trench isolation surface features are non-uniform in height.

57. The optoelectronic device of claim 51, wherein the plurality of shallow trench isolation surface features have a height of about 50 nanometers to about 20 micrometers.

58. An optoelectronic device according to claim 51, wherein the optoelectronic device is an imager capable of detecting visible and infrared electromagnetic radiation.

59. The optoelectronic device of claim 51, wherein the textured region enhances absorption of electromagnetic radiation within the semiconductor layer.

60. The optoelectronic device of claim 51, wherein the textured region increases light absorption within the semiconductor layer in an electromagnetic spectrum range of at least about 700 nanometers to about 1100 nanometers.

61. An optoelectronic device according to claim 51, wherein the textured region increases the effective optical path length of light as it passes through the semiconductor layer.

62. The optoelectronic device of claim 51, wherein the textured region allows the semiconductor layer to experience multiple passes of light.

63. The optoelectronic device of claim 51, further comprising deep trench isolation for isolating the device.

64. The optoelectronic device of claim 63, wherein the deep trench isolation provides a light harvesting function.

65. The optoelectronic device of claim 51, wherein the shallow trench isolation surface features are configured according to a pattern.

66. An optoelectronic device according to claim 51, wherein the pattern is an at least substantially uniform grid.

67. The optoelectronic device of claim 51, wherein the pattern is a non-uniform arrangement.

68. An imager capable of detecting visible and infrared electromagnetic radiation, comprising:

a textured region comprising a plurality of surface features configured to interact with incident electromagnetic radiation, thereby increasing quantum efficiency of the device,

a support substrate coupled to the semiconductor layer; and

a first adhesive layer disposed between the semiconductor layer and the support substrate.

69. The imager of claim 68, wherein textured region is on the light entrance face of the semiconductor layer.

70. The imager of claim 69, further comprising a device layer coupled to the semiconductor layer opposite the light entrance facet.

71. The imager of claim 69, wherein the textured region is formed by etching.

72. The imager according to claim 71, wherein said surface features comprise pyramids.

73. The imager according to claim 69, further comprising a reflector layer disposed between the textured layer and the support substrate.

74. The imager according to claim 68, further comprising deep trench isolation for isolating said device.

75. The imager according to claim 74, wherein said deep trench isolation provides a light capturing function.

76. The imager of claim 68, wherein said semiconductor layer is single crystal silicon.

77. The imager according to claim 68, wherein said semiconductor layer comprises silicon and germanium.

78. The imager according to claim 68, wherein said surface features are formed in said semiconductor layer.

79. The imager of claim 68, wherein the surface features have a substantially uniform height.

80. The imager of claim 68, wherein the surface features are non-uniform in height.

81. The imager according to claim 68, wherein said first adhesion layer comprises any one of silicon oxide, silicon nitride, and amorphous silicon.

82. The imager according to claim 68, wherein said semiconductor layer has a thickness of about 1 micron to about 10 microns.

83. An imager in accordance with claim 82, wherein the device exhibits a quantum efficiency of at least about 35% for electromagnetic radiation having a wavelength of about 940 nanometers.

84. The imager according to claim 68, wherein said bonding layer has a thickness from about 30 nanometers to about 3 micrometers.

85. The imager of claim 68, wherein the plurality of surface features have a height of about 50 nanometers to about 20 micrometers.

86. The imager according to claim 68, wherein the plurality of surface features have a height from about 0.35 microns to about 0.7 microns.

87. The imager according to claim 68, wherein said plurality of surface features are formed by pattern masking and photolithography followed by etching.

88. The imager of claim 68, wherein the plurality of surface features comprises a plurality of etch levels.

89. The imager of claim 68, wherein the textured region increases light absorption within the semiconductor layer in an electromagnetic spectrum range of at least about 700 nanometers to about 1100 nanometers.

90. The imager according to claim 68, further comprising a second adhesive layer between said first adhesive layer and said support substrate.

91. The imager of claim 68, wherein the surface features are configured according to a pattern.

92. The imager according to claim 91, wherein said pattern is an at least substantially uniform grid.

93. The imager of claim 91, wherein the pattern is a non-uniform arrangement.

94. A method of making an imager, comprising the steps of:

providing a semiconductor layer with a light incident surface and an opposite surface, wherein the semiconductor layer is provided with a plurality of doped regions forming at least one junction surface;

providing a support substrate;

forming a plurality of surface features on one of the semiconductor layer and the support substrate; and

bonding the semiconductor layer to the support substrate.

95. The method of claim 94, wherein bonding the semiconductor layer to the support substrate comprises:

depositing a first bonding layer on the semiconductor layer; and

96. The method of claim 94, wherein the plurality of surface features are formed on a light entrance facet of the semiconductor layer.

97. The method of claim 94, wherein the surface features are formed by etching.

98. The method of claim 97, further comprising depositing an oxide material within at least a portion of the semiconductor layer or the support substrate removed by etching.

99. The method of claim 98 wherein the depositing an oxide material comprises at least partially filling one of a trench, a hole, a pit, and a taper formed in the semiconductor layer when etched.

100. The method of claim 98, further comprising performing a CMP process on a region of the semiconductor layer or the support substrate including the surface feature after depositing the oxide material.

101. The method of claim 94, wherein the surface features are formed by shallow trench isolation etching.

102. The method of claim 94, wherein the surface features are formed in the semiconductor layer.