CN110911394B - Packaging structure of terahertz focal plane detector and manufacturing method thereof - Google Patents
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Abstract
The invention discloses a packaging structure of a terahertz focal plane detector and a manufacturing method thereof. Packaging structure includes terahertz focal plane detection chip, CMOS amplifier circuit chip and sets up the insulating substrate between terahertz focal plane detection chip and the CMOS amplifier circuit chip, a plurality of electrically conductive channels of having distributed in the insulating substrate, electrically conductive channel runs through insulating substrate along the thickness direction, and will terahertz focal plane detection chip is connected with CMOS amplifier circuit chip electricity. In the packaging structure of the terahertz focal plane detector provided by the embodiment of the invention, the TCV chip increases the distance between the focal plane chip and the CMOS amplifying circuit chip, so that the sensitivity of the terahertz focal plane detector is improved; and the TCV chip in the embodiment of the invention is respectively connected with the focal plane chip and the CMOS amplifying circuit chip in an inverted manner to realize 3D packaging, thereby being beneficial to realizing the miniaturization of the focal plane detector and improving the stability of the focal plane detector.
Description
Technical Field
The invention particularly relates to a packaging structure of a terahertz focal plane detector and a manufacturing method thereof, and belongs to the technical field of micro-nano manufacturing.
Background
Terahertz waves (Terahertz waves) are a section of electromagnetic spectrum resources which are not applied to human beings on a large scale, have the wavelength of 30 mu m-3 mm and the frequency range of 0.1-10 THz, and are also called submillimeter waves and far-infrared waves.
The terahertz wave has high transmission, low energy, fingerprint characteristic, high bandwidth, transient property, coherence and high resolution. The method can be used in the fields of human body security inspection, medical imaging, nondestructive testing and the like.
For the application requirements of high speed, high sensitivity and portable terahertz imaging, research and development personnel provide a terahertz focal plane imaging sensor of a high electron mobility transistor self-mixing detection mechanism, wherein the focal plane imaging sensor is realized by a detector array chip and a CMOS (complementary metal oxide semiconductor) readout circuit through flip interconnection; however, the distance between the CMOS amplifier chip and the focal plane chip is very small, and the metal on the CMOS amplifier chip shields the incident terahertz waves, which results in that the sensitivity of the focal plane detector chip is reduced to several tens of times of the original sensitivity.
Disclosure of Invention
The invention mainly aims to provide a packaging structure of a terahertz focal plane detector and a manufacturing method thereof, and further overcomes the defects in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
the packaging structure of the terahertz focal plane imaging sensor comprises a terahertz focal plane detection chip and a CMOS amplification circuit chip; and the packaging structure further comprises an insulating substrate arranged between the terahertz focal plane detection chip and the CMOS amplifying circuit chip, wherein a plurality of conductive channels are distributed in the insulating substrate, penetrate through the insulating substrate along the thickness direction and are electrically connected with the terahertz focal plane detection chip and the CMOS amplifying circuit chip.
Furthermore, a first under-bump metal layer and a second under-bump metal layer are further arranged at two ends of the conductive channel, the first under-bump metal layer and the second under-bump metal layer are respectively distributed on the first surface and the second surface of the insulating substrate, the first surface and the second surface are oppositely arranged, the first under-bump metal layer is electrically connected with the terahertz focal plane detection chip through first welding metal, and the second under-bump metal layer is electrically connected with the CMOS amplification circuit chip through second welding metal.
Preferably, the thickness of the first under bump metal layer and the second under bump metal layer is 350-500 nm.
Furthermore, a plurality of through holes are formed in the insulating base material, the through holes penetrate through the insulating base material along the thickness direction, and the through holes are filled with conductive materials to form the conductive channels.
Preferably, the diameter of the through hole is 70 to 100 μm.
Preferably, the conductive material includes a conductive metal material such as metallic copper.
Furthermore, the insulating substrate is a ceramic plate or a ceramic sheet, and the material of the ceramic plate or the ceramic sheet comprises aluminum nitride or aluminum oxide.
Preferably, the thermal expansion coefficient of the insulating base material is between that of the terahertz focal plane detection chip and that of the CMOS amplification circuit chip.
Preferably, the insulating substrate has a coefficient of thermal expansion of 4.3x10-6The thermal expansion coefficient of the focal plane chip is 5.8x10-6The thermal expansion coefficient of the CMOS amplifying circuit chip is 2.5x10-6/℃。
Preferably, the terahertz focal plane detection chip is arranged in a flip-chip manner.
Furthermore, the first surface and the second surface of the insulating substrate are both provided with insulating layers, windows are arranged on the insulating layers, and the first under bump metal layer and the second under bump metal layer are exposed out of the windows.
Preferably, the material of the insulating layer includes SiOx or Si3N4。
Preferably, the thickness of the insulating layer is 200-300 nm.
In some specific embodiments, the insulating layer on the first surface and the insulating layer on the second surface of the insulating substrate are further provided with a metal grid layer, the metal grid layer includes a plurality of grid structures, and the first under bump metal layer and the second under bump metal layer are exposed from the non-metal region of the grid structures.
Preferably, the metal region of the grid structure is arranged around the non-metal region, the side length of the metal region of the grid structure is 8-12 μm, and the side length of the non-metal region is 4-12 μm.
Preferably, the material of the metal grid layer includes metal such as nickel and gold.
Preferably, the thickness of the metal grid layer is 100-200 nm.
In some more specific embodiments, the first bonding metal comprises a solder ball formed by high temperature reflow of indium on the first surface of the insulating substrate.
In some more specific embodiments, the second bonding metal comprises a bonding pad formed by indium or gold vapor deposition on the second surface of the insulating substrate.
Furthermore, underfill adhesive is filled between the insulating base material and the focal plane chip and between the insulating base material and the CMOS amplifying circuit chip, and the underfill adhesive comprises epoxy resin and the like.
The embodiment of the invention also provides a manufacturing method of the terahertz focal plane detector packaging structure, which comprises the following steps:
manufacturing a plurality of through holes penetrating through the insulating substrate along the thickness direction on the insulating substrate, filling a conductive material in the through holes to form conductive channels, and enabling two ends of each conductive channel to be flush with a first surface and a second surface of the insulating substrate respectively, wherein the first surface and the second surface are arranged oppositely;
respectively manufacturing a first salient point lower metal layer and a second salient point lower metal layer which are matched with the two ends of the conductive channel on the first surface and the second surface of the insulating base material;
respectively arranging insulating layers on the first surface and the second surface of the insulating base material, and processing windows on the insulating layers so as to expose the first salient point lower metal layer and the second salient point lower metal layer;
respectively arranging metal grid layers on the insulating layers on the first surface and the second surface of the insulating base material, wherein the metal grid layers comprise a plurality of grid structures, and the first under bump metal layer and the second under bump metal layer are exposed out of the non-metal areas of the grid structures;
arranging a first welding metal and a second welding metal which are respectively matched with the first salient point lower metal layer and the second salient point lower metal layer on the first surface and the second surface of the insulating base material;
and the insulating base material is welded and combined with the terahertz focal plane detection chip and the CMOS amplifying circuit chip through a first welding metal and a second welding metal respectively.
In some more specific embodiments, the manufacturing method comprises:
filling a conductive material in the through hole formed in the insulating base material at least in an electroplating mode so as to form the conductive channel;
and polishing the first surface and the second surface of the insulating base material so as to remove redundant conductive materials distributed on the first surface and the second surface of the insulating base material and enable two ends of the conductive channel to be flush with the first surface and the second surface of the insulating base material respectively.
In some more specific embodiments, the manufacturing method further comprises: welding and combining the insulating base material with the terahertz focal plane detection chip and the CMOS amplifying circuit chip in a flip-chip welding mode; and
and injecting underfill between the TCV chip and the focal plane chip and between the TCV chip and the CMOS amplifying circuit chip.
Compared with the prior art, in the packaging structure of the terahertz focal plane detector provided by the embodiment of the invention, the TCV chip increases the distance between the focal plane chip and the CMOS amplifying circuit chip, and the metal grid structure is manufactured on the TCV chip, so that the reflection of terahertz waves is reduced, the interference is eliminated, and the sensitivity of the terahertz focal plane detector is further improved; the TCV chip in the embodiment of the invention is respectively connected with the focal plane chip and the CMOS amplifying circuit chip in an inverted manner to realize 3D packaging, so that the miniaturization of the focal plane detector is realized, and the stability of the focal plane detector is improved; and the number of the first and second groups,
according to the packaging structure of the terahertz focal plane detector provided by the embodiment of the invention, the TCV chip is manufactured by adopting the aluminum nitride ceramic or the aluminum oxide ceramic as the substrate material, and the aluminum nitride ceramic has well-matched thermal expansion coefficient and high resistance and is low in terahertz wave loss.
Drawings
FIG. 1 is a schematic diagram of an insulating substrate after formation of a via in accordance with an exemplary embodiment of the present invention;
FIG. 2 is a schematic structural diagram of an insulating substrate after filling a via with copper metal in accordance with an exemplary embodiment of the present invention;
FIG. 3 is a schematic diagram of the structure of the insulating substrate after removing the excess copper metal on the front and back sides of the insulating substrate according to an exemplary embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a structure after forming a UBM layer according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a structure after forming an insulating layer according to an exemplary embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a structure after forming a metal grid layer according to an exemplary embodiment of the present invention;
FIG. 7 is a schematic illustration of a structure after formation of a weld metal in accordance with an exemplary embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a package structure of a terahertz focal plane detector in an exemplary embodiment of the present invention;
fig. 9 is a graph of detector photocurrent versus silicon wafer and detector spacing L.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.
Referring to fig. 7, a package structure of a terahertz focal plane detector includes a focal plane chip, a CMOS amplifier circuit chip, and a TCV chip disposed between the focal plane chip and the CMOS amplifier circuit chip, where a first surface and a second surface of the TCV chip are electrically connected to the focal plane chip and the CMOS amplifier circuit chip, respectively, to form a 3D package structure.
Wherein, the TCV chip comprises an insulating substrate, a plurality of through holes penetrating through the insulating substrate along the thickness direction are distributed in the insulating substrate, the diameter of the through holes is 70-100 μm, the through holes are filled with conductive materials such as copper and the like to form a conductive channel, two ends of the conductive channel are respectively and electrically connected with a first UBM layer (namely the first under bump metal layer and the lower same layer) and a second UBM layer (namely the second under bump metal layer and the lower same layer) distributed on the first surface and the second surface of the insulating substrate, the thickness of the first UBM layer and the second UBM layer is 350-500nm, the first UBM layer is electrically connected with a focal plane chip through first welding metal, the first UBM layer is electrically connected with a CMOS amplifying circuit chip through second welding metal, and the first surface and the second surface of the insulating substrate are both provided with a plurality of through holes penetrating through the insulating substrate along the thickness direction, the diameter of the through holes is 70-100 μm, the through the conductive materials are filled in the through holes, the conductive materials are electrically connected with the first UBM layer through the second UBM layer through the focal plane chip, and the second UBM layer through the first surface of the insulating substrate, and the second surface are respectively, and the insulating substrate are provided with a plurality of the first UBM through the second UBM layer, and the second through the second UBM through the first surface are provided with a plurality of the insulating substrate, and the insulating substrate are provided with a plurality of the insulating substrate, and the insulating substrate are provided with a plurality of the insulating substrate, and the insulating substrate are provided with the insulating substrate, andSiOx or Si3N4An insulating layer of SiOx or Si3N4A window is arranged on the insulating layer; in SiOx or Si3N4The insulating layer is also provided with a metal grid layer, the metal grid layer comprises a plurality of grid structures, each grid structure is provided with a metal area and a non-metal area (or an opening, the non-metal area corresponds to a window area on the insulating layer), the first UBM layer and the second UBM layer are made of SiOx or Si3N4Exposing the windows of the insulating layer and the non-metallic regions of the metal grid layer, SiOx or Si3N4The thickness of the insulating layer is 200-300nm, and the thickness of the metal grid layer is 100-200nm, wherein the first surface and the second surface are oppositely arranged.
Specifically, the substrate of the focal plane chip is sapphire, and the thermal expansion coefficient of the focal plane chip is 5.8x10-6The thermal expansion coefficient of the CMOS amplifying circuit chip is 2.5x10 at/DEG C-6The TCV chip comprises an insulating substrate, wherein the insulating substrate is a ceramic plate or a ceramic plate, and the thermal expansion coefficient of the ceramic plate or the ceramic plate is 4.3x10-6And the aluminum nitride ceramic has high insulativity and low loss to terahertz waves.
Specifically, taking an aluminum nitride ceramic plate as an example of an insulating substrate, a method for manufacturing a terahertz focal plane detector may include the following steps:
1) as shown in fig. 1, providing an aluminum nitride ceramic plate (i.e. the aforementioned insulating substrate, the same applies below) with a certain thickness, and forming a plurality of through holes in the aluminum nitride ceramic plate by laser drilling, wherein the through holes penetrate through the aluminum nitride ceramic plate along the thickness direction, and the diameter of the through holes is 70-100 μm;
2) as shown in fig. 2, the through holes are filled with copper by electroplating;
3) as shown in fig. 3, the copper on the front and back surfaces (the front surface may be the first surface and the back surface may be the second surface) of the aluminum nitride ceramic plate is removed by chemical mechanical polishing, and the copper in the through holes is retained to form copper pillars (i.e., the conductive channels), so that the two ends of the copper pillars are flush with the front and back surfaces of the aluminum nitride ceramic plate, respectively, thereby making the surface of the aluminum nitride ceramic plate smooth and flat;
4) as shown in fig. 4, respectively evaporating UBM (Ni/Au/Pt/Au) metal layers on the front and back of the aluminum nitride ceramic plate, and connecting the UBM with the copper pillar, wherein the thickness of the UBM metal layer is 350-500nm, preferably 450nm, and the UBM metal layer is a Ni layer, an Au layer, a Pt layer, and an Au layer sequentially stacked;
5) as shown in FIG. 5, 200-300nm SiOx or Si is grown on the front and back surfaces of the aluminum nitride ceramic plate by PECVD3N4Etching the area corresponding to the UBM metal layer by adopting an RIE (reactive ion etching) mode to form a window exposing the UBM metal layer;
6) as shown in FIG. 6, SiOx or Si is formed on the front and back surfaces of the aluminum nitride ceramic plate3N4A mask is disposed in the window region of the insulating layer, and SiOx or Si is disposed3N4Evaporating 100-200nm nickel or gold and other metals in the area of the insulating layer which is not covered by the mask to form a metal grid layer, and then removing the mask to form openings or windows which are not covered by the metals, wherein each opening or window and the metals distributed around the opening or window form a grid structure, the side length of the metal area of the grid structure is 8-12 mu m, the side length of the non-metal area (namely the opening or window) is 4-12 mu m, and the first UBM layer and the second UBM layer are exposed from the non-metal area;
7) as shown in fig. 7, indium metal (i.e., the first solder metal) is vapor-deposited on the non-metal area of the front surface of the aluminum nitride ceramic plate and reflowed at a high temperature into a spherical shape; evaporating gold or indium plate (without reflowing into balls, i.e. the second soldering metal) in the non-metal area of the back surface of the aluminum nitride ceramic plate, wherein the indium balls and the gold or indium plate are manufactured by the method disclosed in CN 104979224A;
8) as shown in fig. 8, a flip chip bonding method is adopted to connect the metal indium balls on the front side of the TCV chip to the focal plane chip, connect the gold or indium pad on the back side to the CMOS amplifier circuit chip, and inject filling glue such as epoxy resin between the focal plane chip and the TCV chip, and between the CMOS amplifier circuit chip and the TCV chip.
As shown in fig. 9, the TCV chip and the CMOS chip form a resonant cavity, and incident terahertz waves are reflected multiple times in the cavity to generate interference, so that the responsivity of the detector is low at a quarter wavelength, i.e., a pitch of 0-300 μm, and is improved when the distance is greater than the quarter wavelength.
In the packaging structure of the terahertz focal plane detector provided by the embodiment of the invention, the TCV chip increases the distance between the focal plane chip and the CMOS amplifying circuit chip, and the metal grid structure is manufactured on the TCV chip, so that the reflection of terahertz waves is reduced, the interference is eliminated, and the responsivity of the terahertz focal plane detector is further improved; and the TCV chip in the embodiment of the invention is respectively connected with the focal plane chip and the CMOS amplifying circuit chip in an inverted manner to realize 3D packaging, so that the matching of the thermal expansion coefficients of the focal plane chip and the CMOS amplifying circuit chip can be enhanced, the miniaturization of the focal plane detector is facilitated, and the stability of the focal plane detector is improved.
According to the packaging structure of the terahertz focal plane detector provided by the embodiment of the invention, the TCV chip is manufactured by adopting the aluminum nitride ceramic or the aluminum oxide ceramic as the substrate material, and the aluminum nitride ceramic has well-matched thermal expansion coefficient and high resistance and is low in terahertz wave loss.
It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (18)
1. A packaging structure of a terahertz focal plane detector comprises a terahertz focal plane detection chip and a CMOS amplification circuit chip; the terahertz focal plane detection device is characterized by further comprising an insulating base material arranged between the terahertz focal plane detection chip and the CMOS amplification circuit chip, wherein a plurality of conductive channels are distributed in the insulating base material, penetrate through the insulating base material along the thickness direction and electrically connect the terahertz focal plane detection chip with the CMOS amplification circuit chip;
a first under bump metal layer and a second under bump metal layer are further arranged at two ends of the conductive channel, the first under bump metal layer and the second under bump metal layer are respectively distributed on the first surface and the second surface of the insulating substrate, the first surface and the second surface are arranged oppositely, the first under bump metal layer is electrically connected with the terahertz focal plane detection chip through first welding metal, and the second under bump metal layer is electrically connected with the CMOS amplification circuit chip through second welding metal;
the first surface and the second surface of the insulating base material are both provided with insulating layers, windows are arranged on the insulating layers, metal grid layers are further arranged on the insulating layers on the first surface and the second surface of the insulating base material, each metal grid layer comprises a plurality of grid structures, and the first salient point lower metal layer and the second salient point lower metal layer are exposed from the windows on the insulating layers and the nonmetal areas of the grid structures.
2. The package structure of the terahertz focal plane detector as claimed in claim 1, wherein: the thicknesses of the first under bump metal layer and the second under bump metal layer are 350-500 nm.
3. The package structure of the terahertz focal plane detector as claimed in claim 1, wherein: the insulating substrate is internally provided with a plurality of through holes, the through holes penetrate through the insulating substrate along the thickness direction, and the through holes are internally filled with conductive materials to form the conductive channels.
4. The packaging structure of the terahertz focal plane detector as claimed in claim 3, wherein: the diameter of the through hole is 70-100 μm.
5. The packaging structure of the terahertz focal plane detector as claimed in claim 3, wherein: the conductive material comprises metallic copper.
6. The package structure of the terahertz focal plane detector as claimed in claim 1, wherein: the insulating substrate is a ceramic plate or a ceramic wafer, and the ceramic plate or the ceramic wafer is made of aluminum nitride or aluminum oxide.
7. The package structure of the terahertz focal plane detector as claimed in claim 6, wherein: the thermal expansion coefficient of the insulating base material is between that of the terahertz focal plane detection chip and that of the CMOS amplification circuit chip.
8. The package structure of the terahertz focal plane detector as claimed in claim 1, wherein: the terahertz focal plane detection chip is arranged in an inverted mode.
9. The package structure of the terahertz focal plane detector as claimed in claim 1, wherein: the material of the insulating layer comprises SiOx or Si3N4。
10. The package structure of the terahertz focal plane detector as claimed in claim 1, wherein: the thickness of the insulating layer is 200-300 nm.
11. The package structure of the terahertz focal plane detector as claimed in claim 1, wherein: the thickness of the metal grid layer is 100-200 nm.
12. The package structure of the terahertz focal plane detector as claimed in claim 1, wherein: the metal region of the grid structure is disposed around the non-metal region.
13. The package structure of the terahertz focal plane detector as claimed in claim 1, wherein: the first welding metal comprises a welding ball formed by indium in a high-temperature reflow mode on the first surface of the insulating base material.
14. The package structure of the terahertz focal plane detector as claimed in claim 1, wherein: the second welding metal comprises a bonding pad formed by indium or gold on the second surface of the insulating base material through evaporation.
15. The package structure of the terahertz focal plane detector as claimed in claim 1, wherein: and underfill is filled among the insulating base material, the terahertz focal plane detection chip and the CMOS amplifying circuit chip.
16. The manufacturing method of the terahertz focal plane detector packaging structure as claimed in any one of claims 1 to 15, comprising:
manufacturing a plurality of through holes penetrating through the insulating substrate along the thickness direction on the insulating substrate, filling a conductive material in the through holes to form conductive channels, and enabling two ends of each conductive channel to be flush with a first surface and a second surface of the insulating substrate respectively, wherein the first surface and the second surface are arranged oppositely;
respectively manufacturing a first salient point lower metal layer and a second salient point lower metal layer which are matched with the two ends of the conductive channel on the first surface and the second surface of the insulating base material;
respectively arranging insulating layers on the first surface and the second surface of the insulating base material, and processing windows on the insulating layers so as to expose the first salient point lower metal layer and the second salient point lower metal layer;
respectively arranging metal grid layers on the insulating layers on the first surface and the second surface of the insulating base material, wherein the metal grid layers comprise a plurality of grid structures, and the first salient point lower metal layer and the second salient point lower metal layer are exposed from the non-metal areas of the grid structures;
arranging a first welding metal and a second welding metal which are respectively matched with the first salient point lower metal layer and the second salient point lower metal layer on the first surface and the second surface of the insulating base material;
and the insulating base material is welded and combined with the terahertz focal plane detection chip and the CMOS amplifying circuit chip through a first welding metal and a second welding metal respectively.
17. The method of manufacturing of claim 16, wherein:
filling a conductive material in the through hole formed in the insulating base material at least in an electroplating mode so as to form the conductive channel;
and polishing the first surface and the second surface of the insulating base material so as to remove redundant conductive materials distributed on the first surface and the second surface of the insulating base material and enable two ends of the conductive channel to be flush with the first surface and the second surface of the insulating base material respectively.
18. The method of manufacturing according to claim 16, further comprising: welding and combining the insulating base material with the terahertz focal plane detection chip and the CMOS amplifying circuit chip in a flip-chip welding mode; and
and injecting underfill between the insulating base material and the terahertz focal plane detection chip and between the insulating base material and the CMOS amplifying circuit chip.
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| JP6235154B2 (en) * | 2013-09-18 | 2017-11-22 | 中国科学院蘇州納米技術与納米▲ファン▼生研究所 | Terahertz light source chip |
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