CN110895597B

CN110895597B - Transcoding logical function calculation method and device, storage medium and electronic equipment

Info

Publication number: CN110895597B
Application number: CN201811063771.XA
Authority: CN
Inventors: 林家圣
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-09-12
Filing date: 2018-09-12
Publication date: 2022-04-19
Anticipated expiration: 2038-09-12
Also published as: CN110895597A

Abstract

The present disclosure relates to a transcoding logical function calculation method, a transcoding logical function calculation apparatus, a computer-readable storage medium, and an electronic device. The transcoding logic function calculation method provided by the embodiment of the disclosure comprises the following steps: acquiring a plurality of logic character strings with the same length, and determining the corresponding number of input variables according to the length of the logic character strings; classifying the logic character strings through a clustering algorithm to obtain a plurality of clusters; calculating to obtain a transcoding logic subfunction corresponding to each cluster according to the value of the output variable and the value of the input variable in each cluster; and carrying out OR operation on each transcoding logic subfunction to obtain the transcoding logic function. The transcoding logic function calculation method provided by the embodiment of the disclosure can realize rapid and efficient address transcoding or data transcoding.

Description

Transcoding logical function calculation method and device, storage medium and electronic equipment

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a transcoding logic function calculation method, a transcoding logic function calculation apparatus, a computer-readable storage medium, and an electronic device.

Background

For physical memory, each memory location within the memory corresponds to an actual physical address. To facilitate program execution in test engineering or product engineering, a programmer may transcode logical addresses of memory to obtain corresponding physical addresses, thereby facilitating program traversal of desired physical addresses.

The transcoding relationship from the logical address to the physical address can be completed through the address corresponding table, but the address corresponding table often has the problem of poor general applicability. Particularly, for a logic address with a large number of bits, for example, a logic address represented by a 32-bit character is reflected on the address mapping table and has 2^32 mapping relationships, and the way of searching through cycles will occupy more running time and running memory, which is not favorable for the use of programs or instruments.

Therefore, how to improve the transcoding efficiency of addresses or data is a problem to be solved urgently at present.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to a transcoding logic function calculating method, a transcoding logic function calculating device, a computer-readable storage medium, and an electronic device, so as to overcome at least some technical problems of long transcoding time consumption and low transcoding efficiency due to limitations of related technologies.

According to one aspect of the present disclosure, a method for calculating a transcoding logic function is provided, the transcoding logic function is used for transcoding a plurality of input variables to obtain an output variable, and is characterized in that the method comprises:

acquiring a plurality of logic character strings with the same length, and determining the corresponding number of input variables according to the length of the logic character strings;

classifying the logic character strings through a clustering algorithm to obtain a plurality of clusters;

calculating to obtain a transcoding logic subfunction corresponding to each cluster according to the value of the output variable and the value of the input variable in each cluster;

and carrying out OR operation on each transcoding logic subfunction to obtain the transcoding logic function.

In an exemplary embodiment of the present disclosure, the clustering algorithm is a hamming distance-based clustering algorithm.

In an exemplary embodiment of the present disclosure, the calculating to obtain the transcoding logic subfunction corresponding to each cluster includes:

and respectively calculating to obtain transcoding logic subfunctions corresponding to the clusters by utilizing distributed calculation.

In an exemplary embodiment of the present disclosure, before or-ing each of the transcoding logical subfunctions to obtain the transcoding logical function, the method further includes:

performing non-operation on the output variable to obtain an inverted output variable;

respectively calculating to obtain reverse transcoding logic subfunctions corresponding to the clusters according to the values of the reverse output variables and the values of the input variables in the clusters;

carrying out non-operation on the reverse transcoding logic subfunction to obtain a normal phase transcoding logic subfunction;

acquiring the length of a transcoding logic subfunction corresponding to the same cluster and the length of a normal-phase transcoding logic subfunction;

and if the length of the normal-phase transcoding logic subfunction is judged to be smaller than that of the transcoding logic subfunction, taking the normal-phase transcoding logic subfunction as the transcoding logic subfunction of the cluster.

and respectively calculating to obtain transcoding logic subfunctions corresponding to the clusters by using a carnot diagram method.

and respectively calculating to obtain transcoding logic subfunctions corresponding to the clusters by utilizing a heuristic logic simplification algorithm.

In an exemplary embodiment of the present disclosure, the heuristic logic reduction algorithm is an esponso algorithm, a K-SPP algorithm, or a DRedSPP algorithm.

In an exemplary embodiment of the present disclosure, the logical string is a logical address of a memory, and the output variable is one bit in a physical address of the memory.

In an exemplary embodiment of the present disclosure, the transcoding logic function includes and operation, or operation, xor operation, and not operation for the input variable.

According to an aspect of the present disclosure, there is provided a transcoding logic function computing apparatus, the transcoding logic function being configured to transcode a plurality of input variables to obtain an output variable, the apparatus comprising:

the acquisition module is configured to acquire a plurality of logic character strings with the same length and determine the corresponding number of input variables according to the length of the logic character strings;

the clustering module is configured to classify the logic character strings through a clustering algorithm to obtain a plurality of clusters;

the cluster calculation module is configured to calculate and obtain a transcoding logic subfunction corresponding to each cluster according to the value of an output variable and the value of an input variable in each cluster;

a function operation module configured to perform an or operation on each of the transcoding logic subfunctions to obtain the transcoding logic function.

According to an aspect of the present disclosure, there is provided a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements any of the transcoding logic function computing methods described above.

According to one aspect of the present disclosure, there is provided an electronic device characterized by comprising a processor and a memory; wherein the memory is used for storing executable instructions of the processor, and the processor is configured to execute any one of the transcoding logic function calculation methods described above by executing the executable instructions.

The transcoding logic function calculation method provided by the embodiment of the disclosure classifies the logic character strings through clustering, so that the calculation dimension for searching the transcoding logic function can be effectively reduced, the calculation efficiency is improved, the calculation cost is saved, and further, the rapid and efficient address transcoding or data transcoding can be realized.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 schematically illustrates a flowchart of steps of a transcoding logic function computing method in an exemplary embodiment of the present disclosure.

Fig. 2 schematically illustrates a flowchart of a part of steps of a transcoding logic function calculating method in another exemplary embodiment of the present disclosure.

Fig. 3 schematically illustrates a partial step flow diagram of a transcoding logic function computing method in an application scenario in an exemplary embodiment of the present disclosure.

Fig. 4 schematically illustrates a partial step flow diagram of a transcoding logic function calculating method in another application scenario in an exemplary embodiment of the present disclosure.

Fig. 5 schematically illustrates a block diagram of a transcoding logic function computing apparatus according to an exemplary embodiment of the present disclosure.

Fig. 6 schematically illustrates a schematic diagram of a program product in an exemplary embodiment of the present disclosure.

Fig. 7 schematically illustrates a module diagram of an electronic device in an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

In an exemplary embodiment of the present disclosure, a method for calculating a transcoding logic function is first provided, where the transcoding logic function is used to transcode a plurality of input variables to obtain an output variable. The transcoding logical function can be applied to address transcoding or data transcoding in the fields of test engineering, product engineering analysis and the like. For example, in the aspect of Test engineering, both a wafer Test (Chip bonding, abbreviated as CP Test) before Chip packaging and a Final Test (Final Test, abbreviated as FT Test) after Chip packaging may perform address transcoding or data transcoding so as to execute a program. For example, in the aspect of product engineering, Electrical Failure Analysis (EFA) may present an Electrical Failure address (Electrical Failure address) in the form of a Physical Failure address (Physical Failure address) by address transcoding.

Referring to fig. 1, the transcoding logic function calculating method provided in this exemplary embodiment may mainly include the following steps:

and S110, acquiring a plurality of logic character strings with the same length, and determining corresponding number of input variables according to the length of the logic character strings.

In the step, a plurality of logical character strings to be transcoded are obtained, the length of each character string is the same, and the corresponding number of input variables can be determined according to the length of the logical character strings. For example, if the obtained logical strings are

strings

0000, 0100, 0011, 0111 and 1111 … … with a length of 4 bits, this step may determine 4 input variables A, B, C, D, where each input variable represents a bit in the logical string. For another example, if the acquired logical string is a 32-bit logical address, then the present step can correspondingly determine 32 input variables corresponding to the respective address bits.

And S120, classifying the logic character strings through a clustering algorithm to obtain a plurality of clusters.

For the logical character strings obtained in step S110, this step classifies them by a clustering algorithm to obtain a plurality of clusters. This step may use a clustering algorithm based on unsupervised machine learning, for example, a K-MEANS algorithm, a K-MEDOIDS algorithm, a Clara algorithm, a Clarans algorithm, etc. may be used. In addition, the clustering algorithm used in this step may be a clustering algorithm based on Hamming Distance (Hamming Distance) as Distance calculation, where the Hamming Distance represents the number of different characters at corresponding positions of two character strings with equal length, for example, the Hamming Distance between logical character string 0000 and logical character string 0100 is 1, the Hamming Distance between

logical character strings

0000 and 0011 is 2, and the Hamming Distance between

logical character strings

0000 and 0111 is 3. The clustering algorithm based on the Hamming distance is favorable for dividing the logic character strings with approximate binary dimensionality (namely, the Hamming distance is smaller) into the same cluster, and when each logic character string in the same cluster has the same value on at least one position, the purpose of reducing the dimensionality can be achieved, and the calculated amount in the subsequent function calculation is reduced. For example, 64 clusters are obtained after clustering processing is performed on logical character strings with the length of 32 bits, wherein each logical character string in each cluster has the same value at 6bit positions, so that the computational dimension of each cluster can be reduced from 32 bits to 26 bits, and the computational cost is greatly reduced. In the step, when the logic character strings are clustered, the clustering number can be determined by the used clustering algorithm, and the automatic clustering mode is favorable for finding the clustering number and the clustering result which are close to the optimal dimensionality reduction effect. In addition, in this step, a cluster number may also be preset according to the attribute and the value-taking characteristic of the logical character string, and then the clustering is performed by the clustering algorithm according to the preset cluster number, which is not particularly limited in this exemplary embodiment.

And S130, calculating to obtain transcoding logic subfunctions corresponding to the clusters according to the values of the output variables and the values of the input variables in the clusters.

After the clustering process of the logical character strings is completed in step S120, the calculation is performed according to the values of the output variables and the values of the input variables in each cluster, so as to obtain transcoding logical subfunctions corresponding to each cluster one to one. For example, after the clustering processing is performed in step S120, 64 clusters are obtained, and then 64 transcoding logic subfunctions are obtained through corresponding calculation in this step. The transcoding logic subfunction corresponding to a cluster is used for expressing the mapping relation between the input variable and the output variable in the cluster, namely, the transcoding logic subfunction can be used for transcoding the value of the input variable in the cluster to obtain the value of the corresponding output variable.

And S140, performing OR operation on each transcoding logic subfunction to obtain a transcoding logic function.

In this step, the transcoding logic functions obtained in step S130 may be subjected to OR Operation (OR) to obtain a complete transcoding logic function, where X denotes an input variable, Y denotes an output variable, AND f may be a combination of multiple logic operations such as AND operation (AND), OR Operation (OR), exclusive OR operation (XOR), AND NOT Operation (NOT). The transcoding logic function obtained in this step can reflect the mapping relation between all input variables and output variables.

The process of finding the logistic functional relationship between a large number of input variables and output variables belongs to the NP-hard problem. In which NP (Non-deterministic Polynomial) refers to a Non-deterministic problem of Polynomial complexity, it is currently widely accepted in the field of computer science that no effective algorithm exists for NP-hard problem, and large instances of such problem cannot be solved with an accurate algorithm, but an effective approximation algorithm for such problem must be sought. As the number of input variables increases, the amount of computation to find the logistic function will also increase exponentially. The transcoding logic function calculation method provided by the exemplary embodiment classifies the logic character strings through clustering, so that the calculation dimension for searching the transcoding logic function can be effectively reduced, the calculation efficiency is improved, the calculation cost is saved, and further, the rapid and efficient address transcoding or data transcoding can be realized.

On the basis of the above exemplary embodiment, the calculating in step S130 to obtain the transcoding logic subfunction corresponding to each of the clusters may include: and respectively calculating to obtain transcoding logic subfunctions corresponding to the clusters by utilizing distributed calculation. For example, the clusters may be computed in parallel using a Hadoop distributed computing server, where each computing node on the Hadoop distributed computing server corresponds to a cluster. The more the computing nodes are, the more the number of clusters which can be computed simultaneously is, so that the computing efficiency can be greatly improved.

Taking a logic character string with the length of 32 bits as an example, the value combination form of the input variables can reach 2^32 maximum. By using the transcoding logic function calculation method provided by the exemplary embodiment, assuming that 4 clusters are obtained after clustering the obtained logic character strings, and the dimensionality of the input variables in each cluster is reduced to 8 bits, the value combination form of the input variables in each cluster is reduced to 2^ 8. By utilizing the dimensionality reduction effect of clustering processing, the overall calculation amount is greatly reduced, and the time cost for calculating the transcoding logic function can be greatly reduced by combining the parallel processing of distributed calculation. In addition, through clustering processing, the storage types required to be configured during operation are reduced from original 2^32 types to 4 multiplied by 2^8 ^ 2^10 types, so that the space cost for calculating the transcoding logic function can be greatly reduced.

Referring to fig. 2, in another exemplary embodiment of the present disclosure, before performing an or operation on each transcoding logic sub-function to obtain a transcoding logic function at step s140, the transcoding logic function calculating method may further include the following steps:

and S210, carrying out non-operation on the output variable to obtain an inverted output variable.

In the step, firstly, a non-operation (NOT) is carried out on the output variable to obtain an inverse output variable with a value opposite to that of the original output variable. For example, if the original output variable takes a value of 0, then the corresponding inverse output variable 1 will be obtained in this step.

And S220, respectively calculating to obtain reverse transcoding logic subfunctions corresponding to the clusters according to the values of the reverse output variables and the values of the input variables in the clusters.

Based on the result of clustering the logical character strings in step S120, this step calculates according to the values of the inverted output variables and the values of the input variables in each cluster, so as to obtain inverted transcoding logical subfunctions corresponding to each cluster one to one. For example, after the clustering processing is performed in step S120, 64 clusters are obtained, and then 64 inverse transcoding logic subfunctions are obtained through corresponding calculation in this step. The reverse transcoding logic subfunction corresponding to a cluster is used for expressing the mapping relation between the input variable and the reverse output variable in the cluster, namely the reverse transcoding logic subfunction can be used for transcoding the value of the input variable in the cluster to obtain the value of the corresponding reverse output variable. In this step, the same method as that used for calculating the transcoding logic subfunction in step S130 may be used for calculating the inverse transcoding logic subfunction, and a different calculation method from that used in step S130 may also be used, which is not particularly limited in this exemplary embodiment.

And step S230, carrying out non-operation on the reverse-phase transcoding logic subfunction to obtain a normal-phase transcoding logic subfunction.

After the inverse transcoding logical subfunction is obtained in step S220, the function is subjected to non-operation in this step to obtain a normal-phase transcoding logical subfunction. The normal phase transcoding logic subfunction obtained in this step may be used to express a mapping relationship between an input variable and an output variable in the current cluster, that is, may be used to transcode a value of an input variable in the current cluster to obtain a value of a corresponding output variable. The normal phase transcoding logic subfunction in this step may obtain the same transcoding effect as the transcoding logic subfunction obtained in step S130, but because of the difference in the calculation process and the calculation method, the two are necessarily different in the logic expression.

And S240, acquiring the length of the transcoding logic subfunction corresponding to the same cluster and the length of the normal-phase transcoding logic subfunction.

For the same cluster, two function expression modes are obtained in step S130 and step S230, namely the transcoding logic subfunction obtained in step S130 and the inverse transcoding logic subfunction obtained in step S230. The step can obtain the length of the transcoding logic subfunction and the length of the normal-phase transcoding logic subfunction corresponding to the same cluster. In the present exemplary embodiment, the length of the function may be measured by the number of logical operations on the input variable, and the length may reflect the degree of simplicity of the function, and thus may also indirectly reflect the amount of computation for the same logical string.

And S250, if the length of the normal-phase transcoding logic subfunction is judged to be smaller than that of the transcoding logic subfunction, taking the normal-phase transcoding logic subfunction as the clustered transcoding logic subfunction.

According to the function length obtained in step S240, this step compares the length of the normal phase transcoding logic subfunction with that of the original transcoding logic subfunction, and if the length of the normal phase transcoding logic subfunction is determined to be smaller than that of the transcoding logic subfunction, the normal phase transcoding logic subfunction may be used as a new transcoding logic subfunction of the current cluster, that is, the normal phase transcoding logic subfunction with a shorter length is used to replace the transcoding logic subfunction. After the replacement is completed, the normal-phase transcoding logical subfunction can be used as the transcoding logical subfunction of the current cluster, and the normal-phase transcoding logical subfunction and the transcoding logical subfunctions of other clusters are subjected to or operation in step S140, so that a transcoding logical function with a more concise expression is obtained.

In the present exemplary embodiment, a more compact transcoding logic function can be obtained by performing the calculation process of both the forward-phase transcoding logic function and the reverse-phase transcoding logic function on the same cluster and comparing the calculation results. Although the exemplary embodiment adds a calculation process in function calculation, address transcoding or data transcoding is performed by using the transcoding logical function calculated by the exemplary embodiment, so that the calculation amount can be greatly reduced, and the calculation cost can be saved.

In the present exemplary embodiment, a calculation method of performing a non-operation on the output variable first is employed, and the non-operation may be performed before the clustering process performed in step S120 or after the clustering process. Since step S120 is to cluster the logical character strings corresponding to the input variables, performing a non-operation before or after clustering will produce the same clustering result. Similar to the present exemplary embodiment, in other embodiments, a non-operation calculation method for the input variable may also be adopted, if the non-operation is performed before the clustering, different clustering results will be generated, and different transcoding logic function calculation results will be brought by the different clustering results, so that the probability of finding a more concise transcoding logic function can be improved to a certain extent.

In another exemplary embodiment of the present disclosure, the calculating in step S130 to obtain the transcoding logic subfunction corresponding to each of the clusters may include: and respectively calculating to obtain transcoding logic subfunctions corresponding to the clusters by using a carnot diagram method.

Referring to FIG. 3, an example of the correspondence between a set of logical addresses X with a length of 4 bits and a set of physical addresses Y with the same length of 4 bits is shown. In the current cluster, each logical address X is a logical string, 4 input variables A, B, C, D are used to represent the 4bit positions of the logical string, and output variable E is used to represent one of the 4bit positions of the physical address Y. Drawing a corresponding carnot graph according to the values of the input variables A, B, C, D and the output variables E, and then obtaining the transcoding logic subfunction of the current cluster by using the carnot graph

And respectively obtaining transcoding logic subfunctions of the physical address Y on the output variables F, G, H at the other 3 bit positions in the same way as the output variable E, and combining the calculation results of other clusters to obtain the transcoding function relationship between the logical address X and the physical address Y.

The transcoding logic subfunction calculated by using the carnot method is not necessarily the simplest function expression, but only comprises two logic operations of AND operation and OR operation, and has the advantages of simple calculation mode and high calculation speed. Especially for the condition of less input variables, the transcoding logic function can be quickly calculated at lower calculation cost.

In another exemplary embodiment of the present disclosure, the calculating in step S130 to obtain the transcoding logic subfunction corresponding to each of the clusters may include: and respectively calculating to obtain transcoding logic subfunctions corresponding to the clusters by utilizing a heuristic logic simplification algorithm. The heuristic logic simplification algorithm can be an ESPRESSO algorithm, a K-SPP algorithm or a DRedSPP algorithm.

The transcoding logic subfunction obtained by the heuristic logic simplification algorithm can be generally combined with the logical operations such as the AND operation, the OR operation, the XOR operation and the NOT operation. The heuristic logic simplification algorithm is suitable for the transcoding logic function calculation process with large input variable quantity and complex corresponding relation, and the calculation cost can be effectively reduced through clustering processing. Generally speaking, as the number of clusters increases, the degree of reduction in the overall computation cost becomes more significant when the computation conditions permit. For example, a set of 32-bit logical strings with an output variable corresponding to 2³¹And (4) seed preparation. The corresponding transcoding logic function can be found by directly using the heuristic logic simplification algorithm in the exemplary embodiment without clustering (which is equivalent to 1 clustering), and if the clustering is performed on the logical character strings to obtain 64 clusters (assuming that the input variable dimension in each cluster is reduced to 26 bits), then using the heuristic logic simplification algorithm in the exemplary embodiment can also find the corresponding transcoding logic function, but the two methods are greatly different in terms of calculation cost. As shown in table 1, in terms of time complexity, regardless of which heuristic logic simplification algorithm is used, the calculation cost can be greatly reduced after the clustering process. In table 1, in the time complexity of DRedSPP algorithm, the parameter d is a constant less than 32.

TABLE 1 time complexity contrast table

Heuristic logic simplification algorithm	Time complexity (not clustered)	Time complexity (clustering)
			ESPRESSO algorithm	(2³¹)²*32＝2⁶⁷	(2³¹/64)²*26﹤2⁵⁵
K-SPP algorithm	2^((2³¹)²)＝2^(2⁶²)	2^(2³¹/64)﹤2^(2²⁵)
			DRedSPP algorithm	2^((2^31-d)²)＝2^(2^62-2d)	2^(2^31-d/64)﹤2^(2^25-d)

The transcoding logic function calculation method provided by the exemplary embodiment of the present disclosure is described below in conjunction with an application scenario. The application scenario is that a transcoding logic function is formed in a test project according to the corresponding relation between a logic address with the length of N bits and a physical address with the length of N bits.

Referring to fig. 4, first, an N-bit logical address is used as an input variable, and a 1-bit physical address is used as an output variable. Performing logic address of the memory by clusteringClassifying to obtain a first cluster, a second cluster, a third cluster and a fourth cluster, wherein the logic address in each cluster has the same value at some bit positions, so that the input variable dimension of each cluster can be respectively reduced from N bits to N bits₁bit、n₂bit、n₃bit and n₄And (6) bit. Then, four computing nodes provided by the Hadoop distributed computing server are utilized to perform parallel computing to obtain a transcoding logic subfunction f corresponding to each cluster₁F2, f3, and f 4. And finally, performing OR Operation (OR) on the four transcoding logic subfunctions to obtain a transcoding logic function f between the N-bit logic address and the currently selected 1-bit physical address. A new bit position is selected from the N-bit physical addresses, and the function calculation process is repeated, so that the function corresponding relation between all the N-bit logical addresses and the N-bit physical addresses can be obtained.

As shown in fig. 4, before the corresponding transcoding logic subfunction is obtained through distributed computation, a non-operation (NOT) may be performed on the output variable, and a non-operation may be performed again on the function obtained through distributed computation to obtain another transcoding logic subfunction. The specific calculation and comparison methods have been described in the foregoing exemplary embodiments, and thus are not described in detail herein.

It should be noted that although the above exemplary embodiments describe the various steps of the methods of the present disclosure in a particular order, this does not require or imply that these steps must be performed in that particular order, or that all of the steps must be performed, to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.

In an exemplary embodiment of the present disclosure, there is also provided a transcoding logic function calculating apparatus, as shown in fig. 5, the transcoding logic function calculating apparatus 500 may mainly include: an acquisition module 510, a clustering module 520, a cluster computation module 530, and a function computation module 540. The obtaining module 510 is configured to obtain a plurality of logical character strings with the same length, and determine a corresponding number of the input variables according to the lengths of the logical character strings; a clustering module 520 configured to classify the logical character strings by a clustering algorithm to obtain a plurality of clusters; a cluster calculating module 530 configured to calculate, according to the values of the output variables and the values of the input variables in each cluster, transcoding logic subfunctions corresponding to each cluster; a function operation module 540 configured to perform an or operation on each transcoding logic sub-function to obtain a transcoding logic function.

The specific details of the transcoding logic function calculating device are already described in detail in the corresponding transcoding logic function calculating method, and therefore, the details are not repeated herein.

It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

In an exemplary embodiment of the present disclosure, there is also provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, can implement the transcoding logic function calculating method of the present disclosure as described above. In some possible embodiments, various aspects of the disclosure may also be implemented in the form of a program product comprising program code; the program product may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, or a removable hard disk, etc.) or on a network; when the program product is run on a computing device (which may be a personal computer, a server, a terminal apparatus, or a network device, etc.), the program code is configured to cause the computing device to perform the method steps in the above exemplary embodiments of the disclosure.

Referring to fig. 6, a program product 60 for implementing the above method according to an embodiment of the present disclosure may employ a portable compact disc read only memory (CD-ROM) and include program code, and may run on a computing device (e.g., a personal computer, a server, a terminal device, or a network device, etc.). However, the program product of the present disclosure is not limited thereto. In the exemplary embodiment, the computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium.

The readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

A readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the C language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's computing device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device over any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), etc.; alternatively, the connection may be to an external computing device, such as through the Internet using an Internet service provider.

In an example embodiment of the present disclosure, there is also provided an electronic device comprising at least one processor and at least one memory for storing executable instructions of the processor; wherein the processor is configured to perform the method steps in the above-described exemplary embodiments of the disclosure via execution of the executable instructions.

The electronic device 700 in the present exemplary embodiment is described below with reference to fig. 7. The electronic device 700 is only one example and should not bring any limitations to the functionality or scope of use of the embodiments of the present disclosure.

Referring to FIG. 7, an electronic device 700 is shown in the form of a general purpose computing device. The components of the electronic device 700 may include, but are not limited to: at least one processing unit 710, at least one memory unit 720, a bus 730 that couples various system components including the processing unit 710 and the memory unit 720, and a display unit 740.

Wherein the memory unit 720 stores program code which can be executed by the processing unit 710 such that the processing unit 710 performs the method steps in the above exemplary embodiments of the present disclosure.

The storage unit 720 may include readable media in the form of volatile memory units, such as a random access memory unit 721(RAM) and/or a cache memory unit 722, and may further include a read-only memory unit 723 (ROM).

The storage unit 720 may also include a program/utility 724 having a set (at least one) of program modules 725, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.

Bus 730 may be any representation of one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 700 may also communicate with one or more external devices 800 (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that allow a user to interact with the electronic device 700, and/or with any devices (e.g., router, modem, etc.) that allow the electronic device 700 to communicate with one or more other computing devices. Such communication may occur via an input/output (I/O) interface 750. Also, the electronic device 700 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet) via the network adapter 760. As shown in fig. 7, the network adapter 760 may communicate with other modules of the electronic device 700 via the bus 730. It should be appreciated that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the electronic device 700, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.

As will be appreciated by one skilled in the art, aspects of the present disclosure may be embodied as a system, method or program product. Accordingly, various aspects of the present disclosure may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software may be referred to herein generally as a "circuit," module "or" system.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, and the features discussed in connection with the embodiments are interchangeable, if possible. In the above description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

Claims

1. A method for calculating a transcoding logic function, the transcoding logic function being used for transcoding a plurality of input variables to obtain an output variable, the output variable being a bit in a physical address of a memory, the method comprising:

acquiring a plurality of logic character strings with the same length, wherein the logic character strings are logic addresses of the memory, and determining the corresponding number of input variables according to the length of the logic character strings;

2. The transcoding logic function computing method of claim 1, wherein the clustering algorithm is a hamming distance based clustering algorithm.

3. The method of claim 1, wherein the computing a transcoding logic subfunction corresponding to each cluster comprises:

4. The method of claim 1, wherein prior to ORing each of the transcoding logical subfunctions to obtain the transcoding logical function, the method further comprises:

5. The method of claim 1, wherein the computing a transcoding logic subfunction corresponding to each cluster comprises:

6. The method of claim 1, wherein the computing a transcoding logic subfunction corresponding to each cluster comprises:

7. The transcoding logic function computing method of claim 6, wherein the heuristic logic reduction algorithm is an ESPRESSO algorithm, a K-SPP algorithm, or a DRedSPP algorithm.

8. The transcoding logic function calculating method according to any one of claims 1 to 7, wherein the transcoding logic function includes an AND operation, an OR operation, an XOR operation, and a NOT operation for an input variable.

9. A transcoding logic function computing apparatus, the transcoding logic function being configured to transcode a plurality of input variables to obtain an output variable, the output variable being a bit in a physical address of a memory, the apparatus comprising:

the acquisition module is configured to acquire a plurality of logic character strings with the same length, wherein the logic character strings are logic addresses of the memory, and the corresponding number of the input variables is determined according to the length of the logic character strings;

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the transcoding logical function computing method of any of claims 1 to 8.

11. An electronic device, comprising:

a processor;

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the transcoding logic function computation method of any of claims 1-8 via execution of the executable instructions.