CN110890369A - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN110890369A CN110890369A CN201811046271.5A CN201811046271A CN110890369A CN 110890369 A CN110890369 A CN 110890369A CN 201811046271 A CN201811046271 A CN 201811046271A CN 110890369 A CN110890369 A CN 110890369A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 238000000034 method Methods 0.000 title claims description 23
- 239000010410 layer Substances 0.000 claims abstract description 247
- 230000004888 barrier function Effects 0.000 claims abstract description 99
- 239000000463 material Substances 0.000 claims abstract description 49
- 239000011241 protective layer Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000009413 insulation Methods 0.000 claims abstract description 5
- 238000009792 diffusion process Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 abstract description 12
- 230000000903 blocking effect Effects 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 238000007599 discharging Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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Abstract
The embodiment of the invention discloses a preparation method of a semiconductor device and the semiconductor device. The preparation method comprises the following steps: providing a substrate with a plurality of active regions, wherein each active region comprises a source drain region and a bit line contact region, the active regions are provided with word line segments and word line insulation structures for burying the word line segments, and the bit line contact regions are relatively recessed in the source drain regions; forming a protective layer on the source drain region, wherein the protective layer covers the word line insulating structure and is provided with a contact channel formed on the bit line contact region, and the contact channel is communicated with the bit line contact region; forming a barrier layer on the bit line contact region, wherein the barrier layer covers the side wall and the bottom of the contact channel; forming a bit line material layer covering the barrier layer on the protective layer and in the contact channel; the bit line material layer is patterned to form a bit line layer above the protective layer over the contact via, the bit line layer further having a bit line contact integrally formed within the contact via, the barrier layer being between the bit line contact and the bit line contact. The semiconductor device prepared by the preparation method.
Description
Technical Field
The invention relates to the technical field of manufacturing of a Dynamic Random Access Memory (DRAM), in particular to a preparation method of a semiconductor device and the semiconductor device prepared by the preparation method.
Background
The dynamic random access memory comprises a plurality of memory cells, each memory cell comprises a MOS Transistor and a storage capacitor, and the MOS Transistor is a Metal-Oxide-semiconductor Field Effect Transistor (Metal-Oxide-semiconductor Field Effect Transistor) for short. The MOS transistor charges and discharges the storage capacitor by means of a bit line (BitLines) connected to the drain, so the magnitude of the resistance of the bit line affects the speed of charging and discharging the storage capacitor. The present bit line is formed of a polysilicon layer and a metal layer. The bit line comprising the polysilicon layer and the metal layer has a large resistance value, resulting in a small current flowing through the bit line, and further resulting in a slow charging and discharging speed of the storage capacitor.
Therefore, how to reduce the resistance of the bit line is a technical problem that needs to be solved urgently by those skilled in the art.
The above information disclosed in the background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is known to a person of ordinary skill in the art.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a method for manufacturing a semiconductor device and a semiconductor device manufactured by using the same, so as to solve at least the technical problems in the background art.
The technical solution of the embodiment of the present invention is achieved as follows, and according to the embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, including the steps of:
providing a substrate with a plurality of active regions, wherein each active region comprises a source drain region and a bit line contact region between the source drain regions, the active regions are provided with word line segments and word line insulation structures for burying the word line segments between the source drain regions and the bit line contact regions, and the bit line contact regions are relatively recessed in the source drain regions;
forming a protective layer on the source drain region, wherein the protective layer covers the word line insulating structure and is provided with a contact channel formed on the bit line contact region, and the contact channel is communicated with the bit line contact region;
forming a barrier layer on the bit line contact region, wherein the barrier layer at least covers the side wall and the bottom of the contact channel, and the width of the contact channel is defined by the barrier layer;
forming a bit line material layer on the protective layer and in the contact channel, wherein the bit line material layer also covers the barrier layer;
patterning the bit line material layer to form a bit line layer above the protective layer over the contact via, the bit line layer further having a bit line contact integrally formed within the contact via, the barrier layer being between the bit line contact and the bit line contact.
An embodiment of the present invention further provides a semiconductor device, including:
the active region comprises a source drain region and a bit line contact region between the source drain region, a word line segment and a word line insulating structure for burying the word line segment are arranged between the source drain region and the bit line contact region in the active region, and the bit line contact region is relatively recessed in the source drain region;
the protective layer is formed on the source drain region, covers the word line insulating structure and is provided with a contact channel formed on the bit line contact region, and the contact channel is communicated with the bit line contact region;
a barrier layer covering sidewalls and a bottom of the contact via;
a bit line layer formed over the contact via and above the protective layer, and covering the barrier layer, the bit line layer further having a bit line contact integrally formed within the contact via.
Due to the adoption of the technical scheme, the embodiment of the invention has the following advantages: compared with the traditional technology in the background technology, the bit line contact part of the polycrystalline silicon layer is omitted, the bit line contact part is formed in the manufacturing process of the bit line layer at the same time, the step of forming the bit line contact part independently is not needed, and meanwhile, the connection between the bit line layer and the bit line contact part is tighter, and the resistance value is smaller; the barrier layer separates the bit line contact part from the bit line contact region, and prevents the bit line contact part from diffusing to the bit line contact region due to direct contact between the bit line contact part and the bit line contact region.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a schematic view of the preparation method shown in FIG. 1 after step S100 is completed;
FIG. 3 is a schematic view of the preparation method shown in FIG. 1 after step S200 is completed;
FIG. 4 is a schematic view of the manufacturing method shown in FIG. 1 after step S300 is completed;
FIG. 5 is a schematic view of the manufacturing method shown in FIG. 1 after step S400 is completed;
fig. 6 is a schematic view of the manufacturing method shown in fig. 1 after step S500 is completed and a semiconductor device is manufactured;
FIG. 7 is a schematic view of the manufacturing method shown in FIG. 1 after step S600 is completed;
FIG. 8 is a schematic view of step S500 of the preparation method shown in FIG. 1;
FIG. 9 is a schematic view of the third embodiment of the present invention after completing step S100';
FIG. 10 is a schematic view of the third embodiment of the present invention after completing step S200';
FIG. 11 is a schematic view of a third embodiment of the present invention after completing step S300';
FIG. 12 is a schematic view of the third embodiment of the present invention after completing step S400';
FIG. 13 is a schematic view of the third embodiment of the present invention after completing step S510';
fig. 14 is a schematic view of the semiconductor device and the manufacturing method of the third embodiment of the invention after completing step S520';
FIG. 15 is a schematic view of the third embodiment of the present invention after completing step S600';
fig. 16 is a schematic view of step S510' in the preparation method of the third embodiment of the invention.
Description of reference numerals:
100 of a substrate,
110 of the bit line contact regions are formed,
a source region and a drain region of 120,
the segment of the word line 131 is,
132 a word line isolation structure is provided,
200 a protective layer is formed on the substrate,
210 are in contact with the channel(s),
311 a barrier layer for the barrier layer or layers,
400 a layer of a bit line material,
410 a bit line contact to the bit line,
a layer of 420 bit lines,
the number of the shades is 500,
600 spacer layer.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
Example one
An embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 1, the method may include the following steps:
as shown in fig. 2, step S100: providing a substrate 100 with a plurality of active regions, wherein the active regions comprise source and drain regions 120 and bit Line contact regions 110 between the source and drain regions, Word Line segments (Word lines) 131 and Word Line insulating structures 132 for burying the Word Line segments 131 are arranged between the source and drain regions and the bit Line contact regions, and the bit Line contact regions are relatively recessed in the source and drain regions; wherein the word line segment is a segment of the word line in the active region;
as shown in fig. 3, step S200: forming a protection layer 200 on the source and drain regions, wherein the protection layer 200 covers the word line insulation structure and is provided with a contact channel 210 formed on the bit line contact region, and the contact channel is communicated with the bit line contact region; the formed protective layer is arranged on the source drain region and covers the word line insulating structure, and a contact channel 210 formed on the bit line contact region is arranged and communicated with the bit line contact region;
as shown in fig. 4, step S300: forming a Barrier layer (Barrier layer)311 on the bit line contact region, the Barrier layer 311 covering only the sidewalls and bottom of the contact channel, the Barrier layer 311 defining the width of the contact channel 210;
as shown in fig. 5, step S400: forming a bit line material layer 400 on the protection layer 200 and in the contact channel, wherein the bit line material layer also covers the barrier layer 311;
as shown in fig. 6, step S500: patterning the bit line material layer to form a bit line layer 420 higher than the protection layer 200 above the contact via, the bit line layer 420 further having a bit line contact 410 integrally formed within the contact via, the barrier layer 311 being located between the bit line contact 410 and the bit line contact region.
The method for manufacturing the semiconductor Device of the embodiment of the invention can be used for manufacturing the semiconductor Device, in particular to a memory cell Device (Array Device) of DRAM and the like. Compared with the prior art in the background technology, the method for manufacturing the semiconductor device omits the bit line contact part of the polycrystalline silicon layer, simultaneously forms the bit line contact part in the manufacturing process of the bit line layer, does not need a step of independently forming the bit line contact part, and simultaneously has tighter connection between the bit line layer and the bit line contact part and smaller resistance; the barrier layer separates the bit line contact part from the bit line contact region, and prevents the bit line contact part from diffusing to the bit line contact region due to direct contact between the bit line contact part and the bit line contact region.
As an alternative, regarding the structure of the barrier layer, as shown in fig. 6, the barrier layer 311 is further extended and formed between the bit line contact 410 and the protection layer 200. Thus, the barrier layer is higher than the substrate, and can well separate the bit line contact from the substrate.
As an alternative, regarding the structure of the barrier layer, as shown in fig. 6, the upper end face of the barrier layer 311 on the active region is not lower than the upper surface of the substrate, i.e., the upper end face of the portion of the barrier layer covering the sidewall of the contact via is not lower than the upper surface of the substrate. In this way, the barrier layer can well separate the bit line contact from the substrate.
Since the material of the bit line layer may be metal, the material of the barrier layer is a material capable of conducting electricity and blocking metal diffusion, including but not limited to one or a combination of titanium nitride and tantalum nitride. Thus, the barrier layer can conduct the bit line contact region and the bit line contact portion and can prevent the bit line contact portion from diffusing to the bit line contact region.
The thickness range of the barrier layer on the bit line contact region can be 3-5 nanometers, and the barrier layer is used for preventing the bit line contact portion from diffusing to the bit line contact region due to the fact that the bit line contact portion is directly contacted with the bit line contact region. The barrier layer having this thickness range is superior in both the conductive property and the property of blocking the diffusion of the bit line contact portion to the bit line contact region.
As shown in fig. 6, the bit line layer 420 covers the upper end surface of the barrier layer on the active region, i.e., the bit line layer 420 covers the upper end surface of the portion of the barrier layer covering the sidewall of the contact via. The cross section area of the formed bit line layer is larger, and the probability of line breakage of the bit line layer is reduced.
The method for manufacturing a semiconductor device may further include the steps as shown in fig. 7:
step S600: a spacer layer 600 is formed, which covers the protection layer 200 and the bit line layer 420. The spacer layer 600 protects the bit line layer in preparation for subsequent fabrication steps of the semiconductor device.
As an alternative implementation, step S500 may include the following steps:
as shown in fig. 8, a mask 500 is used to cover the area of the bit line material layer covering the bit line contact region, and the area of the bit line material layer covering the protection layer 200 and connecting the bit lines between two adjacent contact channels;
referring to fig. 8, the "region covering the bit line material layer covering the protection layer 200 and connecting the bit line between two adjacent contact channels" is further described, where there are a plurality of contact channels arranged at intervals in the direction perpendicular to the cross section shown in fig. 8, and the part covered by the mask 500 is: the bit line material layer covers the protective layer 200 and connects the regions between two adjacent channels disposed in front and back with respect to the cross section shown in fig. 8 as bit lines;
etching down from the bit line material layer until the protection layer is exposed, as shown in fig. 6, further separating a filling portion of the bit line material layer within the contact channel to form a plurality of bit line contacts 410, and leaving a line portion of the bit line material layer on the protection layer and connected to at least two of the bit line contacts to form the bit line layer 420; wherein the contact vias and bit line layer 420 are staggered lines.
Referring to fig. 6, a further description is made on "the contact channel and the bit line layer are staggered lines", wherein a plurality of contact channels are spaced in a direction perpendicular to the cross section shown in fig. 6, and further a plurality of bit line contacts 410 are spaced in a direction perpendicular to the cross section shown in fig. 6, and the bit line layer 420 is continuously extended in a direction perpendicular to the cross section shown in fig. 6, so that a plurality of bit line contacts 410 are connected under the elongated bit line layer 420 in a direction perpendicular to the cross section shown in fig. 6, that is, the contact channels and the bit line layer are staggered lines.
In this way, the integrated bit line layer and bit line contact can be easily formed.
Example two
The second embodiment of the invention provides a preparation method of a semiconductor device, which comprises the following steps:
as shown in fig. 9, step S100': providing a substrate 100 with a plurality of active regions, wherein the active regions comprise source and drain regions 120 and bit Line contact regions 110 between the source and drain regions, Word Line segments (Word lines) 131 and Word Line insulating structures 132 for burying the Word Line segments 131 are arranged between the source and drain regions and the bit Line contact regions, and the bit Line contact regions are relatively recessed in the source and drain regions; wherein the word line segment is a segment of the word line in the active region;
as shown in fig. 10, step S200': forming a protection layer 200 on the source and drain regions, wherein the protection layer 200 covers the word line insulation structure and is provided with a contact channel 210 formed on the bit line contact region, and the contact channel is communicated with the bit line contact region; forming a protective layer, wherein the protective layer is formed on the source drain region and covers the word line insulating structure, and is provided with a contact channel 210 formed on the bit line contact region, and the contact channel is communicated with the bit line contact region;
as shown in fig. 11, step S300': forming a Barrier layer (Barrier layer)311 on the bit line contact region, the Barrier layer 311 covering the sidewalls and bottom of the contact channel and covering the protection layer, the Barrier layer 311 defining the width of the contact channel 210;
as shown in fig. 12, step S400': forming a bit line material layer 400 on the protection layer 200 and in the contact via 210, the bit line material layer further covering the barrier layer 311;
as shown in fig. 13, step S510': patterning the bit line material layer to form a bit line layer 420 higher than the protection layer 200 above the contact via, the bit line layer 420 further having a bit line contact 410 integrally formed within the contact via; as shown in fig. 14, step S520': the barrier layer is patterned and etched to remove the portion of the barrier layer 311 on the protection layer 200 and beyond the bit line layer 420, and the portion remaining on the sidewall and the bottom of the contact via, the pattern of the barrier layer 311 completely covers the bit line layer 420.
The method for manufacturing the semiconductor Device of the embodiment of the invention can be used for manufacturing the semiconductor Device, in particular to a memory cell Device (Array Device) of DRAM and the like. Compared with the prior art in the background technology, the method for manufacturing the semiconductor device omits the bit line contact part of the polycrystalline silicon layer, simultaneously forms the bit line contact part in the manufacturing process of the bit line layer, does not need a step of independently forming the bit line contact part, and simultaneously has tighter connection between the bit line layer and the bit line contact part and smaller resistance; the barrier layer separates the bit line contact part from the bit line contact region, and prevents the bit line contact part from diffusing to the bit line contact region due to direct contact between the bit line contact part and the bit line contact region.
As an alternative, regarding the structure of the barrier layer, as shown in fig. 6, the barrier layer 311 is further extended and formed between the bit line contact 410 and the protection layer 200. Thus, the barrier layer is higher than the substrate, and can well separate the bit line contact from the substrate.
As an alternative, regarding the structure of the barrier layer, as shown in fig. 14, an upper end surface of the barrier layer 311 on the active region is higher than an upper surface of the substrate and is also higher than an upper surface of the protection layer, that is, an upper end surface of a portion of the barrier layer covering the sidewall of the contact via is higher than the upper surface of the substrate and is also higher than the upper surface of the protection layer. In this way, the barrier layer can well separate the bit line contact from the substrate.
Since the material of the bit line layer may be metal. Therefore, the material of the barrier layer is a material capable of conducting electricity and blocking metal diffusion, including but not limited to one or a combination of titanium nitride and tantalum nitride. Thus, the barrier layer can conduct the bit line contact region and the bit line contact portion and can prevent the bit line contact portion from diffusing to the bit line contact region.
The thickness range of the barrier layer on the bit line contact region can be 3-5 nanometers, and the barrier layer is used for preventing the bit line contact portion from diffusing to the bit line contact region due to the fact that the bit line contact portion is directly contacted with the bit line contact region. The barrier layer having this thickness range is superior in both the conductive property and the property of blocking the diffusion of the bit line contact portion to the bit line contact region.
As shown in fig. 14, the bit line layer 420 covers the upper end surface of the barrier layer on the active region, i.e., the bit line layer 420 covers the upper end surface of the portion of the barrier layer covering the sidewall of the contact via. The cross section area of the formed bit line layer is larger, and the probability of line breakage of the bit line layer is reduced.
The method for manufacturing a semiconductor device may further include the steps as shown in fig. 15:
step S600': a spacer layer 600 is formed, which covers the protection layer 200 and the bit line layer 420. The spacer layer 600 protects the bit line layer in preparation for subsequent fabrication steps of the semiconductor device.
As an alternative embodiment, step S510' may include the following steps:
as shown in fig. 16, a mask 500 is used to cover the area of the bit line material layer covering the bit line contact region, and the area of the bit line material layer covering the protection layer 200 and connecting the bit lines between two adjacent contact channels;
referring to fig. 16, the "region covering the bit line material layer covering the protection layer 200 and connecting the bit line between two adjacent contact channels" is further described, where there are a plurality of contact channels arranged at intervals in a direction perpendicular to the cross section shown in fig. 16, and the portion covered by the mask 500 includes: the bit line material layer covers the passivation layer 200 and connects the regions between two adjacent channels disposed in front and back with respect to the cross section shown in fig. 16 as bit lines;
etching down from the bit line material layer until the protection layer is exposed, as shown in fig. 14, further separating a filling portion of the bit line material layer within the contact channel to form a plurality of bit line contacts 410, and leaving a line portion of the bit line material layer on the protection layer and connected to at least two of the bit line contacts to form the bit line layer 420; wherein the contact vias and bit line layer 420 are staggered lines.
Referring to fig. 14, a further description is made on "the contact channel and the bit line layer are staggered lines", wherein a plurality of contact channels are spaced in a direction perpendicular to the cross section shown in fig. 14, and further a plurality of bit line contacts 410 are spaced in a direction perpendicular to the cross section shown in fig. 14, and the bit line layer 420 is continuously extended in a direction perpendicular to the cross section shown in fig. 14, so that a plurality of bit line contacts 410 are connected under the elongated bit line layer 420 in a direction perpendicular to the cross section shown in fig. 14, that is, the contact channels and the bit line layer are staggered lines.
In this way, the integrated bit line layer and bit line contact can be easily formed.
EXAMPLE III
An embodiment of the present invention provides a semiconductor device manufactured by the manufacturing method of the semiconductor device of the first embodiment and the second embodiment, and as shown in fig. 2 and 6 and fig. 9 and 14, the manufacturing method may include:
a substrate 100 having a plurality of active regions, wherein the active regions include source and drain regions 120 and bit line contact regions 110 between the source and drain regions, word line segments 131 and word line insulating structures 132 burying the word line segments 131 are disposed between the source and drain regions and the bit line contact regions, and the bit line contact regions are recessed relative to the source and drain regions;
the protective layer 200 is formed on the source drain region, covers the word line insulating structure and is provided with a contact channel 210 formed on the bit line contact region, and the contact channel is communicated with the bit line contact region; namely, the protective layer covers the source-drain region and the word line insulating structure, and has a contact channel 210 formed on the bit line contact region, and the contact channel is communicated with the bit line contact region;
a barrier layer 311 covering the sidewalls and bottom of the contact via; and
a bit line layer 420 formed above the contact via and above the protection layer 200, and covering the barrier layer, the bit line layer 420 further having a bit line contact 410 integrally formed within the contact via.
According to the semiconductor device, the bit line layer and the bit line contact part are integrally formed, and the bit line layer and the bit line contact part are connected more tightly; the barrier layer separates the bit line contact from the bit line contact, preventing diffusion of the bit line contact 410 into the bit line contact due to direct contact between the bit line contact 410 and the bit line contact.
As an alternative, regarding the structure of the barrier layer, as shown in fig. 6 and 14, the barrier layer 311 is further extended and formed between the bit line contact 410 and the protection layer 200. Thus, the barrier layer is higher than the substrate, and can well separate the bit line contact from the substrate.
As an alternative, regarding the structure of the barrier layer, as shown in fig. 6 and fig. 14, the upper end surface of the barrier layer 311 is not lower than the upper surface of the substrate, that is, the upper end surface of the portion of the barrier layer covering the sidewall of the contact via is not lower than the upper surface of the substrate. In this way, the barrier layer can well separate the bit line contact from the substrate.
Since the material of the bit line layer may be metal. Therefore, the material of the barrier layer is a material capable of conducting electricity and blocking metal diffusion, including but not limited to one or a combination of titanium nitride and tantalum nitride. Thus, the barrier layer can conduct the bit line contact region and the bit line contact portion and can prevent the bit line contact portion from diffusing to the bit line contact region.
As shown in fig. 6 and 14, the thickness of the blocking layer on the bit line contact region 110 may be 3 to 5 nanometers, and the blocking layer is used to prevent the bit line contact portion from diffusing into the bit line contact region due to the direct contact between the bit line contact portion and the bit line contact region. The barrier layer having this thickness range is superior in both the conductive property and the property of blocking the diffusion of the bit line contact portion to the bit line contact region.
As shown in fig. 6 and 14, the bit line layer 420 covers the upper end surface of the barrier layer on the active region, that is, the bit line layer 420 covers the upper end surface of the barrier layer covering the sidewall of the contact via. The cross section area of the formed bit line layer is larger, and the probability of line breakage of the bit line layer is reduced.
The semiconductor device may further include:
as shown in fig. 7 and 15, a spacer layer 600, which covers the protective layer 200 and the bit line layer 420. Spacer layer 600 protects the bit line layer.
In the description of the present invention and its embodiments, it is to be understood that the terms "top," "bottom," "height," and the like are used in the positional or orientational relationships shown in the drawings for the purpose of convenience and simplicity of description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be construed as limiting the present invention.
In the present invention and its embodiments, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention and its embodiments, unless otherwise expressly specified or limited, the first feature "on" or "under" the second feature may comprise the first and second features being in direct contact, or may comprise the first and second features being in contact, not directly, but via another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The above disclosure provides many different embodiments, or examples, for implementing different features of the invention. The components and arrangements of the specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present invention, and these should be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (14)
1. A method for manufacturing a semiconductor device, comprising the steps of:
providing a substrate with a plurality of active regions, wherein each active region comprises a source drain region and a bit line contact region between the source drain regions, the active regions are provided with word line segments and word line insulation structures for burying the word line segments between the source drain regions and the bit line contact regions, and the bit line contact regions are relatively recessed in the source drain regions;
forming a protective layer on the source drain region, wherein the protective layer covers the word line insulating structure and is provided with a contact channel formed on the bit line contact region, and the contact channel is communicated with the bit line contact region;
forming a barrier layer on the bit line contact region, wherein the barrier layer at least covers the side wall and the bottom of the contact channel, and the width of the contact channel is defined by the barrier layer;
forming a bit line material layer on the protective layer and in the contact channel, wherein the bit line material layer also covers the barrier layer;
patterning the bit line material layer to form a bit line layer above the protective layer over the contact via, the bit line layer further having a bit line contact integrally formed within the contact via, the barrier layer being between the bit line contact and the bit line contact.
2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming a barrier layer on the bit line contact region, the barrier layer covers only sidewalls and a bottom of the contact via.
3. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the barrier layer on the bit line contact region, the barrier layer covers sidewalls and a bottom of the contact via and the protective layer;
in the step of patterning the bit line material layer, further comprising:
and patterning and etching the barrier layer to remove the part of the barrier layer on the protective layer and beyond the bit line layer and remain the part of the barrier layer on the side wall and the bottom of the contact channel, wherein the pattern of the barrier layer completely covers the bit line layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the barrier layer is further formed to extend between the bit line contact and the protective layer.
5. The method for manufacturing a semiconductor device according to claim 1, wherein an upper end face of a portion of the barrier layer covering the side wall of the contact via is not lower than an upper surface of the substrate.
6. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the barrier layer on the bit line contact region is in a range of 3 to 5 nm, and the barrier layer is used to prevent diffusion of the bit line contact portion to the bit line contact region due to direct contact between the bit line contact portion and the bit line contact region.
7. The method of claim 1, wherein the material of the barrier layer comprises one or a combination of titanium nitride and tantalum nitride.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the bit line layer covers an upper end face of a sidewall portion of the barrier layer covering the contact via.
9. The method of manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the step of patterning the bit line material layer to form a bit line layer higher than the protective layer over the contact via comprises:
covering the area of the bit line material layer covering the bit line contact area and covering the area of the bit line material layer covering the protective layer and connecting the bit line between two adjacent contact channels by using a shield;
and etching downwards from the bit line material layer until the protective layer is exposed, separating the filling part of the bit line material layer in the contact channel to form a plurality of bit line contacts, and keeping the line part of the bit line material layer on the protective layer and connected to at least two bit line contacts to form the bit line layer.
10. A semiconductor device, comprising:
the active region comprises a source drain region and a bit line contact region between the source drain region, a word line segment and a word line insulating structure for burying the word line segment are arranged between the source drain region and the bit line contact region in the active region, and the bit line contact region is relatively recessed in the source drain region;
the protective layer is formed on the source drain region, covers the word line insulating structure and is provided with a contact channel formed on the bit line contact region, and the contact channel is communicated with the bit line contact region;
a barrier layer covering sidewalls and a bottom of the contact via;
a bit line layer formed over the contact via and above the protective layer, and covering the barrier layer, the bit line layer further having a bit line contact integrally formed within the contact via.
11. The semiconductor device of claim 10, wherein an upper end surface of the portion of the barrier layer covering the contact via sidewall is not lower than an upper surface of the substrate.
12. The semiconductor device as claimed in claim 10, wherein the thickness of the barrier layer on the bit line contact region is in a range of 3 to 5 nm, and the barrier layer is used to prevent the bit line contact portion from diffusing into the bit line contact region due to direct contact between the bit line contact portion and the bit line contact region.
13. The semiconductor device of claim 10, wherein the material of the barrier layer comprises one or a combination of titanium nitride and tantalum nitride.
14. The semiconductor device according to any one of claims 10 to 13, wherein the bit line layer covers an upper end face of a sidewall portion of the barrier layer covering the contact via.
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