CN110889822B - Wafer design image analysis method, system and non-transitory computer readable medium - Google Patents

Abstract

A method, system and non-transitory computer readable medium for wafer design image analysis. The wafer design image analysis method comprises the following steps: obtaining a layout of circuit patterns implemented on a semiconductor wafer; identifying one or more polygons in the layout based on the length criteria; placing one or more measurement units on the identified polygon, thereby obtaining a plurality of measured polygons; obtaining a scanning electron microscope image of the circuit pattern; aligning the scanning electron microscope image with a layout comprising the measured polygons; measuring critical dimensions of one or more objects corresponding to the one or more polygons in the scanning electron microscope image; and determining whether the circuit pattern is acceptable based on the measured critical dimension.

Description

Wafer design image analysis method, system and non-transitory computer readable medium

Technical Field

Embodiments of the present disclosure relate to a wafer design image analysis system, and more particularly, to a method, system, and non-transitory computer readable medium for wafer design image analysis.

Background

Traditionally, using scanning electron microscopy (scanning electron microscope, SEM) to verify the quality of an acquired image of a circuit pattern formed on a wafer is labor intensive and time consuming. The engineer must manually create the measurement effort. After the image is acquired, the quality of the image is manually verified by analyzing the measurement results. Thus, there is a need for a more efficient and thorough image quality verification (image qualification) process.

Disclosure of Invention

An embodiment of the present disclosure provides a wafer design image analysis method, including: obtaining a layout of circuit patterns implemented on a semiconductor wafer; identifying one or more polygons in the layout based on the length criteria; placing one or more measurement units on the identified polygon, thereby obtaining a plurality of measurement target polygons; obtaining (scanning electron microscope, SEM) images of the circuit patterns; aligning the SEM image with a layout including a measurement target polygon; measuring critical dimensions of one or more objects in the SEM image corresponding to the measurement target polygon; and determining whether the circuit pattern is acceptable based on the measured critical dimension.

The embodiment of the disclosure further provides a wafer design image analysis system, which comprises: a memory for storing a plurality of instructions and at least one processor. The at least one processor is configured to execute instructions to: obtaining a layout of circuit patterns implemented on a semiconductor wafer; identifying a first polygon having a length greater than a first threshold size; identifying a plurality of segments of the first polygon, wherein each segment has a length equal to a second threshold size; placing one or more measurement units on the identified plurality of polygons, thereby obtaining measured polygons; aligning the SEM image of the circuit pattern with a layout comprising the measured polygons; measuring critical dimensions of one or more objects in the SEM image corresponding to one or more polygons in the layout; and determining whether the circuit pattern is acceptable based on the measured critical dimension.

Embodiments of the present disclosure further provide a non-transitory computer readable medium storing a plurality of instructions that when executed by a processor cause a computer to perform a method comprising: obtaining a layout of circuit patterns implemented on a semiconductor wafer; identifying a first polygon having a length greater than a first threshold size; identifying a plurality of segments of the first polygon, wherein each segment has a length equal to a second threshold size; placing one or more measurement units on the identified plurality of polygons, thereby obtaining measured polygons; obtaining an SEM image of the circuit pattern; aligning the SEM image with a layout comprising the measured polygon; measuring critical dimensions of one or more objects in the SEM image corresponding to one or more polygons in the layout; measuring the total critical dimension of the segments in the first polygon; generating a normal distribution of critical dimensions; calculating an average value of critical dimensions from the normal distribution; comparing the measured critical dimension of the one or more objects with the average value to obtain a comparison result; and determining whether the circuit pattern is acceptable based on the comparison result.

Drawings

The aspects of the embodiments of the present disclosure will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic diagram illustrating an SEM image quality verification process according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram illustrating a process flow performed by a wafer design image analysis module for image quality verification according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram illustrating the results of a polygon-based layout analysis and automatic measurement cell placement operation, according to some embodiments of the present disclosure;

FIG. 4 is a process flow illustrating operations for image-to-GDS alignment according to some embodiments of the present disclosure;

FIG. 5A is a diagram showing a CD-SEM image and a corresponding pre-processed image output from an operation of image pre-processing;

FIG. 5B illustrates an exemplary design layout and corresponding binary image obtained from a rasterization operation;

FIG. 6 is a diagram illustrating images taken at different processing steps performed during the operation of feature extraction according to some embodiments of the present disclosure;

FIG. 7 illustrates operations for fine searching, in which images from feature extraction operations are aligned with cropped GDS images, according to some embodiments of the present disclosure;

FIG. 8A illustrates a process flow performed during a measurement operation when an object is identified as a hole, according to some embodiments of the present disclosure;

FIG. 8B is a graph depicting the intersection points determined during the measurement operation of FIG. 8A;

FIG. 9A illustrates a process flow performed during a measurement operation when an object is identified as a line (or space) in accordance with some embodiments of the present disclosure;

FIG. 9B is a graph depicting the intersection points determined during the measurement operation of FIG. 9A;

FIG. 10 is a process flow diagram illustrating operations performed by layer/measurement cell related decisions according to some embodiments of the present disclosure;

FIG. 11 illustrates a system for performing image quality verification according to some embodiments of the present disclosure;

fig. 12 is a flowchart illustrating a method of image quality verification according to some embodiments of the present disclosure.

[ symbolic description ]

100: SEM image quality verification process

102: SEM apparatus of CD-SEM

104: designed layout

200. 800: process flow

201: CD-SEM image/wafer image

202: wafer design image analysis module

302: layout analysis based on polygons

304: automatic measurement cell placement

306: image preprocessing

308: image to GDS alignment

310: measurement of

312: layer/measurement cell related determination

401. 403, 405, 407, 409, 431: pattern and method for producing the same

411. 413, 415, 417, 419, 421, 423, 425, 427, 441, 451, 471: polygonal shape

444. 446, 448, 464, 466, 468: segment(s)

450. 460: one end is provided with

461: part of the pattern

481: measuring unit

501: binarized image

502: coarse search

503: gridding

504: feature extraction

505: preprocessing an image

506: fine search

511: processed image

513. 515, 517: image processing apparatus

521: cropped GDS image

523: finely matched images

531: feature points

802. 804, 806, 808, 810, 812, 814, 816, 818, 820, 822, 902, 904, 906, 908, 910, 912, 914, 916, 1002, 1004, 1006, 1008, 1010, 1012, 1014, 1016, S1202, S1204, S1206, S1208, S1210, S1212, S1214: operation of

831: critical Dimension (CD)

851: intersection point

1100: combination of two or more kinds of materials

1102: client host

1103: image quality verification tool

1112. 1136: processor and method for controlling the same

1114: input device

1116: output device

1118. 1138: communication module

1120: memory body

1122: application program

1130: memory device

1140: database for storing data

1150: network system

1152: layout module based on polygon

1154: automatic measuring unit placing module

1156: image preprocessing module

1158: image-to-GDS alignment module

1160: measuring module

1162: layer/measurement unit related judgment module

1200: method of

CD: critical Dimension (CD)

L, W: direction of

Detailed Description

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of embodiments of the disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. These are, of course, merely examples and are not intended to limit embodiments of the present disclosure. For example, the device dimensions are not limited to the disclosed ranges or values, but may be dependent on process conditions and/or desired properties of the device. Furthermore, in the description, a first feature is formed over or on a second feature, which may include embodiments in which the first feature is formed in direct contact with the second feature, as well as embodiments in which additional features may be formed interposed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. For simplicity and clarity of illustration, various features may be arbitrarily drawn at different scales.

Furthermore, spatially relative terms, such as "lower," "upper," and the like, may be used herein to facilitate a description of one element or feature relative to another element or feature as illustrated in the accompanying drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Further, the description of "made of" may be read as meaning "comprising" or "consisting of.

A critical dimension scanning electron microscope (critical dimension SEM, CD-SEM) is used as a measurement device to inspect various patterns of processes (workmanship) by measuring patterns formed on a semiconductor wafer. In SEM equipment such as CD-SEM, the critical point (dimensionally critical points) of dimensions on the semiconductor pattern is inspected and observed as an end measurement point by SEM, then various dimensional data of the pattern, such as pattern width, is measured from the acquired images during the observation process, and the dimensional data is monitored to detect changes in process conditions.

In SEM image quality verification (image qualification), SEM images are taken based on SEM images of a recipe (also referred to as a measurement job) created by the SEM operator. SEM images may be automatically acquired according to the recipe. The creation of a recipe depends on the operator's ability to interpret the layout and then uses the corresponding measurement settings to register (register) the location on the wafer under test in the recipe. The analysis of the measurement results varies depending on the application, the layer and the type of measurement unit (gauge-type). Thus, different formulations provide different analysis results, and image analysis depends on the quality of the SEM images obtained.

The disclosed embodiments relate to a polygon-based layout analysis method for extracting and classifying meaningful measurement locations on a wafer. The analysis method uses an automatic measurement unit placement (automated gauge placement) technique to place measurement units (gauges) on measurement locations with appropriate measurement parameters. The analysis method includes image-to-GDC (Graphic Database System) alignment, measurement core (measurement kernel), layer/measurement-dependent (layer/measurement-dependent) determination to obtain full-automatic wafer SEM image quality verification. The disclosed method advantageously provides full-automatic, full-field wafer SEM image quality verification. Meanwhile, the judging flow related to the customized layer/measuring unit can be customized according to different applications. There is a need for an image quality verification process that is independent of the SEM operator, as well as a more standardized image quality verification process. According to some embodiments of the present disclosure, measurement points in a circuit pattern formed on a substrate are automatically determined based on a pattern layout of the circuit pattern.

FIG. 1 is a schematic diagram illustrating an SEM image quality verification process 100 according to one embodiment of the disclosure. As shown in fig. 1, a semiconductor wafer having a desired circuit pattern implemented thereon is provided to SEM equipment at 102. In one embodiment, a critical dimension scanning electron microscope (critical dimension SEM, CD-SEM) is used to acquire images of patterns of circuit patterns implemented on a semiconductor wafer. The CD-SEM outputs an image 201 of the circuit pattern. In some embodiments, the image contains a pattern of the entire circuit, or, in other embodiments, the image contains an image of one or more areas (locations) of the circuit specified by the operator. In accordance with embodiments disclosed herein, a CD-SEM image 201 is provided to a wafer-to-design image analysis (WDIA) module 202. In one embodiment, the wafer design image analysis module 202 is implemented in software as computer executable program code executed by a processor. In other embodiments, the wafer design image analysis module 202 is implemented in hardware as a logic gate. In still other embodiments, the wafer design image analysis module 202 is implemented as a combination of hardware and software. In addition, the wafer design image analysis module 202 is also provided with a designed circuit layout 104 (e.g., graphic Database System (GDS) file) of circuits, wherein the CD-SEM image 201 is provided to the wafer design image analysis module 202. The wafer design image analysis module 202 performs quality verification on the CD-SEM image 201 based on the designed circuit layout 104. By analyzing the images, it can be determined whether the circuit pattern implemented on the semiconductor wafer is acceptable, e.g., within a desired range. A circuit pattern is considered acceptable if certain design parameters are met. For example, a circuit pattern implemented on a semiconductor wafer is considered acceptable if the distance between adjacent circuit lines is equal to or within a desired error range of the distance between adjacent circuit lines in the designed layout. In other embodiments, a circuit pattern is considered acceptable if the line width in the circuit pattern implemented on the semiconductor wafer is equal to or within some margin of error of the line width in the designed layout.

Fig. 2 is a schematic diagram illustrating a process flow 200 performed by a wafer design image analysis module 202 for image quality verification according to some embodiments of the present disclosure. As shown in FIG. 2, the wafer design image analysis module 202 includes operations for polygon-based layout analysis 302, automatic measurement cell placement 304, image pre-processing 306, image-to-GDS alignment 308, measurement 310, and layer/measurement cell related determination 312. Initially, operations of polygon-based layout analysis 302 and automatic measurement cell placement 304 are performed on the designed layout 104 of the circuit. In some embodiments, the designed layout 104 is considered to be implemented in a GDS file format (or GDSII file format). However, in other embodiments, the designed layout 104 is implemented as a OASIS (Open Artwork System Interchange Standard) file format.

The operation of the polygon based layout analysis 302 and the automatic measurement cell placement 304 is explained with reference to fig. 3. As shown in fig. 3, the layout 104 includes a plurality of patterns, each pattern including one or more polygons. Some of the patterns are labeled as patterns 401, 403, 405, 407, and 409 in fig. 3. For example, pattern 401 is comprised of a plurality of polygons 411, 413, 415, 417, 419, 421, 423, 425, and 427. The plurality of polygons 411, 413, 415, 417, 419, 421, 423, 425, and 427 are substantially rectangular or square in shape and are arranged in an end-to-end manner (end to end fashion) in the length (L) direction. In one embodiment, the patterns 401, 403, 405, 407, and 409 have the same length. However, in other embodiments, the patterns 401, 403, 405, 407, and 409 have different lengths. The patterns in layout 401 (e.g., patterns 401, 403, 405, 407, and 409) include polygons of different lengths (e.g., polygons 411, 413, 415, 417, 419, 421, 423, 425, and 427 in pattern 401). Alternatively, some or all of the polygons may have the same length. Furthermore, the pattern of polygons may include polygons having different widths. Alternatively, the pattern of polygons may include polygons having the same width (widths, W). In some embodiments, based on the orientation of fig. 3, the length (L) is a vertical dimension and the width (W) is a horizontal dimension.

During the polygon based layout analysis 302, the provided layout 104 is analyzed to identify portions of the layout 104 that meet a length criterion (length criterion) or an aspect ratio criterion (aspect criterion). The layout 104 then undergoes an operation of automatic measurement unit placement 304, where the operation of automatic measurement unit placement 304 inserts (or otherwise places) a plurality of measurement units (measurement gauges) on the polygon based on the measurement unit placement rules. The portion of the layout 104 that is processed using the polygon-based layout analysis 302 and the automatic measurement unit placement 304 is identified (or otherwise provided) by the user. As used herein, "measurement unit" refers to a region of interest (region-of-interest) on the layout 104 that has a measurement unit type (line/space/hole/island) and its corresponding measurement settings. In one embodiment, the measurement cell type is determined by a polygon-based layout analysis 302. If the aspect ratio of a polygon is less than or equal to a threshold (e.g., 2), such a polygon is identified as a hole object and is considered to represent a hole (or island) in the wafer image 201. Automatic measurement cell placement 304 places one measurement cell on each hole (or island), where a measurement cell consists of a measurement cell type, a region of interest and a corresponding measurement setup.

When a polygon is identified as a hole object, a hole-type measurement unit is placed on the polygon. After image-to-GDS alignment (operation 308 discussed below), the region of interest on the layout 104 is mapped to an aligned wafer image (e.g., image 523 in FIG. 7 discussed below), and then the measurement operation 310 (discussed below) uses the region of interest on the layout 104 to crop the sub-image (operation 802 in FIG. 8A discussed below).

When the aspect ratio of the polygon is greater than a threshold, the polygon is considered a line (or space) pattern. A line-type measurement unit (or a space-type measurement unit) is placed over each group polygon and isolated polygons (as discussed below) and has a corresponding region of interest. After image-to-GDS alignment 308, the region of interest of the line-type measurement cells (spatial-type measurement cells) on layout 104 is mapped to the aligned wafer image (image 523 in fig. 7 as discussed below), and then measurement operation 310 (discussed below) uses the region of interest of the line-type measurement cells (spatial-type measurement cells) on layout 104 to crop the sub-image (operation 902 in fig. 9A as discussed below).

In some embodiments, the polygon-based layout analysis 302 identifies polygons having a length less than a first threshold size, e.g., 10 nanometers (nm). For example, each of the polygons 423, 425, and 427 is determined to have a length less than 10nm by the polygon-based layout analysis 302. However, it should be noted that in some embodiments, the first threshold size of 10nm is a design choice, and embodiments are not limited thereto. In other embodiments, the first threshold size may be set at about 5nm to about 20nm. Polygons 423, 425, and 427 having a size less than the first threshold are identified in fig. 3 as discarded polygons (discarded polygon). Polygons within a range of a second threshold size, e.g., 20nm, located at an end of the longitudinal distance containing pattern of polygons are also identified as discarded polygons. In some embodiments, the second threshold size may be set at about 10nm to about 30nm. For example, the polygon 451 in the pattern 403 is located within 20nm of the longitudinal distance of one end 450 of the pattern 403 and is identified as a discarded polygon. Furthermore, a portion of the polygon within 20nm of the longitudinal distance that encompasses one end of the pattern of polygons is also discarded. For example, the portion 461 of the pattern 403 is located within 20nm of the end 460 of the pattern 403 and is identified as a discarded polygonal portion.

As discussed below, when performing the measurement unit placement, the automatic measurement unit placement 304 ignores discarded polygons or discarded polygon portions identified during the polygon-based layout analysis 302. In other words, the measurement unit is not placed in the discarded polygon or in the portion of the discarded polygon within a threshold (e.g. 20 nm) distance. The reason for this is that the mask features representing one end of the pattern cannot be properly reproduced during exposure. For example, the shape of one end of the pattern will be replicated as circular or elliptical, rather than sharp edges. It should be noted that if the remaining portion of the polygon or pattern meets the length criteria discussed below, the measurement unit may be placed in the remaining portion of the other polygons of the pattern. Thus, it should be appreciated that in some embodiments, the entire polygon is not discarded.

The polygon-based layout analysis 302 identifies polygons having a length (10 nm < l <20 nm) that is greater than a smaller threshold size, such as 10nm, and less than a larger threshold size, such as 20 nm. These polygons are called isolated polygons. The operation of automatic measurement cell placement 304 places a single measurement cell (denoted by 'X') on opposite sides of each isolated polygon. As shown in fig. 3, the polygon 471 is identified as an isolated polygon, and the measurement unit 481 is placed on each of opposite sides of the polygon 471 along the longitudinal direction.

The polygon-based layout analysis 302 identifies polygons having a length greater than a second threshold size, e.g., 20 nm. For each such polygon, the polygon-based layout analysis 302 divides the polygon into a plurality of sections. In one embodiment, the length of each segment is between 8 pixels and 96 pixels. In other embodiments, the length of each segment is between 16 and 84 pixels. In still other embodiments, each segment is 32 pixels in length. It should be appreciated that the length of the segments is a design choice and may be increased or decreased depending on the design and application requirements. The segment length may also be selected based on the processing capabilities of the control system (e.g., system 1100, fig. 11). In some cases, a lower pixel length increases processing time, but requires less memory, while a higher pixel length shortens processing time, but requires more memory.

The multiple sections in each polygon have the same width. Such polygons are referred to as group (polygons). The operation of automatic measurement cell placement 304 places a single measurement cell on opposite sides of each segment of the group polygon.

FIG. 3 shows a group polygon 441 including sections 444, 446, and 448, each of the sections 444, 446, and 448 having the same width. A measurement unit 481 is then placed in each of the sections 444, 446 and 448. Two or more measurement units may be placed in each section. It should be noted, however, that the group is not limited to polygons from the same pattern. In some embodiments, polygons of the same width but partially spaced apart are also grouped together. For example, sections 464, 466, and 468 from pattern 431 and having the same width as sections 444, 446, and 448 are combined with sections 444, 446, and 448. Alternatively, if a polygon has a different width than other polygons of a pattern, then polygons from the same pattern are classified into different groups.

It should be noted that the operations of identifying different polygons and polygon portions in the provided layout 104 through the polygon-based layout analysis 302 first, and then providing the layout 104 with the identified different polygons and polygon portions to the automatic measurement unit placement 304. It should be noted that the polygonal lengths of 10nm and 20nm discussed in the above embodiments are exemplary. In other embodiments, the polygon length may be increased or decreased depending on design and application requirements.

The layout 104 with the placed measurement cells is then provided to an operation of image-to-GDS alignment 308. The image-to-GDS alignment 308 operation also provides a CD-SEM image 201 of the circuit pattern. The CD-SEM image 201 is pre-processed in the operation of the image pre-processing 306. The operation of image pre-processing 306 improves the quality of the CD-SEM image 201 for processing through the operation of image-to-GDS alignment 308 and other components in the wafer design image analysis module 202. For example, image preprocessing includes suppressing unwanted distortion or enhancing some of the image features required for further processing.

image-to-GDS alignment 308 aligns CD-SEM image 201 with designed layout 104. FIG. 4 illustrates a process flow of operations of image-to-GDS alignment 308 according to some embodiments of the present disclosure. The operations of image-to-GDS alignment 308 include rasterization (rasterization) 503, coarse search (coarse search) 502, feature extraction (feature extraction) 504, and fine search (fine search) 506.

The rough search 502 operates on a pre-processed image output from the image pre-processing and a binarized image of the design layout 104 obtained from the operation of rasterizing 503. In the image preprocessing 306, an average filter (average filter) is applied to smooth the noise of the wafer image 201. The operation of rasterizing 503 is performed on the layout 104 to obtain a raster image of the layout 104. The raster image is then converted into a binarized image of the layout 104. The binarized image is a digital image having only two possible values for each pixel. In some embodiments, the two colors used for the binarized image are black and white.

Referring briefly to FIG. 5A, an illustration of a CD-SEM image 201 and a corresponding binarized wafer image 505 is shown. Fig. 5B also shows an exemplary layout 104 and corresponding binarized image 501 taken from the operation of rasterizing 503. The rough search 502 processes the pre-processed image 511 using a series of morphological operations (morphological operations), then performs an Otsu thresholding process to obtain a binarized wafer image 505, and then aligns the binarized wafer image 505 with the binarized image 501.

In general, the layout 104 is larger in size (dimension) than the wafer image 201. The binarized image 501 is also larger than the binarized wafer image 505. In one embodiment, to align the binarized wafer image 505 with the binarized image 501, the binarized wafer image 505 is moved (or otherwise adjusted) over the binarized image 501 until a position is found where cross-correlation of the binarized wafer image 505 with the binarized image 501 is minimized. Once the binary wafer image 505 and the binary image 501 have been aligned, the binary image 501 surrounding the binary wafer image 505 is cropped (diced) to obtain a cropped GDS image 521 (see fig. 7).

Returning to fig. 4, after alignment, the wafer image 201 is provided to the feature extraction 504 operation, wherein the wafer image 201 is further processed. Fig. 6 illustrates images taken at various processing steps performed during operation of feature extraction 504, according to some embodiments of the present disclosure. The operation of feature extraction 504 applies an edge detection algorithm (edge detection algorithms) to the pre-processed image 511, and then identifies left and right points on each object (e.g., hole, line/space in wafer image 201) in the processed image 511, as shown in image 513, where the left point is the rising edge along the horizontal intensity line and the right point is the falling edge along the horizontal intensity line. For purposes of discussion herein, circuit features on a semiconductor wafer are referred to as objects in an image of a circuit pattern. Thus, for each feature, there is a corresponding object on the wafer image. Filtered (filtered) image 513 to obtain image 515. In image 513, each object includes four edge lines, a left point at the left edge, a right point at the left edge, a left point at the right edge, and a right point at the right edge. The two inner edge lines in image 513 merge to form a centerline 527.

A plurality of feature points are then inserted on each object in image 515. In one embodiment, a plurality of feature points are inserted on the upper, lower, left and right sides of each object. A resulting image 517 is shown containing feature points 531. A close-up view of a portion of the image 517 shows the feature points 531 on different objects in detail.

The image 517 is then provided to the fine search 506 for further processing. Fig. 7 illustrates the operation of the fine search 506, wherein the image 517 is aligned with the cropped GDS image 521 to obtain a fine-matched image 523. The image 517 and the cropped GDS image 521 are aligned so that the region of interest on the layout 104 should be provided with an aligned wafer image 523. The measurement operation 310 then clips the sub-image (802 in fig. 8A) for measurement processing. In other words, the image 523 is the wafer image 201 on which the region of interest is marked. Then, the measurement operation 310 is performed on the fine-matched image 523.

The measurement operation 310 determines the size, e.g., critical dimension (critical dimension, CD), of each object on the wafer image 201. During the measurement operation 310, each object on the wafer image 201 is identified as a line/space or a via, according to aspect ratio (aspect ratio).

FIG. 8A illustrates a process 800 performed during a measurement operation 310 when an object is identified as a hole, according to some embodiments of the present disclosure. Each hole in the fine-matched image 523 is analyzed individually to determine its critical dimension. Operation 802 comprises extracting an image of the hole for analysis from the fine-matched image 523 to obtain a sub-image. Then, in operation 804, image interpolation is performed on the image (image interpolation). In one embodiment, during image interpolation, intensity values for one or more locations of the image are determined. At operation 806, the center of the hole is extracted. Briefly, active contour modeling (active contour modeling) is used to find a closed contour (closed contour) from an interpolated image. The center of the hole object is then obtained by calculating the centroid (center-of-mass) of the closed contour. The image is smoothed in operation 808 and radial setting (radial setting) is performed in operation 810. During radial placement, the holes are divided into 32 radial (or slices) and the edges of the holes in each radial are determined. An intensity extraction (intensity extraction) operation is performed at operation 812. During the intensity extraction operation, the intensity of the line is extracted along each radial image from the center to the image boundary. Referring to fig. 8B, an image of a hole, for example, taken from image 523 is shown. As shown, along the edges, the "inside" of the hole is darker than the "outside" of the hole, thus representing different intensity values. Then, a threshold method (threshold) operation is performed at operation 814. In a thresholding method operation, a threshold value is determined for each intensity line, the threshold value being the average of the maximum intensity and the minimum intensity along the intensity line.

At operation 816, a measurement point extraction operation is performed in which inner edge points in each radial intensity line are determined. The inner edge point is the first intersection from the center where the intensity is greater than the threshold determined at 814. Fig. 8B shows the intersection 851. At operation 818, a (fixed) ellipse 811 is fitted along the intersection. The major axis of the ellipse 811 is measured at operation 820 and determined to be the critical dimension (critical dimension, CD) 831 of the hole at operation 822. The measurement operation 310 is repeated for each hole in the image.

Fig. 9A illustrates a process flow 900 performed during a measurement operation 310 when an object is identified as a line (or space) in accordance with some embodiments of the present disclosure. Each line (or space) in the image 523 is analyzed individually to determine its critical dimension. In some embodiments, the process flow 900 is described with reference to measuring critical dimensions of a line. It should be understood that the described operations are equally applicable to measuring critical dimensions of a space. Operation 902 comprises extracting an image of the line for analysis from the fine matching image 523. At operations 904 and 906, a vertical smoothing operation and a horizontal smoothing operation are performed, respectively. Then, a threshold method (threshold) operation is performed at operation 908. In the thresholding operation, the smoothed image is vertically averaged to form a horizontal intensity line. The threshold is calculated as the average of the maximum and minimum values along the intensity line. Each pixel in the image (or at least along the edge) is replaced with a black pixel if the image intensity of the pixel is less than a desired value, or a white pixel if the image intensity of the pixel is greater than the desired value. At operation 910, an edge of the line is then determined. Referring to fig. 9B, an image of a line 911 acquired from an image 523 is shown, for example. As shown, along the edges, the inside of the line is darker than the outside of the line, thus representing different intensity values. The edge is determined as the location where the intensity line crosses the threshold. The distance between the edges is calculated in operation 912. This distance is then determined as the individual critical dimension (individual critical dimension, ind_cd) of the line (or segment in the polygon) and provided to operation 914.

FIG. 10 is a process flow 1000 that illustrates operations performed by layer/measurement unit related determination 312 in accordance with some embodiments of the present disclosure. It should be appreciated that additional operations may be provided before, during, and after the processing discussed in fig. 10, and that some of the operations described below may be replaced or eliminated for additional embodiments of the operations. The order of operations/processes may be interchanged and at least some of the operations/processes may be performed in different orders. At least two or more operations/processes may be performed overlapping in time or nearly simultaneously.

The operation of layer/measurement unit related determination 312 receives output from measurement operation 310. At operation 1002, process flow begins by examining a group containing segments to be analyzed in the data received from measurement operation 310. In one embodiment, the sections include sections 444, 446, 448, 464, 466, and 468 in fig. 3. The number of segments in the group is counted in operation 1004. If the count value is greater than or equal to a first threshold count value, such as 30 (count value > 30), the process passes to operation 1006, which determines whether each segment meets the designed target value. The designed target value may be line width or line spacing or other specified design parameters. Specifically, at operation 1006, a normal distribution of critical dimensions of the segment is generated (normal distribution), and an average of the critical dimensions (denoted mean) is taken from the normal distribution. The average value (indicated mean in the figure) is subtracted from the critical dimension (critical dimension of individual segment, ind_cd) of the individual segments and the result (absolute value) is compared with the maximum value (indicated max in the figure) of 3σ (standard deviation of the average value) and with 10% of the average value. If the absolute value is greater than the maximum value of 3σ (standard deviation of the mean) (denoted max in the figure) and a number of 10% of the mean, then the individual segment is identified as Failed (FAIL) (referred to as out-of-specification (Out Of Specification, OOS). Failure (FAIL) indicates that the critical dimension CD on the wafer is not within an acceptable range of values and that it indicates that the circuit feature was not properly exposed, or alternatively, that the circuit feature was properly exposed by (PASS).

If the count value is greater than a second threshold count value, e.g., 4, and less than the first threshold count value 30 (4 < count value < 30), the process proceeds to operation 1008, which determines whether each segment meets the designed target value, but under a different criteria than operation 1006. The designed target value may be line width or line spacing or other specified design parameters. Specifically, at operation 1008, other distributions of critical dimensions for the segment are generated and an average (denoted mean') of the critical dimensions is taken from the normal distribution. The average value (indicated as mean' in the figure) is subtracted from the critical dimension (ind_cd) of the individual segments and the result (absolute value) is compared with a number 10% of the average value. If the absolute value is greater than the number of 10% of the average value, then the individual segment is determined to be Failed (FAIL).

As discussed, operations 1006 and 1008 of the process flow determine whether individual segments are Failed (FAIL) based on a normal distribution of the critical dimensions of the segments. However, if the count value is smaller than the third threshold count value 4 (count value < 4), the number of segments is too small to generate a distribution.

Process flow advances to operation 1010 where it is determined whether operation 1006 or operation 1008 represents a Failed (FAIL) segment. If either operation 1006 or operation 1008 does not represent a Failed (FAIL) segment, i.e., "No (N"), then process flow advances to operation 1002.

If operation 1006 or operation 1008 indicates a Failed (FAIL) segment, i.e., "Yes (Y)", or a segment with a group count+.4, then process flow advances to operation 1012. In operation 1012, it is determined whether a reference critical dimension (reference critical dimension, ref_cd) is available. If available, i.e., "yes," then at operation 1014, the absolute value of the difference between the unacceptable critical dimension (defective unacceptable (or less desirable)) critical dimension value (def_cd) (i.e., the individual critical dimension value CD that was Failed (FAIL) at operation 1006 or 1008) and the reference critical dimension ref_cd is compared to a number of 10% ref_cd. If the absolute value of the difference is greater than 10% ref_cd, then the individual sector is considered Failed (FAIL), otherwise it is considered PASS (PASS).

If it is determined at operation 1012 that the reference critical dimension ref_cd is not available, i.e., "no (N)", process flow then advances to operation 1016. Here, the absolute value of the difference between the unacceptable (or less desirable) critical dimension value def_cd (i.e., the individual critical dimension value CD that was Failed (FAIL) in operation 1006 or 1008) and the GDS target value (gds_target) (i.e., the value of the critical dimension CD corresponding to the polygon of the segment) is compared to a number of 10% gds_target. If the absolute value of the difference is greater than 10% GDS target, then the individual segment is considered Failed (FAIL), otherwise it is considered PASS (PASS).

If either of the results of operations 1014 and 1016 is FAIL (FAIL), an indication is sent to the user. Failure (FAIL) indicates that the corresponding feature on the mask needs to be repaired prior to exposure, and then the user can repair the mask to correct the feature. If the result of operations 1014 and 1016 is a PASS (PASS), then it is determined that the circuit pattern is implemented on the wafer by design. The process is then repeated for each set of segments.

Fig. 11 illustrates a system 1100 for performing image quality verification (image qualification) according to some embodiments of the present disclosure. The client host 1102 includes a processor 1112 for executing a plurality of instructions stored in a memory 1120. Memory 1120 may include an application 1122 that includes commands that when executed by processor 1112 cause client host 1112 to perform methods consistent with embodiments of the present disclosure. The application 1122 may comprise a runtime software program (runtime software program) running on the client host 1102 to issue commands to control the image quality verification tool 1103, including the wafer design image analysis module 202. For example, the application 1122 includes an application for controlling the image quality verification tool 1103 to perform image quality verification using the wafer design image analysis module 202. The client host 1102 also includes a communication module 1118 that enables the client host 1102 to transmit data, provide commands, and receive instructions from the image quality verification tool 1103 over a network 1150. In some embodiments, the client host 1102 is coupled with an input device 1114 (e.g., mouse, keyboard, touch screen display, etc.), and the client host 1102 is coupled to an output device 1116 (e.g., display, speaker, etc.). Accordingly, a user of the client host 1102 may input commands and queries to the client host 1102 using the input device 1114 and receive graphical or other information from the client host 1102 via the output device 1116. In some embodiments, the application 1122 controls the input device 1114 and the output device 1116 through a graphical user interface (graphic user interface, GUI) so that a user can access the image quality verification tool 1103 and perform image quality verification.

The image quality verification tool 1103 includes a memory device 1130, a processor 1136 and a communication module 1138 for transmitting data, receiving commands and providing instructions from the client host 1102 via the network 1150. In some embodiments, the wafer design image analysis module 202 includes sub-modules for implementing different operations for performing polygon-based layout analysis 302, automatic measurement unit placement 304, image pre-processing 306, image-to-GDS alignment 308, measurement 310, and layer/measurement unit related determination 312. As shown, the wafer design image analysis module 202 includes a polygon-based layout module 1152 for performing the polygon-based layout analysis 302, an automatic measurement unit placement module 1154 for performing the automatic measurement unit placement 304, an image pre-processing module 1156 for performing the image pre-processing 306, an image-to-GDS alignment module 1158 for performing the image-to-GDS alignment 308, a measurement module 1160 for performing the measurement 310, and a layer/measurement unit related determination module 1162 for performing the layer/measurement unit related determination 312. Furthermore, each of the operations of rasterization 503, coarse search 502, feature extraction (feature extraction) 504, and fine search 506 in FIG. 4 is implemented using one or more modules within the image-to-GDS alignment module 1158. Further, operations 802, 804, 806, 808, 810, 812, 814, 816, 818, 820, and 822 (fig. 8), and operations 902, 904, 906, 908, 910, 912, and 914 (fig. 9) are implemented using one or more modules within measurement module 1160. In one embodiment, the wafer design image analysis module 202 is implemented in software as computer executable program code (computer executable program code) executed by the processor 1136. In other embodiments, the wafer design image analysis module 202 is implemented in hardware as a logic gate. In still other embodiments, the wafer design image analysis module 202 is implemented in a combination of hardware/software. The database 1140 stores data results from operations performed by the image quality verification tool 1103. In some embodiments, database 1140 stores data required by the different modules to perform the corresponding operations.

Fig. 12 is a flowchart illustrating a method 1200 of image quality verification (image qualification) according to some embodiments of the present disclosure. It should be appreciated that additional operations may be provided before, during, and after the processing discussed in fig. 12, and that some of the operations described below may be replaced or eliminated for additional embodiments of the operations. The order of operations/processes may be interchanged and at least some of the operations/processes may be performed in different orders. At least two or more operations/processes may be performed overlapping in time or nearly simultaneously.

The method 1200 includes an operation S1202 of obtaining a layout of a circuit pattern implemented on a semiconductor wafer. In operation S1204, one or more polygons in the layout are identified based on the length criteria. In operation S1206, one or more measurement units are placed on the identified polygon, thereby obtaining a plurality of measurement target polygons. In operation S1208, a scanning electron microscope (scanning electron microscope, SEM) image of the circuit pattern is acquired. In some embodiments, critical dimension scanning electron microscopy (critical dimension SEM, CD-SEM) is used to obtain the image. In operation S1210, the SEM image is aligned with the layout including the measurement target polygon. At operation 1212, critical dimensions of one or more objects in the SEM image are measured. The one or more objects correspond to a measurement target polygon. In operation S1214, it is determined whether the circuit pattern is acceptable based on the measured critical dimension.

In one embodiment of the present disclosure, a wafer design image analysis method is provided, comprising: obtaining a layout of circuit patterns implemented on a semiconductor wafer; identifying one or more polygons in the layout based on the length criteria; placing one or more measurement units on the identified polygon, thereby obtaining a plurality of measurement target polygons; obtaining (scanning electron microscope, SEM) images of the circuit patterns; aligning the SEM image with a layout including a measurement target polygon; measuring critical dimensions of one or more objects in the SEM image corresponding to the measurement target polygon; and determining whether the circuit pattern is acceptable based on the measured critical dimension. In an embodiment, wherein identifying one or more polygons in the layout based on the length criteria includes: identifying a first polygon having a length greater than a first threshold size; and identifying a plurality of segments of the first polygon, wherein each segment has a length equal to the second threshold size. In one embodiment, the placing one or more measurement units therein comprises: one or more measurement units are placed in each of the segments of the first polygon. In an embodiment, each of the sections has the same width. In an embodiment, wherein identifying one or more polygons in the layout based on the length criteria further includes: a second polygon having a length greater than the third threshold size and less than the first threshold size is identified. In one embodiment, the placing one or more measurement units therein comprises: the measuring unit is placed on the second polygon. In an embodiment, the method further comprises: measuring the total critical dimension of the segments in the first polygon; generating a normal distribution of critical dimensions (normal distribution); calculating an average value of critical dimensions from the normal distribution; comparing the critical dimension of the measured object with the average value to obtain a comparison result; and determining whether the circuit pattern is acceptable based on the comparison result. In an embodiment, the method further comprises: when the critical dimension of the measured object is greater than the average value, the circuit pattern is determined to be unacceptable. In an embodiment, the method further comprises: when the critical dimension of the measured object is less than the average value, the circuit pattern is determined to be acceptable.

In another embodiment of the present disclosure, a wafer design image analysis system is provided, comprising: a memory for storing a plurality of instructions and at least one processor. The at least one processor is configured to execute instructions to: obtaining a layout of circuit patterns implemented on a semiconductor wafer; identifying a first polygon having a length greater than a first threshold size; identifying a plurality of segments of the first polygon, wherein each segment has a length equal to a second threshold size; placing one or more measurement units on the identified plurality of polygons, thereby obtaining measured polygons; aligning the SEM image of the circuit pattern with a layout comprising the measured polygons; measuring critical dimensions of one or more objects in the SEM image corresponding to one or more polygons in the layout; and determining whether the circuit pattern is acceptable based on the measured critical dimension. In one embodiment, at least one processor executes instructions to: one or more measurement units are placed in each of the segments of the first polygon. In an embodiment, each of the sections has the same width. In one embodiment, at least one processor executes instructions to: a second polygon having a length greater than the third threshold size and less than the first threshold size is identified. In one embodiment, at least one processor executes instructions to: the measuring unit is placed on the second polygon. In one embodiment, at least one processor executes instructions to: measuring the total critical dimension of the segments in the first polygon; generating a normal distribution of critical dimensions; calculating an average value of critical dimensions from the normal distribution; comparing the measured critical dimension of the one or more objects with the average value to obtain a comparison result; and determining whether the circuit pattern is acceptable based on the comparison result. In one embodiment, at least one processor executes instructions to: when the critical dimension of the measured object is greater than the average value, the circuit pattern is determined to be unacceptable. In one embodiment, at least one processor executes instructions to: when the critical dimension of the measured object is less than the average value, the circuit pattern is determined to be acceptable.

In another embodiment of the present disclosure, a non-transitory computer readable medium is provided that stores a plurality of instructions that when executed by a processor cause a computer to perform a method comprising: obtaining a layout of circuit patterns implemented on a semiconductor wafer; identifying a first polygon having a length greater than a first threshold size; identifying a plurality of segments of the first polygon, wherein each segment has a length equal to a second threshold size; placing one or more measurement units on the identified plurality of polygons, thereby obtaining measured polygons; obtaining an SEM image of the circuit pattern; aligning the SEM image with a layout comprising the measured polygon; measuring critical dimensions of one or more objects in the SEM image corresponding to one or more polygons in the layout; measuring the total critical dimension of the segments in the first polygon; generating a normal distribution of critical dimensions; calculating an average value of critical dimensions from the normal distribution; comparing the measured critical dimension of the one or more objects with the average value to obtain a comparison result; and determining whether the circuit pattern is acceptable based on the comparison result. In an embodiment, the method further comprises: a second polygon having a length greater than the third threshold size and less than the first threshold size is identified. In one embodiment, the placing one or more measurement units therein comprises: placing one or more measurement units in each of the segments of the first polygon; and placing the measurement unit on the second polygon.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the embodiments of the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims (19)

1. The wafer design image analysis method is characterized by comprising the following steps:

obtaining a layout of circuit patterns implemented on a semiconductor wafer;

identifying one or more polygons in the layout based on length criteria, wherein the one or more polygons include a plurality of discarded polygons;

placing one or more measurement units on the one or more polygons identified in the layout, and not placing the one or more measurement units on the discarded polygons identified in the layout;

obtaining a Scanning Electron Microscope (SEM) image of the circuit pattern implemented on the semiconductor wafer by a critical dimension SEM;

Aligning the SEM image with the layout including the one or more polygons identified in the layout;

clipping the SEM image by the one or more measurement units on the one or more polygons, wherein one or more objects in the SEM image are included within one or more regions of interest of the SEM image clipped by the one or more measurement units;

measuring critical dimensions of the one or more objects in the SEM image, wherein the one or more objects correspond to the one or more polygons identified in the layout; and

determining whether the circuit pattern is acceptable based on the measured critical dimension; wherein identifying the one or more polygons in the layout based on the length criteria includes:

identifying a first polygon having a length greater than a first threshold size as one of the polygons;

identifying a plurality of segments of the first polygon, wherein each of the segments has a length equal to a second threshold size; and

a second polygon having a length less than the first threshold size is identified as the discarded polygons along with a polygon portion within a third threshold size from one end of the pattern of the layout.

2. The method of claim 1, wherein positioning the one or more measurement units comprises:

the one or more measurement units are placed in each of the segments of the first polygon.

3. The method of claim 1, wherein each of the segments has the same width.

4. The method of claim 1, wherein identifying the one or more polygons in the layout based on the length criterion further comprises:

a third polygon having a length greater than a fourth threshold size and less than the first threshold size is identified.

5. The method of claim 4, wherein positioning the one or more measurement units comprises:

the measuring unit is placed on the third polygon.

6. The method as recited in claim 1, further comprising:

measuring all of the critical dimensions of the segments in the first polygon;

generating normal distribution of the critical dimensions;

calculating an average of the critical dimensions from the normal distribution;

comparing the measured critical dimension of the object with the average value to obtain a comparison result; and

It is determined whether the circuit pattern is acceptable based on the comparison result.

7. The method as recited in claim 6, further comprising:

when the measured critical dimension of the object is greater than the average value, the circuit pattern is determined to be unacceptable.

8. The method as recited in claim 6, further comprising:

when the measured critical dimension of the object is less than the average value, the circuit pattern is determined to be acceptable.

9. A wafer design image analysis system, comprising:

a memory for storing a plurality of instructions; and

at least one processor configured to execute the instructions to:

obtaining a layout of circuit patterns implemented on a semiconductor wafer;

identifying a first polygon having a length greater than a first threshold size;

identifying a plurality of segments of the first polygon, wherein each of the segments has a length equal to a second threshold size;

identifying a second polygon having a length less than the first threshold size and identifying a portion of the polygon within a third threshold size from one end of the pattern of the layout as a plurality of discarded polygons;

placing one or more measurement units on the first polygon and not placing the one or more measurement units on the discarded polygons identified in the layout;

Aligning an SEM image of the circuit pattern implemented on the semiconductor wafer obtained by CD-SEM with the layout including the first polygon, wherein the first polygon includes the one or more measurement cells;

clipping the SEM image by the one or more measurement units on the one or more polygons, wherein one or more objects in the SEM image are included within one or more regions of interest of the SEM image clipped by the one or more measurement units;

measuring critical dimensions of the one or more objects in the SEM image, wherein the one or more objects correspond to the first polygon including the one or more measurement units; and

a determination is made as to whether the circuit pattern is acceptable based on the measured critical dimension.

10. The system of claim 9, wherein the at least one processor executes the instructions to:

the one or more measurement units are placed in each of the segments of the first polygon.

11. The system of claim 10, wherein each of the segments has the same width.

12. The system of claim 10, wherein the at least one processor executes the instructions to:

A third polygon having a length greater than a fourth threshold size and less than the first threshold size is identified.

13. The system of claim 12, wherein the at least one processor executes the instructions to:

the measuring unit is placed on the third polygon.

14. The system of claim 10, wherein the at least one processor executes the instructions to:

measuring all of the critical dimensions of the segments in the first polygon;

generating normal distribution of the critical dimensions;

calculating an average of the critical dimensions from the normal distribution;

comparing the measured critical dimensions of the one or more objects with the average value to obtain a comparison result; and

it is determined whether the circuit pattern is acceptable based on the comparison result.

15. The system of claim 14, wherein the at least one processor executes the instructions to:

when the measured critical dimension of the object is greater than the average value, the circuit pattern is determined to be unacceptable.

16. The system of claim 14, wherein the at least one processor executes the instructions to:

When the measured critical dimension of the object is less than the average value, the circuit pattern is determined to be acceptable.

17. A non-transitory computer readable medium storing instructions that when executed by a processor cause a computer to perform a method comprising:

obtaining a layout of circuit patterns implemented on a semiconductor wafer;

identifying a first polygon having a length greater than a first threshold size;

identifying a plurality of segments of the first polygon, wherein each of the segments has a length equal to a second threshold size;

identifying a second polygon having a length less than the first threshold size and identifying a portion of the polygon within a third threshold size from one end of the pattern of the layout as a plurality of discarded polygons;

placing one or more measurement units on the first polygon and not placing the one or more measurement units on the discarded polygons identified in the layout;

obtaining an SEM image of the circuit pattern implemented on the semiconductor wafer by CD-SEM;

aligning the SEM image with the layout including the first polygon, wherein the first polygon includes the one or more measurement units;

Clipping the SEM image by the one or more measurement units on the one or more polygons, wherein one or more objects in the SEM image are included within one or more regions of interest of the SEM image clipped by the one or more measurement units;

measuring a critical dimension of the one or more objects in the SEM image, wherein the one or more objects correspond to the first polygon including the one or more measurement units;

measuring all of the critical dimensions of the segments in the first polygon;

generating normal distribution of the critical dimensions;

calculating an average of the critical dimensions from the normal distribution;

comparing the measured critical dimensions of the one or more objects with the average value to obtain a comparison result; and

it is determined whether the circuit pattern is acceptable based on the comparison result.

18. The non-transitory computer readable medium of claim 17, further comprising:

a third polygon having a length greater than a fourth threshold size and less than the first threshold size is identified.

19. The non-transitory computer readable medium of claim 18, wherein placing the one or more measurement units comprises:

Placing the one or more measurement units in each of the segments of the first polygon; and

the measuring unit is placed on the third polygon.

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