CN110888589B - Flash memory controller and related access method and electronic device - Google Patents
Flash memory controller and related access method and electronic device Download PDFInfo
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- CN110888589B CN110888589B CN201811045853.1A CN201811045853A CN110888589B CN 110888589 B CN110888589 B CN 110888589B CN 201811045853 A CN201811045853 A CN 201811045853A CN 110888589 B CN110888589 B CN 110888589B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
The invention discloses a flash memory controller, which comprises an artificial intelligent module and a microprocessor. In the operation of the flash memory controller, the artificial intelligent module is used for determining a first user behavior mode or a second user behavior mode according to a plurality of access commands from a main device and/or a plurality of parameters of a flash memory module controlled by the flash memory controller, and generating a judging result according to the first user behavior mode or the second user behavior mode; and when the judging result is the first user behavior mode, the microprocessor adopts a first control strategy to control the flash memory module; and when the judging result is the second user behavior mode, the microprocessor adopts a second control strategy which is different from the first control strategy to control the flash memory module.
Description
Technical Field
The present invention relates to a flash memory controller.
Background
In the current flash memory controller, the control strategy adopted for the flash memory module is set by engineers according to the presupposed user behavior so as to set related algorithms and parameters. For example, the flash memory controller may employ the same garbage collection trigger conditions, the same wear leveling operation, and the same trigger mechanism for the read scan operation, however, the usage behaviors of different users may vary greatly, and the usage behaviors of the same user may vary with time, so that the system performance may not be optimized if the same control strategy is employed to control the flash memory module.
For example, housewives or office workers may be on-line or reading data most of the time, and therefore the comparison pursued is biased to optimize the reading behavior of the flash memory module; students may often download files or write documents, and thus the comparisons sought are biased toward optimizing the writing behavior of flash memory modules. In addition, in addition to the consideration of the read and write performance, the damage to the flash memory module caused by different user behaviors is also different, so that the pre-control and post-remediation of the potential damage caused by different user behaviors are important issues.
Disclosure of Invention
It is therefore one of the objectives of the present invention to provide a flash memory controller that can control the operation of a flash memory module according to different control strategies based on user behavior, so as to provide an optimal processing method for the performance and lifetime of the flash memory module, thereby solving the problems described in the prior art.
In one embodiment of the present invention, a flash memory controller is disclosed that includes an artificial intelligence module and a microprocessor. In the operation of the flash memory controller, the artificial intelligent module is used for determining a first user behavior mode or a second user behavior mode according to a plurality of access commands from a main device and/or a plurality of parameters of a flash memory module controlled by the flash memory controller, and generating a judging result according to the first user behavior mode or the second user behavior mode; and when the judging result is the first user behavior mode, the microprocessor adopts a first control strategy to control the flash memory module; and when the judging result is the second user behavior mode, the microprocessor adopts a second control strategy which is different from the first control strategy to control the flash memory module.
In another embodiment of the present invention, a method for accessing a flash memory module is disclosed, comprising the steps of: determining a first user behavior mode or a second user behavior mode according to a plurality of access commands from a main device and/or a plurality of parameters of a flash memory module controlled by the flash memory controller, and generating a judging result according to the first user behavior mode or the second user behavior mode; when the judging result is the first user behavior mode, the microprocessor adopts a first control strategy to control the flash memory module; and when the judging result is the second user behavior mode, the microprocessor adopts a second control strategy which is different from the first control strategy to control the flash memory module.
In another embodiment of the present invention, an electronic device is disclosed, which comprises a flash memory module and a flash memory controller, wherein the flash memory controller comprises an artificial intelligence module and a microprocessor. In the operation of the flash memory controller, the artificial intelligent module is used for determining a first user behavior mode or a second user behavior mode according to a plurality of access commands from a main device and/or a plurality of parameters of a flash memory module controlled by the flash memory controller, and generating a judging result according to the first user behavior mode or the second user behavior mode; and when the judging result is the first user behavior mode, the microprocessor adopts a first control strategy to control the flash memory module; and when the judging result is the second user behavior mode, the microprocessor adopts a second control strategy which is different from the first control strategy to control the flash memory module.
Drawings
Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the invention.
FIG. 2 is a schematic diagram showing a flash memory module including a plurality of blocks, and each block includes a plurality of data pages.
FIG. 3 is a flow chart of a method for accessing a flash memory module according to an embodiment of the invention.
Symbol description:
100. electronic device
110. Main device
120. Flash memory controller
121. Interface circuit
122. Artificial intelligence module
124. Microprocessor
126. Buffer memory
128. Read only memory
129. Control logic
130. Flash memory module
210_1 to 210_K blocks
300 to 306 steps
P1 to PN data pages
Detailed Description
Fig. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the invention. As shown in FIG. 1, the electronic device 100 comprises a host device 110, a flash memory controller 120 and a flash memory module 130, wherein the flash memory controller 120 comprises an interface circuit 121, an artificial intelligence module 122, a microprocessor 124, a buffer memory 126, a read only memory 128 and a control logic 129. The ROM 213 is used to store a plurality of codes, and the microprocessor 122 is used to execute the codes to control the access to the flash memory module 130, and the devices in the flash memory controller 120 can transfer data through the bus of the figure. In this embodiment, the flash memory controller 120 and the flash memory module 130 can be regarded as a Solid-state drive (SSD), the electronic device 100 can be any computer or server with a Solid-state drive, and the host device 110 can be a processor for accessing the flash memory module 130 through the flash memory controller 120.
The flash memory module 130 includes at least one flash memory chip, each of which includes a plurality of blocks (blocks) and each of which includes a plurality of pages (pages). In the related design of flash memory, each block is a minimum erase unit, i.e., all data in the block is erased together and cannot be erased only in a portion, and each page is a minimum write unit. Referring to FIG. 2, the flash memory module 130 includes a plurality of blocks 210_1 to 210_K, each of which includes a plurality of pages P1 to PN.
In operation of the electronic device 100, the artificial intelligence module 122 is used for determining a user behavior pattern of a user of the electronic device 100 to generate a determination result, and the microprocessor 124 generates a corresponding control strategy to control the flash memory module 130 according to the determination result, so as to optimize the performance of the flash memory controller 120 and the flash memory module 130. For example, the artificial intelligence module 122 can determine that the user operates the electronic device 100 with a first user behavior pattern or a second user behavior pattern to generate the determination result, wherein the first user behavior pattern is used to indicate that the main behavior of the user operating the electronic device 100 is to read the content of the flash memory module 130, but rarely write data into the flash memory module 130, for example, the user is mostly accessing the data or reading the file data stored in the flash memory module 130, and rarely download a large amount of data from the network or use the electronic device 100 to long-time create and edit files, such that the user is similar to some housewives or office workers returning home; the second user behavior pattern is used to indicate that the user has a certain degree of operation on the electronic device 100, for example, a user has a part of time to download a large amount of data from the network, or uses the electronic device 100 to create an edited file for a long time, such as a part of students or engineers.
In this embodiment, the artificial intelligence module 122 can determine whether the user operates the electronic device 100 to bias the read operation (i.e. the first user behavior pattern) or to bias the write operation (i.e. the second user behavior pattern) according to a plurality of access commands from the host device 110 and/or a plurality of parameters of the flash memory module 130, and generate the determination result accordingly. In the first example, the artificial intelligence module 122 generates the determination result according to the occurrence frequency of a read command and the occurrence frequency of a write command from the host device 110. Specifically, the artificial intelligence module 122 can calculate how many write commands and how many read commands the host device 110 sends to the flash memory controller 120 over a period of time to calculate the frequency of occurrence of the read commands and the frequency of occurrence of the write commands. In one example, when the write command frequency is lower than a threshold value and the read command frequency is higher than another threshold value, the artificial intelligence module 122 determines that the user operation of the electronic device 100 is biased to a read operation and determines the first user behavior pattern as the determination result; and when the frequency of the write command is higher than the threshold, or when the frequency of the write command is higher than the threshold and the frequency of the read command is lower than the other threshold, the artificial intelligence module 122 determines that the user operating the electronic device 100 is biased to write operation and determines the second user behavior pattern as the determination result.
In a second example, the artificial intelligence module 122 can generate the determination result according to the number of times of reading the plurality of blocks 210_1 to 210_k in the flash memory module 130. Specifically, during the operation of the electronic device 100, the flash memory controller 120 keeps track of the number of reads of each of the blocks 210_1 to 210_k by the flash memory controller 120, and records the number in the buffer memory 126, and then stores the number in the flash memory module 130. It should be noted that the above-mentioned number of times of reading refers to the number of times of reading that the block starts to count after the data is written, that is, the number of times of reading that the block starts to count again after the block is erased. Therefore, the artificial intelligence module 122 can determine whether the user operates the electronic device 100 to bias the reading operation according to the number of times of reading at least a portion of the blocks 210_1 to 210_k. For example, when the number of times of reading at least a portion of the plurality of blocks 210_1 to 210_k is higher than a threshold, or the average value of the number of times of reading at least a portion of the plurality of blocks 210_1 to 210_k is higher than a threshold, or any parameter capable of indicating the number of times of reading the block is higher than a threshold, the artificial intelligence module 122 determines that the user operation electronic device 100 is biased to the reading operation and determines the first user behavior pattern as the determination result.
In a third example, the artificial intelligence module 122 can generate the determination result according to the generation time difference of each of the blocks 210_1 to 210_k for storing data in the flash memory module 130. Specifically, during the process of writing data into the flash memory module 130 by the flash memory controller 120, if all the data pages P1 to PN of the block to which the flash memory module 130 is currently written are about to be fully written, the flash memory module 130 will additionally establish the next block for data to be written, and the time difference between the establishment of the blocks is referred to as the generation time difference of the blocks. As described above, when the host device 110 continuously issues a write command to write data into the flash memory module 130, the generation time difference of the blocks 210_1 to 210_k is short because new blocks are continuously established to store data; in addition, when the host device 110 rarely issues a write command to write data to the flash memory module 130, the difference in generation time of the blocks 210_1 to 210_k is short. Therefore, if the time difference between the blocks 210_1 to 210_k is longer (for example, the average value of the time difference between the blocks is a period of time), the artificial intelligence module 122 determines that the user operates the electronic device 100 to bias the reading operation and determines the first user behavior pattern as the determination result; if the difference between the generation time of the blocks 210_1 to 210_k is shorter, the artificial intelligence module 122 determines that the user operates the electronic device 100 to bias the writing operation and determines the second user behavior pattern as the determination result.
In a fourth example, the artificial intelligence module 122 may generate the determination result according to the number or frequency of performing wear leveling (wear leveling) operations in the flash memory module 130. Specifically, when the number or frequency of performing the wear-leveling operation is high, it is indicated that the space in the flash memory module 130 may be insufficient or there may be excessive invalid data, i.e., the number of writes to the flash memory module 130 may be frequent. Therefore, when the number or frequency of performing the wear-leveling operation is higher than a threshold, the artificial intelligence module 122 determines that the user operation of the electronic device 100 is biased towards the write operation and determines the second user behavior pattern as the determination result; or when the number or frequency of performing the wear-leveling operation is lower than a threshold, the artificial intelligence module 122 determines that the user is operating the electronic device 100 to bias the reading operation and determines the first user behavior pattern as the determination result.
It should be noted that the above four examples can be used in combination, i.e., the artificial intelligence module 122 generates the determination result according to at least two of the occurrence frequency of the plurality of read commands and the plurality of write commands from the host device 110, the number of reads of the blocks 210_1 to 210_k, the difference in generation time of the blocks 210_1 to 210_k, and the number or frequency of performing the wear-leveling operation in the flash memory module 130. In addition, the above four examples are merely exemplary, and the artificial intelligence module 122 can refer to other parameters related to whether the user operates the electronic device 100 to bias the reading operation or to bias the writing operation to generate the determination result, and the design changes are all within the scope of the present invention.
Then, after the artificial intelligence module 122 determines whether the user operates the electronic device 100 to bias the read operation (i.e., the first user behavior pattern) or to bias the write operation (i.e., the second user behavior pattern), the microprocessor 124 can employ the corresponding control strategy to control the flash memory module 130. Specifically, when the determination result indicates that the user operates the electronic device 100 in the first user behavior mode, since the user behavior is biased towards the read operation, the data in the flash memory module 130 may be damaged due to a problem of data retention (data refresh) caused by long-time non-refresh, and some blocks in the flash memory module 130 may have a problem of read disturb (read disturb), so the first control policy adopted by the microprocessor 124 may include a higher-frequency read scan operation to more actively read all the data pages P1 to PN of some blocks to determine whether the data quality meets the standard, and move the data in the blocks to another block when the data quality does not meet the standard, so as to ensure that the data which is not updated for a long time cannot be wrong; additionally, because the user action has fewer write operations, the first control strategy employed by the microprocessor 124 may include less aggressive garbage collection (garbage collection) operations, such as requiring longer time or more invalid data pages to trigger garbage collection operations, or may include looser wear-leveling operations, such as allowing for higher erase count differences between blocks. In addition, since the user having the first user behavior mode usually has a long time to interrupt the use of the electronic device 100, the first control strategy adopted by the microprocessor 124 may include or be in a more aggressive power saving mode, i.e. the flash memory controller 120 and the flash memory module 130 may be in a power saving mode or a sleep mode more quickly.
On the other hand, when the determination result indicates that the user operation of the electronic device 100 belongs to the second user behavior mode, the flash memory module 130 is less prone to data saving and read disturb because the user behavior is biased towards the write operation, so the second control strategy adopted by the microprocessor 124 may include a lower frequency read scan operation; in addition, since the user action has more write operations, the second control strategy employed by the microprocessor 124 may include more aggressive garbage collection operations, such as requiring less time or fewer invalid data pages to trigger the garbage collection operation, or may include more aggressive wear-leveling operations, i.e., lower erase count differences between allowed blocks. In addition, since the user having the second user behavior mode does not generally interrupt the use of the electronic device 100 for a long time, the second control strategy adopted by the microprocessor 124 may include or be less aggressive in the power saving mode.
In the above embodiments, only two user behavior patterns and two control strategies are used as illustrations, but this is not a limitation of the present invention. In other embodiments, the flash memory controller 120 may also include a plurality of other user behavior patterns, such as the occurrence or frequency of abnormal power-down, or the average idle time of the flash memory controller 120 and the flash memory module 130, and the microprocessor 124 may also generate corresponding control strategies to optimize the performance and lifetime of the flash memory module.
In one embodiment, the artificial intelligence module 122 performs training operations to determine a plurality of judgment logics when the flash memory controller 120 is in an off-line state (on-line), and uses the judgment logics to judge the user behavior pattern when the flash memory controller 120 is in an on-line state (on-line) to generate the judgment result. For example, when the flash memory controller 120 is offline (i.e., the flash memory controller 120 is not yet connected to the flash memory module 130), the engineer may determine a portion of the judgment logic for the artificial intelligence module 122 to train by inputting the simulated access command and the parameters of the simulated flash memory module 130 to the artificial intelligence module 122, wherein the judgment logic may be a mode for judging the behavior of the user.
FIG. 3 is a flowchart of a method for accessing the flash memory module 130 according to an embodiment of the invention. Referring to fig. 1-2 and the disclosure thereof, the flow is as follows.
Step 300: the flow starts.
Step 302: determining a first user behavior mode or a second user behavior mode according to a plurality of access commands from a host device and/or a plurality of parameters of a flash memory module controlled by the flash memory controller to generate a determination result, wherein when the determination result is the first user behavior mode, the flow proceeds to step 304; and when the judgment result is the second user behavior mode, the flow proceeds to step 306.
Step 304: the first control strategy is used to control the flash memory module, wherein the first control strategy comprises a less aggressive garbage collection operation, a higher frequency read scan operation, a looser wear-leveling operation, or a more aggressive power saving mode.
Step 306: the flash memory module is controlled by a second control strategy that includes more aggressive garbage collection operations, less frequent read scan operations, more aggressive wear-leveling operations, or a more relaxed power saving mode.
Briefly summarized, in the flash memory controller of the present invention, an artificial intelligent module is employed to determine a user behavior pattern of a user of the electronic device, and the microprocessor selects a suitable control strategy according to the determined user behavior pattern, so as to have an optimal processing manner for the performance and life of the flash memory module, and also can perform pre-control and post-remediation for the potential damage situation of different user behaviors.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (10)
1. A flash memory controller includes:
an artificial intelligent module for determining a first user behavior mode biased to a read operation or a second user behavior mode biased to a write operation according to a plurality of access commands from a host device of an electronic device and/or a plurality of parameters of a flash memory module controlled by the flash memory controller for determining whether a user is biased to a read operation or a write operation by operating the electronic device, and generating a determination result according to the determination result; and
a microprocessor coupled to the artificial intelligence module, wherein when the judgment result is the first user behavior mode, the microprocessor adopts a first control strategy to control the flash memory module, the first control strategy comprises less aggressive garbage collection operation and higher frequency reading scanning operation, so as to more aggressively read all data pages of a block in the flash memory module to judge whether the data quality meets the standard or not, and when the data quality does not meet the standard, the microprocessor moves the data in the block to another block; and when the judging result is the second user behavior mode, the microprocessor adopts a second control strategy which is different from the first control strategy to control the flash memory module, wherein the second control strategy comprises more active garbage collection operation and lower-frequency reading scanning operation.
2. The flash memory controller of claim 1, wherein the artificial intelligence module determines the first user behavior pattern or the second user behavior pattern according to an occurrence frequency of an access command from the host device, and generates the determination result according to the first user behavior pattern or the second user behavior pattern.
3. The flash memory controller of claim 2, wherein the access command frequency comprises a read command frequency and a write command frequency, and the artificial intelligence module determines the first user behavior pattern or the second user behavior pattern based on at least the write command frequency, and generates the determination result based on the determination result.
4. The flash memory controller of claim 3, wherein the artificial intelligence module determines the first user behavior pattern when the write command occurs at a frequency below a threshold and the read command occurs at a frequency above another threshold; and determining the second user behavior mode by the artificial intelligence module when the occurrence frequency of the writing command is higher than the threshold value.
5. The flash memory controller of claim 4, wherein the first control strategy used by the microprocessor further comprises a looser wear-leveling operation or a more aggressive power saving mode when the determination is the first user behavior mode; and when the judging result is the second user behavior mode, the second control strategy used by the microprocessor also comprises more active wear-leveling operation or more loose power saving mode.
6. The flash memory controller of claim 1, wherein the plurality of parameters includes a number of reads of a plurality of blocks in the flash memory module or a time difference of generation of each block of the flash memory module for storing data.
7. The flash memory controller of claim 6, wherein the first control strategy used by the microprocessor comprises a less aggressive garbage collection operation, a higher frequency read scan operation, a more relaxed wear leveling operation, or a more aggressive power saving mode when the number of reads of blocks in the flash memory module is above a threshold or the difference in generation time of each block in the flash memory module for storing data is above another threshold; and when the number of times of reading the plurality of blocks in the flash memory module is lower than the threshold value or the generation time difference of each block used for storing data in the flash memory module is lower than the other threshold value, the second control strategy used by the microprocessor comprises more active garbage collection operation, lower-frequency reading scanning operation, more active wear-leveling operation or more loose power saving mode.
8. The flash memory controller of claim 1, wherein the plurality of parameters includes a number or frequency of performing wear leveling operations in the flash memory module, a number or frequency of occurrence of abnormal power outages, or an average idle time of the flash memory controller and the flash memory module.
9. A method for accessing a flash memory module includes:
determining a first user behavior mode biased to a read operation or a second user behavior mode biased to a write operation according to a plurality of access commands from a host device of an electronic device and/or a plurality of parameters of the flash memory module controlled by the flash memory controller for judging whether the electronic device is biased to the read operation or the write operation by a user, and generating a judging result according to the first user behavior mode biased to the read operation or the second user behavior mode biased to the write operation;
when the judging result is the first user behavior mode, the microprocessor adopts a first control strategy to control the flash memory module, wherein the first control strategy comprises less aggressive garbage collection operation and higher-frequency reading scanning operation so as to more aggressively read all data pages of a block in the flash memory module to judge whether the data quality meets the standard or not, and when the data quality does not meet the standard, the microprocessor moves the data in the block to another block; and
when the judging result is the second user behavior mode, the microprocessor adopts a second control strategy which is different from the first control strategy to control the flash memory module, and the second control strategy comprises more active garbage collection operation and lower-frequency reading scanning operation.
10. An electronic device, comprising:
a flash memory module; and
a flash memory controller for accessing the flash memory module, comprising:
an artificial intelligent module for determining a first user behavior mode biased to a read operation or a second user behavior mode biased to a write operation according to a plurality of access commands from a host device and/or a plurality of parameters of a flash memory module controlled by the flash memory controller for determining whether a user operates the electronic device to bias to the read operation or bias to the write operation, and generating a determination result according to the determination result; and
a microprocessor coupled to the artificial intelligence module, wherein when the judgment result is the first user behavior mode, the microprocessor adopts a first control strategy to control the flash memory module, the first control strategy comprises less aggressive garbage collection operation and higher frequency reading scanning operation, so as to more aggressively read all data pages of a block in the flash memory module to judge whether the data quality meets the standard or not, and when the data quality does not meet the standard, the microprocessor moves the data in the block to another block; and when the judging result is the second user behavior mode, the microprocessor adopts a second control strategy which is different from the first control strategy to control the flash memory module, wherein the second control strategy comprises more active garbage collection operation and lower-frequency reading scanning operation.
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