CN110880939B - Design method of parallel cascade space coupling RA code - Google Patents
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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Abstract
The invention discloses a design method of parallel cascade space coupling RA codes, which comprises the steps of selecting a (J, K) regular RA code prototype diagram; copying the RA code protographs to obtain L RA code protographs, and sequentially arranging the L RA code protographs, wherein the positions after arrangement are 1,2, … and L respectively; connecting message bit nodes and check bit nodes in L RA code protographs to form a (J, K, L) SCRA code coupling chain; adding check bit nodes and parity bit nodes in a (J, K, L) SCRA code coupling chain to generate an original model graph of the parallel cascade SCRA code; generating parallel cascade SCRA codes according to the original pattern of the parallel cascade SCRA codes; according to the method, the check bit node and the parity bit node are added in the (J, K, L) SCRA code coupling chain, the original graph of the parallel cascade SCRA code is generated through a simple and convenient connection method, the original graph has a randomized structure, an interleaver does not need to be additionally introduced, and interleaving and de-interleaving operation is not needed during coding and decoding, so that the decoding time delay is reduced.
Description
[ technical field ] A method for producing a semiconductor device
The invention belongs to the technical field of error control coding, and particularly relates to a design method of a parallel cascade spatial coupling RA code.
[ background of the invention ]
Spatially Coupled repetitive Summation Codes (SCRA) are a special class of Spatially Coupled Low Density Parity Check codes (SC-LDPC). SC-LDPC codes were proposed by Kudekar et al in 2011, and proved that performance close to performance of a maximum a posteriori probability decoding algorithm adopted by corresponding block LDPC codes can be obtained by adopting a BeliefPropagation (BP) decoding algorithm under Binary Erasure Channel (BEC) and general Binary Memoryless Symmetry (BMS) channels, which is called "threshold saturation", and SC-LDPC codes also become a research hotspot because they have excellent performance of reaching a capacity limit under a low-delay, high-efficiency storage sliding window decoding algorithm.
The coupling chain construction method of the SCRA code is similar to that of the SC-LDPC code, and specifically comprises the following steps: the master pattern of a simple regular RA code is copied several times to produce a series of identical master patterns, and adjacent patterns are connected into a coupling chain by unfolding of edges. The difference is that the construction of the SCRA code only performs spatial coupling operation on the repeated part in the RA code, and the accumulated part is kept as it is, so that the SCRA code not only can keep the inherent advantage of low encoding complexity of the RA code, but also has the threshold saturation characteristic of the spatial coupling code.
The parallel concatenated code is an effective coding scheme of a long code with excellent performance and acceptable decoding complexity by utilizing the short code, and has good error correction capability for burst errors and random errors. However, the existing parallel concatenated structure of the parallel concatenated code needs an interleaver to implement a randomized structure, and the interleaver is introduced to make interleaving and deinterleaving operations necessary during encoding and decoding, which may increase the encoding and decoding delay.
[ summary of the invention ]
The invention aims to provide a design method of a parallel cascade space coupling RA code, which is used for reducing coding and decoding time delay when the space coupling RA code is subjected to parallel cascade.
The invention adopts the following technical scheme: a design method of a parallel cascade space coupling RA code comprises the following steps:
selecting a (J, K) rule RA code protogram; j is the degree of a message bit node in the RA code protograph, K is the degree of a check bit node in the RA code protograph, and J and K are positive integers;
copying the RA code protographs to obtain L RA code protographs, and sequentially arranging the L RA code protographs, wherein the positions after arrangement are 1,2, … and L respectively;
connecting message bit nodes and check bit nodes in L RA code protographs to form a (J, K, L) SCRA code coupling chain;
adding check bit nodes and parity bit nodes in a (J, K, L) SCRA code coupling chain to generate a prototype graph of the parallel concatenated SCRA code;
and generating the parallel concatenated SCRA code according to the protograph of the parallel concatenated SCRA code.
Further, the RA code protograph comprises message bit nodes, check bit nodes, parity bit nodes and edges connecting the message bit nodes, the check bit nodes and the parity bit nodes;
the degree of a parity bit node in the RA code protograph is 2;
the RA code prototype graph comprises J ' check bit nodes, K ' message bit nodes and J ' parity bit nodes;
a represents the greatest common divisor of J and K, J = aJ ', K = aK', gcd (J ', K') =1.
Further, the specific method for connecting the message bit nodes and the check bit nodes in the L RA code protographs includes:
respectively connecting J edges corresponding to message bit nodes in the RA code prototype graph with the position of i to each check bit node of the RA code prototype graph with the position of { i, i +1, …, i + a-1}, wherein i belongs to [1,L ];
the degree of the parity bit node in each RA code protogram is 2.
Further, a specific method for adding check bit nodes and parity bit nodes in the (J, K, L) SCRA code coupling chain is as follows:
adding RA code protographs with the positions of L +1, L +2, … and L + a-1 respectively; the RA code protographs with the positions of L +1, L +2, … and L + a-1 respectively have no message bit nodes, and the number of check bit nodes and parity bit nodes in each added RA code protograph is equal to the number of check bit nodes and parity bit nodes in the (J, K) regular RA code protograph;
connecting the newly added check bit node to the message bit node of the (J, K, L) SCRA code coupling chain in a connection mode:
respectively connecting J edges corresponding to message bit nodes in the RA code prototype graph with the position of i to each check bit node of the RA code prototype graph with the position of { i, i +1, …, i + a-1}, wherein i belongs to [1,L ];
the newly added parity bit node is connected to the newly added parity bit node, and the degree of the newly added parity bit node is 2.
Further, the generating of the parallel concatenated SCRA code according to the prototype graph of the parallel concatenated SCRA code specifically includes:
copying message bit nodes, check bit nodes and parity bit nodes in the original graph of the parallel cascade SCRA code and connecting edges among the message bit nodes, the check bit nodes and the parity bit nodes, and obtaining MK ' message bit nodes, MJ ' check bit nodes and MJ ' parity bit nodes in each position of the original graph of the parallel cascade SCRA code;
randomly replacing edges between MK 'message bit nodes and MJ' check bit nodes at each position;
expanding edges connecting the check bit nodes and the parity bit nodes according to an accumulation mode;
and obtaining the parallel cascade SCRA codes.
The invention has the beneficial effects that: according to the method, the check bit node and the parity bit node are added in the (J, K, L) SCRA code coupling chain, the original graph of the parallel cascade SCRA code is generated through a simple and convenient connection method, the original graph has a randomized structure, an interleaver does not need to be additionally introduced, and interleaving and de-interleaving operation is not needed during coding and decoding, so that the decoding time delay is reduced.
[ description of the drawings ]
Fig. 1 is a diagram illustrating a process of constructing a coupling chain of SCRA codes in an embodiment of the present application;
fig. 2 is a schematic diagram of a prototype graph of parallel concatenated spatial-coupled RA codes constructed according to an embodiment of the present application.
[ detailed description ] embodiments
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The embodiment of the application provides a method for designing a parallel cascade space coupling RA code, which comprises the following steps:
s1, selecting a (J, K) rule RA code prototype graph; the RA code protograph includes message bit nodes, check bit nodes, parity bit nodes, and edges connecting therebetween.
J is the degree of a message bit node in the RA code protograph, K is the degree of a check bit node in the RA code protograph, and J and K are positive integers; the degree of the parity bit node in the RA code protogram is 2.
The RA code prototype graph includes J ' check bit nodes, K ' message bit nodes, and J ' parity bit nodes, where a denotes the greatest common divisor of J and K, and a = gcd (J, K), J = aJ ', K = aK ', gcd (J ', K ') =1.
And S2, copying the RA code protographs to obtain L RA code protographs, sequentially arranging the L RA code protographs at 1,2, … and L respectively, and connecting message bit nodes and check bit nodes in the L RA code protographs to form a (J, K, L) SCRA coupling chain.
During specific connection, according to the edge expansion rule, the specific principle is as follows:
j edges of message bit nodes of the RA code protograph with the position of i are respectively connected to each check bit node, i e [1,L ], of the RA code protograph with the position of { i, i +1, …, i + a-1}, and the degree of parity bit nodes in each RA code protograph is 2.
S3, adding check bit nodes and parity bit nodes in the (J, K, L) SCRA code coupling chain to generate an original model graph of the parallel cascade SCRA code; wherein the number of added check bit nodes and parity bit nodes is equal.
In order to complete the connection process, as shown in fig. 1, RA code protographs with positions L +1, L +2, …, and L + a-1 are added behind the RA protograph with position L; the RA code protographs with the positions of L +1, L +2, … and L + a-1 respectively have no message bit nodes, and the number of check bit nodes and parity bit nodes in each added RA code protograph is equal to the number of check bit nodes and parity bit nodes in the (J, K) regular RA code protograph.
Connecting the newly added check bit node to the message bit node of the (J, K, L) SCRA code coupling chain in the manner shown in fig. 2, wherein the specific method is as follows:
respectively connecting J edges corresponding to message bit nodes in the RA code protograph with the position of i to each check bit node of the protograph with the position of { i, i +1, …, i + a-1}, wherein i belongs to [1,L ]; the newly added parity bit node is connected to the newly added parity bit node, and the degree of the newly added parity bit node is 2.
And S4, generating the parallel cascade SCRA code according to the prototype graph of the parallel cascade SCRA code.
In this embodiment, the parallel concatenated SCRA codes are obtained by copying and replacing an original pattern of the parallel concatenated SCRA codes, which specifically includes:
copying message bit nodes, check bit nodes and parity bit nodes in the protograph of the parallel concatenated SCRA code and connecting edges between the message bit nodes and the check bit nodes, and obtaining MK ' message bit nodes, MJ ' check bit nodes and MJ ' parity bit nodes in each position in the protograph of the parallel concatenated SCRA code.
And randomly replacing edges between MK 'message bit nodes and MJ' check bit nodes at each position in the original graph of the parallel cascade SCRA codes, namely randomly replacing the M edges connecting the message bit nodes and the check bit nodes with the copied M edges connecting the message bit nodes and the check bit nodes.
And expanding edges connecting the check bit nodes and the parity bit nodes in an accumulation mode to obtain the parallel cascade SCRA code.
After the parallel concatenated SCRA code is obtained, in order to compare it with other coding methods, the code rate needs to be calculated, which is adopted in the embodiment of the present application
To calculate its code rate.
Design example 1:
in this embodiment, a parallel concatenated SCRA code with J =3 and k =3 needs to be designed, and the design method of the parallel concatenated SCRA code includes the following steps:
step S10: a (3,3) regular RA code protograph is selected that contains message bit nodes, check bit nodes and parity bit nodes and edges connecting them.
In this embodiment, J =3,k =3. Calculating a = gcd (3,3) =3, where J '=1 satisfying the condition and K' =1 satisfying the condition at this time, that is, the RA code prototype graph includes 1 check bit node, 1 message bit node and 1 parity bit node.
Step S20: and copying the RA code protographs to obtain 30 RA code protographs.
The RA code protographs are arranged in sequence and marked as 30, namely the positions of the RA code protographs are 1,2, … and 30 respectively. And connecting the message bit nodes and the check bit nodes in the 30 RA code protographs according to an edge expansion rule to form (3,3,30) an SCRA coupling chain.
For example: for the message bit node in the RA code protograph with position 1, 3 edges thereof are connected to the check bit node in the RA protograph with number {1,2,3 }. The connections between the check bit nodes and the parity bit nodes remain in a conventional accumulation fashion.
And step 30: the check bit nodes and parity bit nodes with the same number and the same degree are added in the (3,3,30) SCRA coupling chain, in this embodiment, 2 check bit nodes and 2 parity bit nodes are added, and the added 2 check bit nodes are respectively connected with the last message bit node in the (3,3,30) SCRA coupling chain.
Step S40: and copying and replacing the original pattern of the parallel cascade SCRA code to obtain the parallel cascade SCRA code.
The method specifically comprises the following steps: the message bit nodes, check bit nodes and parity bit nodes in the protograph of the parallel concatenated SCRA code are all copied to obtain M parts of message bit nodes, check bit nodes and parity bit nodes, and since the number of M has no influence on test data and final results, M can be any numerical value, in this embodiment, M is set to be 2 for convenience of calculation.
And randomly replacing the same type of 2 edges connecting the message bit nodes and the check bit nodes, wherein in the embodiment of the application, the same type of 2 edges refer to 2 edges connected to the message bit nodes with the same position. Edges connecting the check bit nodes and the parity bit nodes are spread out in a conventional accumulation manner. Thus, the parallel concatenated SCRA code in this embodiment is obtained.
Design example 2:
in this example, L =50, and the other conditions are the same as those in design example 1.
Design example 3:
in this example, L =100, and other conditions are the same as those in design example 1.
For design embodiments 1 to 3, the code rate of the parallel concatenated SCRA code obtained in step S40 is calculated, and the specific calculation method is as follows:
for L =30:
/>
for L =50:
for L =100:
in order to further verify the effect of the invention, a density evolution algorithm is adopted to carry out threshold simulation analysis, and the decoding threshold of the designed parallel cascade SCRA code under the BEC channel and the difference value between the decoding threshold and the capacity limit are given according to different coupling lengths. As shown in table 1, the first column indicates the degree distribution of the SCRA code, the second column indicates the value of the coupling length L, the third column indicates the code rate, the fourth column indicates the capacity limit, the fifth column indicates the decoding threshold, and the last column indicates the difference.
As can be seen from table 1, when the decoding threshold and the capacity limit are compared, the difference is small, and the decoding threshold is close to the capacity limit, which indicates that the probability of the error bit is low, i.e., the decoding performance is good and the reliability is high in the embodiment of the present application.
Table 1 threshold results at different coupling lengths for a distribution of J =3, k =3
Design example 4
In this embodiment, a parallel concatenated SCRA code with J =3,k =6 is designed, and the method for designing the parallel concatenated SCRA code includes the following steps:
step S110: a (3,6) regular RA code protograph is selected that contains message bit nodes, check bit nodes and parity bit nodes and edges connecting them.
In this example, J =3,k =6. Calculating a = gcd (3,6) =3, where J '=1 satisfying the condition and K' =2 satisfying the condition, that is, the RA code prototype graph includes 1 check bit node, 2 message bit nodes and 1 parity bit node.
Step S120: and copying the RA code protographs to obtain 30 RA code protographs.
The RA code protographs are arranged in sequence and marked as 30, namely the positions of the RA code protographs are 1,2, … and 30 respectively. And connecting the message bit nodes and the check bit nodes in the 30 RA code protographs according to an edge expansion rule to form (3,6,30) an SCRA coupling chain.
Step S130: the same number and same degree of check bit nodes and parity bit nodes are added in the (3,6,30) SCRA coupling chain, which in this embodiment is 1 check bit node and 1 parity bit node.
Step S140: and copying and replacing the original pattern of the parallel cascade SCRA code to obtain the parallel cascade SCRA code. The method specifically comprises the following steps: all message bit nodes, check bit nodes and parity bit nodes in the original graph are copied to M parts (the value of M in the embodiment is the same as the value-taking principle in the design embodiment 1), M edges of the same type connecting the message bit nodes and the check bit nodes are randomly replaced, and the edges connecting the check bit nodes and the parity bit nodes are expanded according to a conventional accumulation mode. Thus, the parallel concatenated SCRA code in this embodiment is obtained.
Design example 5:
in this example, L =50, and the other conditions are the same as those in design example 4.
Design example 6:
in this example, L =50, and the other conditions are the same as those in design example 4.
For the design embodiment 4-6, the code rate of the parallel concatenated SCRA code obtained in step four is calculated, and the specific calculation method is as follows:
for L =30:
for L =50:
for L =100:
in order to further verify the effect of the invention, a density evolution algorithm is adopted to perform threshold simulation analysis, and for different coupling lengths, the decoding threshold of the designed parallel concatenated SCRA code under the BEC channel and the difference between the decoding threshold and the capacity limit are given, as shown in table 2, wherein a first column represents the degree distribution of the SCRA code, a second column represents the value of the coupling length L, a third column represents the code rate, a fourth column represents the capacity limit, a fifth column represents the decoding threshold, and a last column represents the difference.
As can be seen from table 2, when the decoding threshold and the capacity limit are compared, the difference is small, and the decoding threshold is close to the capacity limit, which indicates that the error bit probability in the embodiment of the present application is low, i.e., the decoding performance is good, and the reliability is high
Table 2 threshold results at different coupling lengths for a distribution of J =3, k =6 degrees
As can be seen from the above design examples 1 to 6, if the decoding threshold values in the embodiments of the present application are all close to the capacity limit, it is indicated that the decoding method of the present application has excellent performance, is an SCRA code having a "threshold saturation" characteristic, and the decoding performance is very close to the capacity limit.
Claims (2)
1. A design method of a parallel cascade space coupling RA code is characterized by comprising the following steps:
selecting a (J, K) rule RA code protogram; wherein J is the degree of a message bit node in the RA code protograph, K is the degree of a check bit node in the RA code protograph, and J and K are positive integers;
copying the RA code protographs to obtain L RA code protographs, and sequentially arranging the L RA code protographs, wherein the positions after arrangement are 1,2, … and L respectively;
connecting message bit nodes and check bit nodes in L RA code protographs to form a (J, K, L) SCRA code coupling chain; the specific method for connecting the message bit nodes and the check bit nodes in the L RA code protographs comprises the following steps:
respectively connecting J edges corresponding to message bit nodes in the RA code prototype graph with the position of i to each check bit node of the RA code prototype graph with the position of { i, i +1, …, i + a-1}, wherein i belongs to [1,L ];
the degree of a parity bit node in each RA code prototype graph is 2;
adding check bit nodes and parity bit nodes in the (J, K, L) SCRA code coupling chain to generate an original model graph of the parallel cascade SCRA code; the specific method for adding check bit nodes and parity bit nodes in the (J, K, L) SCRA code coupling chain is as follows:
adding RA code protographs with the positions of L +1, L +2, … and L + a-1 respectively; wherein, there is no message bit node in the RA code protographs with the positions of L +1, L +2, …, and L + a-1, respectively, and the number of check bit nodes and parity bit nodes in each added RA code protograph is equal to the number of check bit nodes and parity bit nodes in the (J, K) regular RA code protograph;
connecting the newly added check bit node to the message bit node of the (J, K, L) SCRA code coupling chain in a connection mode:
respectively connecting J edges corresponding to message bit nodes in the RA code prototype graph with the position of i to each check bit node of the RA code prototype graph with the position of { i, i +1, …, i + a-1}, wherein i belongs to [1,L ];
the newly added parity bit node is connected to the newly added check bit node, and the degree of the newly added parity bit node is 2;
generating parallel cascade SCRA codes according to the original pattern of the parallel cascade SCRA codes; the method specifically comprises the following steps:
copying message bit nodes, check bit nodes and parity bit nodes in the original graph of the parallel cascade SCRA code and edges connecting the message bit nodes, the check bit nodes and the parity bit nodes, and obtaining MK ' message bit nodes, MJ ' check bit nodes and MJ ' parity bit nodes in each position of the original graph of the parallel cascade SCRA code;
randomly replacing edges between MK 'message bit nodes and MJ' check bit nodes at each position;
expanding edges connecting the check bit nodes and the parity bit nodes according to an accumulation mode;
and obtaining the parallel cascade SCRA code.
2. The method of claim 1, wherein the RA code protograph comprises message bit nodes, check bit nodes, parity bit nodes, and edges connecting therebetween;
the degree of a parity bit node in the RA code prototype graph is 2;
the RA code protograph comprises J ' check bit nodes, K ' message bit nodes and J ' parity bit nodes;
a represents the greatest common divisor of J and K, J = aJ ', K = aK', gcd (J ', K') =1.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101442315A (en) * | 2007-11-19 | 2009-05-27 | 电子科技大学 | Method and apparatus for encoding multiple LDPC code based on weighting totalizer |
| CN101521511A (en) * | 2008-02-28 | 2009-09-02 | 重庆无线绿洲通信技术有限公司 | Method for constructing and coding multiple irregular RA code |
| CN108777605A (en) * | 2018-05-24 | 2018-11-09 | 西安电子科技大学 | Multichain SC-LDPC coding methods suitable for bulk nanometer materials |
| CN110061746A (en) * | 2019-04-26 | 2019-07-26 | 华侨大学 | A kind of coupling process of the Space Coupling LDPC code of code rate free of losses |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100918763B1 (en) * | 2003-11-14 | 2009-09-24 | 삼성전자주식회사 | Interleaving apparatus and method in a channel coder using a parallel concatenated low density parity check code |
| KR101009785B1 (en) * | 2003-12-10 | 2011-01-19 | 삼성전자주식회사 | Apparatus and method for coding/decoding irregular repeat accumulate code |
| US20050160351A1 (en) * | 2003-12-26 | 2005-07-21 | Ko Young J. | Method of forming parity check matrix for parallel concatenated LDPC code |
| KR100946884B1 (en) * | 2005-07-15 | 2010-03-09 | 삼성전자주식회사 | Channel interleaving/de-interleaving apparatus in a communication system using a low density parity check code and control method thereof |
| US8689083B2 (en) * | 2010-06-15 | 2014-04-01 | California Institute Of Technology | Rate-compatible protograph LDPC codes |
-
2019
- 2019-12-10 CN CN201911256871.9A patent/CN110880939B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101442315A (en) * | 2007-11-19 | 2009-05-27 | 电子科技大学 | Method and apparatus for encoding multiple LDPC code based on weighting totalizer |
| CN101521511A (en) * | 2008-02-28 | 2009-09-02 | 重庆无线绿洲通信技术有限公司 | Method for constructing and coding multiple irregular RA code |
| CN108777605A (en) * | 2018-05-24 | 2018-11-09 | 西安电子科技大学 | Multichain SC-LDPC coding methods suitable for bulk nanometer materials |
| CN110061746A (en) * | 2019-04-26 | 2019-07-26 | 华侨大学 | A kind of coupling process of the Space Coupling LDPC code of code rate free of losses |
Non-Patent Citations (1)
| Title |
|---|
| 原模图LDPC码的一种联合优化算法;方毅等;《应用科学学报》;20111130(第06期);全文 * |
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