CN110880521A - Image pickup panel and method for manufacturing same - Google Patents
Image pickup panel and method for manufacturing same Download PDFInfo
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- CN110880521A CN110880521A CN201910834972.3A CN201910834972A CN110880521A CN 110880521 A CN110880521 A CN 110880521A CN 201910834972 A CN201910834972 A CN 201910834972A CN 110880521 A CN110880521 A CN 110880521A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
Abstract
The imaging panel includes a photoelectric conversion element (12) arranged on a substrate (101). The photoelectric conversion element (12) comprises: a cathode electrode (14 a); a first semiconductor layer (151) of a first conductivity type in contact with the cathode electrode (14 a); a second semiconductor layer (153) which is bonded to the first semiconductor layer (151) and has a second conductivity type different from the first conductivity type; and an anode electrode (14b) in contact with the second semiconductor layer (153). The extinction coefficient of the second semiconductor layer (153) is larger as it approaches the anode electrode (14 b).
Description
Technical Field
The invention disclosed below relates to an imaging panel and a method for manufacturing the same.
Background
An X-ray imaging apparatus is known which images an X-ray image through an imaging panel having a plurality of pixel units. In such an X-ray imaging apparatus, for example, a PIN (p-intrinsic-n) photodiode is used as a photoelectric conversion element, and the PIN photodiode converts an irradiated X-ray into an electric charge. The converted charges are read by operating a Thin Film Transistor (hereinafter also referred to as "TFT") provided in the pixel portion, and an X-ray image is obtained based on the read charges. Japanese patent laid-open publication No. 2014-078651 discloses such a photoelectric conversion element array unit.
Disclosure of Invention
Technical problem to be solved by the invention
However, in the semiconductor layer in contact with the anode electrode of the photoelectric conversion element, the extinction coefficient in the semiconductor layer is optically small, and the quantum efficiency is improved, but the smaller the extinction coefficient, the smaller the doping concentration in the semiconductor layer is, and the leakage current of the photoelectric conversion element easily flows to the interface with the anode electrode.
Means for solving the problems
An imaging panel completed in view of the above problems includes: a substrate; and a photoelectric conversion element disposed on the substrate, the photoelectric conversion element including: a cathode electrode; a first semiconductor layer of a first conductivity type in contact with the cathode electrode; a second semiconductor layer which is bonded to the first semiconductor layer and has a second conductivity type different from the first conductivity type; and an anode electrode in contact with the second semiconductor layer, the extinction coefficient in the second semiconductor layer being larger closer to the anode electrode.
Effects of the invention
According to the above configuration, the leakage current of the photoelectric conversion element can be suppressed and the quantum efficiency can be improved.
Drawings
Fig. 1 is a schematic diagram showing an X-ray imaging apparatus according to an embodiment.
Fig. 2 is a schematic view showing a schematic configuration of the imaging panel shown in fig. 1.
Fig. 3 is an enlarged plan view of one pixel portion of the imaging panel shown in fig. 2.
Fig. 4A is a cross-sectional view of the pixel shown in fig. 3 taken along line a-a.
Fig. 4B is an enlarged schematic view of a part of the p-type amorphous semiconductor layer shown in fig. 4A.
Fig. 5A is a sectional view showing a process of manufacturing the imaging panel shown in fig. 4A, that is, a process of forming a gate insulating film and a TFT on a substrate.
Fig. 5B is a sectional view showing a step of forming a first insulating film covering the gate insulating film and the TFT shown in fig. 5A.
Fig. 5C is a sectional view showing a step of forming an opening of the first insulating film shown in fig. 5B.
Fig. 5D is a sectional view showing a step of forming a second insulating film on the first insulating film in fig. 5C.
Fig. 5E is a sectional view showing a step of forming an opening of the second insulating film in fig. 5D and forming a contact hole CH 1.
Fig. 5F is a sectional view showing a step of forming a lower electrode on the second insulating film in fig. 5E.
Fig. 5G is a cross-sectional view showing a step of forming an n-type amorphous semiconductor layer, an intrinsic amorphous semiconductor layer, and a p-type amorphous semiconductor layer covering the lower electrode shown in fig. 5F, and forming an upper electrode on the p-type amorphous semiconductor layer.
Fig. 5H is a sectional view showing a step of patterning the n-type amorphous semiconductor layer, the intrinsic amorphous semiconductor layer, and the p-type amorphous semiconductor layer shown in fig. 5G to form a photoelectric conversion layer.
Fig. 5I is a sectional view showing a step of forming a third insulating film covering the photoelectric conversion layer in fig. 5H.
Fig. 5J is a sectional view showing a step of forming an opening of the third insulating film in fig. 5H.
Fig. 5K is a sectional view showing a step of forming a fourth insulating film covering the third insulating film and the photoelectric conversion layer in fig. 5J.
Fig. 5L is a sectional view showing a step of forming an opening of the fourth insulating film in fig. 5K and forming a contact hole CH 2.
Fig. 5M is a sectional view showing a step of forming a metal film as a bias wiring covering the surfaces of the fourth insulating film and the photoelectric conversion layer in fig. 5L.
Fig. 5N is a cross-sectional view showing a step of patterning a metal film as the bias wiring in fig. 5M to form the bias wiring.
Fig. 5O is a sectional view showing a step of forming a transparent insulating film covering the bias wiring and the surface of the photoelectric conversion layer in fig. 5N.
Fig. 5P is a sectional view showing a step of patterning the transparent conductive film in fig. 5O to form a conductive film connected to the bias wiring and the upper electrode.
Fig. 5Q is a sectional view showing a step of forming a fifth insulating film covering the surface of the conductive film in fig. 5P.
Fig. 5R is a sectional view showing a step of forming a sixth insulating film covering the fifth insulating film in fig. 5Q.
Detailed Description
Hereinafter, embodiments of the invention will be described in detail with reference to the drawings. The same or corresponding portions in the drawings are denoted by the same reference numerals, and description thereof will not be repeated.
(constitution)
Fig. 1 is a schematic diagram showing an X-ray imaging apparatus according to the present embodiment. The X-ray imaging apparatus 100 includes an imaging panel 1 and a control unit 2. The control section 2 includes a gate control section 2A and a signal readout section 2B. The X-ray source 3 irradiates the subject S with X-rays, and the X-rays transmitted through the subject S are converted into fluorescent light (hereinafter, referred to as scintillation light) by the scintillator 1A disposed on the imaging panel 1. The X-ray imaging apparatus 100 captures an X-ray image by imaging the scintillation light using the imaging panel 1 and the control unit 2.
Fig. 2 is a schematic diagram showing a schematic configuration of the imaging panel 1. As shown in fig. 2, a plurality of source wirings 10 and a plurality of gate wirings 11 intersecting the plurality of source wirings 10 are formed on the imaging panel 1. The gate line 11 is connected to the gate control section 2A, and the source line 10 is connected to the signal readout section 2B.
The imaging panel 1 includes TFTs 13 connected to the source lines 10 and the gate lines 11 at positions where the source lines 10 and the gate lines 11 intersect. A photodiode 12 is provided in a region (hereinafter referred to as a pixel) surrounded by the source line 10 and the gate line 11. In the pixel, scintillation light obtained by converting X-rays having passed through the object S is converted into electric charges corresponding to the amount of light by the photodiode 12.
Each gate line 11 in the imaging panel 1 is sequentially switched to a selected state in the gate control unit 2A, and the TFT13 connected to the gate line 11 in the selected state is turned on. When the TFT13 is turned on, a signal corresponding to the charge converted by the photodiode 12 is output to the signal readout section 2B via the source wiring 10.
Fig. 3 is an enlarged plan view of one pixel portion of the imaging panel 1 shown in fig. 2. As shown in fig. 3, a photodiode 12 and a TFT13 are provided in a pixel surrounded by a gate wiring 11 and a source wiring 10. The photodiode 12 includes a lower electrode (cathode) 14a and an upper electrode (anode) 14b as a pair of electrodes, and a photoelectric conversion layer 15. The upper electrode 14b is provided above the photoelectric conversion layer 15, that is, on the side irradiated with X-rays from the X-ray source 3 (see fig. 1). The TFT13 has a gate electrode 13a integrated with the gate wiring 11, a semiconductor active layer 13b, and a source electrode 13c and a drain electrode 13d integrated with the source wiring 10. The bias wiring 16 is arranged to overlap the gate wiring 11 and the source wiring 10 in a plan view. The bias wiring 16 supplies a bias to the photodiode 12. The pixel is provided with a connection hole CH1 for connecting the drain electrode 13d and the lower electrode 14a.
Here, fig. 4A shows a cross-sectional view of the pixel shown in fig. 3 along line a-a. Hereinafter, the positive Z-axis direction shown in fig. 4A, i.e., the side on which the X-ray source is provided, may be referred to as the upper side, and the negative Z-axis direction may be referred to as the lower side.
As shown in fig. 4A, each element in the pixel is disposed on one surface of the substrate 101. The substrate 101 is an insulating substrate, and is made of, for example, a glass substrate.
A gate electrode 13a and a gate insulating film 102 are formed on the substrate 101, the gate electrode being integrated with the gate wiring 11 (see fig. 3).
The gate electrode 13a and the gate line 11 are made of a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), molybdenum nitride (MoN), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), an alloy thereof, or a nitride thereof. In the present embodiment, the gate electrode 13a and the gate line 11 may have a laminated structure in which a metal film made of molybdenum nitride and a metal film made of aluminum are sequentially laminated. The film thickness is, for example, about 100nm for a metal film made of molybdenum nitride and about 300nm for a metal film made of aluminum.
The gate insulating film 102 covers the gate electrode 13a. For the gate insulating film 102, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x > y), silicon nitride oxide (SiNxOy) (x > y), or the like can be used, for example. In this embodiment, the gate insulating film 102 is formed by sequentially laminating a silicon oxide (SiOx) and silicon nitride (SiNx) in this order, and the silicon oxide (SiOx) has a film thickness of about 50nm and the silicon nitride (SiNx) has a film thickness of about 400 nm.
A semiconductor active layer 13b, and a source electrode 13c and a drain electrode 13d connected to the semiconductor active layer 13b are formed on the gate electrode 13a with a gate insulating film 102 interposed therebetween.
The semiconductor active layer 13b is formed in contact with the gate insulating film 102. The semiconductor active layer 13b is made of an oxide semiconductor. Oxide semiconductor may also be used, for example, InGaO3(ZnO)5Magnesium zinc oxide (MgxZn)1-xO), cadmium zinc oxide (CdxZn)1-xO), cadmium oxide (CdO), or an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) at a predetermined ratio. In the present embodiment, the semiconductor active layer 13b is formed of an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) at predetermined ratios, and the film thickness thereof is, for example, about 70 nm.
The source electrode 13c and the drain electrode 13d are disposed in contact with a part of the semiconductor active layer 13b on the gate insulating film 102. The source electrode 13c is integrated with the source wiring 10 (see fig. 3). The drain electrode 13d is connected to the lower electrode 14a through a contact hole CH 1.
The source electrode 13c and the drain electrode 13d are formed on the same layer, and are made of, for example, a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), an alloy thereof, or a nitride thereof. As the material of the source electrode 13c and the drain electrode 13d, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), indium tin oxide containing silicon oxide (ITSO), and indium oxide (In) may be used2O3) Tin oxide (SnO)2) Materials having light-transmitting properties such as zinc oxide (ZnO) and titanium nitride, and combinations thereof as appropriate.
The source electrode 13c and the drain electrode 13d may be formed by stacking a plurality of metal films, for example. Specifically, the source electrode 13c and the drain electrode 13d have a laminated structure in which a metal film made of molybdenum nitride (MoN), a metal film made of aluminum (Al), and a metal film made of molybdenum nitride (MoN) are laminated in this order. The film thickness of the metal film made of molybdenum nitride (MoN) in the lower layer is about 100nm, the film thickness of the metal film made of aluminum (Al) is about 500nm, and the film thickness of the metal film made of molybdenum nitride (MoN) in the upper layer is about 50 nm.
The first insulating film 103 is provided to cover the source electrode 13c and the drain electrode 13d. The first insulating film 103 may be made of silicon oxide (SiO)2) Or a single-layer structure made of silicon nitride (SiN), or silicon nitride (SiN) and silicon oxide (SiO) may be stacked in this order2) The laminated structure of (1).
A second insulating film 104 is formed on the first insulating film 103. A contact hole CH1 is formed in the drain electrode 13d. The contact hole CH1 penetrates the second insulating film 104 and the first insulating film 103. The second insulating film 104 is made of, for example, an organic transparent resin such as an acrylic resin or a silicone resin, and has a film thickness of, for example, about 2.5 μm.
A lower electrode 14a is formed on the second insulating film 104. The lower electrode 14a is connected to the drain electrode 13d through a contact hole CH 1. The lower electrode 14a is formed of a metal film containing, for example, molybdenum nitride (MoN), and the film thickness thereof is, for example, about 200 nm.
A photoelectric conversion layer 15 is formed on the lower electrode 14a. The photoelectric conversion layer 15 is configured by sequentially stacking an n-type amorphous semiconductor layer 151, an intrinsic amorphous semiconductor layer 152, and a p-type amorphous semiconductor layer 153. In this example, the length of the photoelectric conversion layer 15 in the X-axis direction is shorter than the length of the lower electrode 14a in the X-axis direction.
The n-type amorphous semiconductor layer 151 is made of amorphous silicon doped with n-type impurities (phosphorus or the like). The thickness of the n-type amorphous semiconductor layer 151 is, for example, about 30 nm.
The intrinsic amorphous semiconductor layer 152 is made of intrinsic amorphous silicon. The intrinsic amorphous semiconductor layer 152 is formed in contact with the n-type amorphous semiconductor layer 151. The thickness of the intrinsic amorphous semiconductor layer 152 is, for example, about 1000 nm.
The p-type amorphous semiconductor layer 153 is made of amorphous silicon doped with p-type impurities (boron and the like). The p-type amorphous semiconductor layer 153 is formed in contact with the intrinsic amorphous semiconductor layer 152. The film thickness of the p-type amorphous semiconductor layer 153 is, for example, about 5 nm.
Here, fig. 4B is an enlarged cross-sectional view of a part of the photoelectric conversion layer 15 in fig. 4A. As shown in fig. 4B, the p-type amorphous semiconductor layer 153 in the photoelectric conversion layer 15 is composed of two layers of a first p-type amorphous semiconductor layer 1531 and a second p-type amorphous semiconductor layer 1532.
The doping concentration of the first p-type amorphous semiconductor layer 1531 is less than that of the second p-type amorphous semiconductor layer 1532. The greater the doping concentration, the greater the extinction coefficient. That is, in this embodiment, the extinction coefficient of the p-type amorphous semiconductor layer 153 is smaller on the first p-type amorphous semiconductor layer 1531 side than on the second p-type amorphous semiconductor layer 1532 side. Therefore, free electrons are more easily suppressed in the second p-type amorphous semiconductor layer 1532 than in the first p-type amorphous semiconductor layer 1531, and a leakage current is hard to flow between the upper electrode 14b and the second p-type amorphous semiconductor layer 1532. In addition, the transmittance of light to the p-type amorphous semiconductor layer 153 is improved, and quantum efficiency is improved. In addition, since the second p-type amorphous semiconductor layer 1532 has a higher doping concentration than the first p-type amorphous semiconductor layer 1531, the resistivity is lower than that of the first p-type amorphous semiconductor layer 1531.
In this embodiment, the extinction coefficient of the p-type amorphous semiconductor layer 153 is preferably 0.040 or more and 0.250 or less, and the difference in extinction coefficient between the first p-type amorphous semiconductor layer 1531 and the second p-type amorphous semiconductor layer 1532 is preferably 0.005 or more. In this example, for example, the doping concentrations of the first p-type amorphous semiconductor layer 1531 and the second p-type amorphous semiconductor layer 1532 are adjusted so that the extinction coefficient of the first p-type amorphous semiconductor layer 1531 is 0.075 and the extinction coefficient of the second p-type amorphous semiconductor layer 1532 is 0.150.
Returning to fig. 4A, the upper electrode 14b is provided on the p-type amorphous semiconductor layer 15. In this example, the width of the upper electrode 14b in the X-axis direction is smaller than the width of the p-type amorphous semiconductor layer 15. In this example, the upper electrode 14b is formed of a transparent conductive film made of, for example, ITO (Indium Tin Oxide), and the film thickness of the upper electrode 14b is about 70 μm.
A third insulating film 105 is provided on the second insulating film 104 to cover the surface of the photodiode 12. The third insulating film 105 has an opening 105a at a position overlapping with the upper electrode 14b in a plan view. The third insulating film 105 is, for example, an inorganic insulating film made of silicon nitride (SiN), and has a film thickness of, for example, about 300 nm.
A fourth insulating film 106 is provided on the third insulating film 105. The fourth insulating film 106 has an opening 106a at a position overlapping with the opening 105a of the third insulating film 105 in a plan view. Contact hole CH2 is formed by openings 105a and 106 a.
The fourth insulating film 106 is formed of an organic insulating film made of an organic transparent resin such as an acrylic resin or a siloxane resin. The thickness of the fourth insulating film 106 is, for example, about 2.5 μm.
The bias wiring 16 and the conductive film 17 covering the bias wiring 16 are formed on the fourth insulating film 106.
The bias wiring 16 has a laminated structure in which a metal film 161 made of molybdenum nitride (MoN), a metal film 162 made of aluminum (Al), and a metal film 163 made of titanium (Ti) are laminated in this order. The film thicknesses of molybdenum nitride (MoN), aluminum (Al) and titanium (Ti) are, for example, about 100nm, 300nm and 50nm, respectively.
The conductive film 17 is connected to the bias wiring 16 and is connected to the upper electrode 14b through a contact hole CH 2. In this example, the conductive film 17 is made of, for example, a transparent conductive film made of ITO (Indium Tin Oxide), and the film thickness of the conductive film 17 is about 70 μm.
The bias wiring 16 is connected to the control unit 2 (see fig. 1). The bias wiring 16 applies a bias input from the control unit 2 to the upper electrode 14b via the conductive film 17.
A fifth insulating film 107 is provided on the fourth insulating film 106 so as to cover the conductive film 17. The fifth insulating film 107 is composed of, for example, an inorganic insulating film made of silicon nitride (SiN). The thickness of the fifth insulating film 107 is, for example, about 200 nm.
A sixth insulating film 108 is provided on the fifth insulating film 107. In this example, the sixth insulating film 108 is formed of an organic insulating film made of an organic transparent resin such as an acrylic resin or a siloxane resin. The thickness of the sixth insulating film 108 is, for example, about 2.0 μm.
(method of manufacturing Camera Panel 1)
Next, a method for manufacturing the imaging panel 1 will be described. Fig. 5A to 5R are sectional views (section a-a in fig. 3) in the manufacturing process of the imaging panel 1.
First, on the substrate 101, the gate insulating film 102 and the TFT13 are formed using a known method (see fig. 5A), and the first insulating film 103 made of silicon nitride (SiN) is formed using, for example, a plasma CVD method so as to cover the TFT13 (see fig. 5B).
Next, heat treatment at about 350 ℃ is applied to the entire surface of the substrate 101, and photolithography and wet etching are performed to pattern the first insulating film 103 and form an opening 103a in the drain electrode 13d (see fig. 5C).
Next, a second insulating film 104 made of an acrylic resin or a siloxane resin is formed over the first insulating film 103 by, for example, a slit coating method (see fig. 5D).
Then, the opening 104a of the second insulating film 104 is formed at a position overlapping with the opening 103a in a plan view using photolithography. Thereby, contact hole CH1 (see fig. 5E) including openings 103a and 104a is formed.
Next, on the second insulating film 104, a metal film made of molybdenum nitride (MoN) is formed using, for example, a sputtering method, and then the metal film is patterned by photolithography and wet etching. Thereby, the lower electrode 14a connected to the drain electrode 13d via the contact hole CH1 is formed on the second insulating film 104 (see fig. 5F).
Next, an n-type amorphous semiconductor layer 151, an intrinsic amorphous semiconductor layer 152, and a p-type amorphous semiconductor layer 153 having a first p-type amorphous semiconductor layer 1531 and a second p-type amorphous semiconductor layer 1532 are sequentially formed using, for example, a plasma CVD method to cover the second insulating film 104 and the lower electrode 14a. After that, a transparent conductive film made of ITO is formed on the p-type amorphous semiconductor layer 153 using, for example, a sputtering method, and then the transparent conductive film is patterned by photolithography and dry etching. Thereby, the upper electrode 14b is formed.
In this embodiment, when the p-type amorphous semiconductor layer 153 is formed, the distance between electrodes in the reaction chamber of the plasma CVD apparatus is controlled to be about 20nm, and the reaction is performedThe pressure and temperature distribution in the chamber were controlled to about 200pa and 200 ℃, and the high frequency (RF) power was controlled to about 100W. In this example, as the reaction gas, SiH is used4Gas, B2H6Gas and H2A gas. The proportion of these reactive gases is adjusted according to the extinction coefficient.
Extinction coefficient dependent on B2H6Gas flow ratio of gas to total flow of reactant gases, and B2H6The larger the gas flow rate ratio of the gas, the larger the extinction coefficient of the p-type amorphous semiconductor layer. In this embodiment, the flow rates of the reaction gases used for forming the first p-type amorphous semiconductor layer 1531 are adjusted as follows: SiH4Gas about 240sccm, B2H6Gas (by dilution H2Gas, B2H6Concentration of 1%) is about 100sccm, H2The gas content is about 860 sccm. The flow rates of the reaction gases used for forming the second p-type amorphous semiconductor layer 1532 are adjusted as follows: SiH4Gas about 240sccm, B2H6Gas (by dilution H2Gas, B2H61%) of about 500sccm, H2The gas is about 460 sccm.
Thus, by making B2H6The flow ratio of the total flow rate of the reaction gas at the time of film formation of the gas and the p-type amorphous semiconductor layer 153 is larger in the second p-type amorphous semiconductor layer 1532 than in the first p-type amorphous semiconductor layer 1531, and the p-type amorphous semiconductor layer 153 in which the first p-type amorphous semiconductor layer 1531 and the second p-type amorphous semiconductor layer 1532 having different extinction coefficients and doping concentrations are stacked is formed.
Next, the n-type amorphous semiconductor layer 151, the intrinsic amorphous semiconductor layer 152, and the p-type amorphous semiconductor layer 153 are patterned by photolithography and dry etching, whereby the photoelectric conversion layer 15 is formed and the photodiode 12 is formed (see fig. 5H).
Next, a third insulating film 105 made of silicon nitride (SiN) is formed by, for example, a plasma CVD method so as to cover the surface of the photodiode 12 (see fig. 5I), and then the third insulating film 105 is patterned by photolithography and wet etching (see fig. 5J). Thus, the opening 105a of the third insulating film 105 is formed at a position overlapping the p-type amorphous semiconductor layer 153 in plan view.
Next, a fourth insulating film 106 made of an acrylic resin or a siloxane resin is formed over the third insulating film 105 by, for example, a slit coating method (see fig. 5K).
Next, the opening 106a of the fourth insulating film 106 is formed at a position overlapping with the opening 105a of the third insulating film 105 in a plan view by photolithography. Thereby, contact hole CH2 (see fig. 5L) including openings 105a and 106a is formed.
Next, a metal film 160 in which molybdenum nitride (MoN), aluminum (Al), and titanium (Ti) are sequentially stacked is formed using, for example, a sputtering method so as to cover the fourth insulating film 106 and the contact hole CH2 (see fig. 5M). Then, photolithography and wet etching are performed to pattern the metal film 160 (see fig. 5N). Thereby, the bias wiring 16 is formed at a position overlapping with the photoelectric conversion layer 15 in a plan view.
Next, the transparent conductive film 170 made of ITO is formed so as to cover the fourth insulating film 106, the contact hole CH2, and the bias wiring 16 (see fig. 5O) using, for example, a sputtering method, and the transparent conductive film 170 is patterned by a photolithography method and a dry etching method (see fig. 5P). Thereby, the conductive film 17 connected to the bias wiring 16 and connected to the upper electrode 14b through the contact hole CH2 is formed.
Next, a fifth insulating film 107 made of silicon nitride (SiN) is formed using, for example, a plasma CVD method so as to cover the fourth insulating film 106 and the conductive film 17 (see fig. 5Q). Next, a sixth insulating film 108 made of an acrylic resin or a siloxane resin is formed on the fifth insulating film 107 by, for example, a slit coating method (see fig. 5R). Thus, the pixel portion of the imaging panel 1 of the present embodiment is formed.
The above is the imaging panel 1 and the manufacturing method thereof in the present embodiment. As described above, the p-type amorphous semiconductor layer 153 in the photoelectric conversion layer 15 of the imaging panel 1 according to the present embodiment has a structure in which the first p-type amorphous semiconductor layer 1531 and the second p-type amorphous semiconductor layer 1532 having different extinction coefficients and doping concentrations are stacked. Specifically, the extinction coefficient and the doping concentration of the first p-type amorphous semiconductor layer 1531 side are smaller than those of the second p-type amorphous semiconductor layer 1532. That is, the second p-type amorphous semiconductor layer 1532 in contact with the upper electrode 14b has an extinction coefficient and a doping concentration greater than the first p-type amorphous semiconductor layer 1531 on the intrinsic amorphous semiconductor layer 152 side. Therefore, a leakage current hardly flows between the upper electrode 14b and the second p-type amorphous semiconductor layer 1532. In addition, since the extinction coefficient of the first p-type amorphous semiconductor layer 1531 side is smaller than that of the second p-type amorphous semiconductor layer 1532, light is easily transmitted from the second p-type amorphous semiconductor layer 1532 to the first p-type amorphous semiconductor layer 1531, and quantum efficiency can be improved.
(operation of X-ray imaging apparatus 100)
Here, the operation of the X-ray imaging apparatus 100 shown in fig. 1 will be described. First, X-rays are irradiated from the X-ray source 3. At this time, the control unit 2 applies a predetermined voltage (bias) to the bias wiring 16 (see fig. 3 and the like). The X-rays irradiated from the X-ray source 3 pass through the subject S and are incident on the scintillator 1A. The X-rays incident on the scintillator 1A are converted into fluorescent light (scintillation light), and the scintillation light is incident on the imaging panel 1. When scintillation light is incident on the photodiode 12 provided in each pixel of the imaging panel 1, the photodiode 12 is charged in accordance with the amount of scintillation light. When the TFT13 (see fig. 3 and the like) is turned on by a gate voltage (positive voltage) output from the gate control unit 2A via the gate line 11, a signal corresponding to the electric charge converted by the photodiode 12 is read out to the signal reading unit 2B via the source line 10 (see fig. 2 and the like). Then, the control unit 2 generates an X-ray image corresponding to the read signal.
Although the embodiments of the imaging panel and the method of manufacturing the same have been described above, the above embodiments are merely examples. Therefore, the imaging panel and the method for manufacturing the same are not limited to the above embodiment, and the above embodiment can be appropriately modified and implemented without departing from the scope of the invention. A modified example of the imaging panel will be described below.
(1) The above embodiment has described an example in which the p-type amorphous semiconductor layer 153 has a structure in which two first p-type amorphous semiconductor layers 1531 and second p-type amorphous semiconductor layers 1532 having different extinction coefficients and doping concentrations are stacked, but the structure of the p-type amorphous semiconductor layer 153 is not limited to this. For example, the p-type amorphous semiconductor layer 153 may be formed of three p-type amorphous semiconductor layers having different extinction coefficients and different doping concentrations so that the extinction coefficient and the doping concentration become larger toward the upper electrode 14b side, or may be formed of four p-type amorphous semiconductor layers having different extinction coefficients and different doping concentrations. In short, the p-type amorphous semiconductor layer 153 may be configured to have a higher extinction coefficient and a higher doping concentration as the upper electrode 14b is closer.
Specifically, for example, when the p-type amorphous semiconductor layer 153 has a structure in which three p-type amorphous semiconductor layers are stacked, the extinction coefficients of the lowermost p-type amorphous semiconductor layer in contact with the intrinsic amorphous semiconductor layer 152, the intermediate p-type amorphous semiconductor layer, and the uppermost p-type amorphous semiconductor layer in contact with the upper electrode 14b are preferably about 0.075, 0.100, and 0.150, respectively. In this case, the ratio of the gas flow rates of the reaction gases when the three p-type amorphous semiconductor layers are to be formed can be adjusted as follows. In the case of forming the p-type amorphous semiconductor layer as the lowermost layer, SiH is added4Adjusting the gas to about 240sccm, and adjusting the gas concentration to B2H6Gas (by dilution H2Gas, B2H6Concentration of 1%) is adjusted to about 100sccm, H is added2The gas content is about 860 sccm. In the case of forming the p-type amorphous semiconductor layer of the intermediate layer, SiH is added4Adjusting the gas to about 240sccm, and adjusting the gas concentration to B2H6Gas (by dilution H2Gas, B2H6Concentration of 1%) is adjusted to about 300sccm, H is added2The gas is about 660 sccm. In addition, in the case of forming the uppermost p-type amorphous semiconductor layer, SiH is added4Adjusting the gas to about 240sccm, and adjusting the gas concentration to B2H6Gas (by dilution H2Gas, B2H6Concentration of 1%) is adjusted to about 500sccm, H is added2The gas is about 460 sccm.
(2) In the above embodiment, the example in which the PIN photodiode in which the intrinsic amorphous semiconductor layer 152 is provided between the p-type amorphous semiconductor layer 153 and the n-type amorphous semiconductor layer 151 is used as the photoelectric conversion layer 15 has been described, but the structure of the photoelectric conversion layer 15 is not limited thereto. The photoelectric conversion layer 15 may be a pn junction semiconductor of a planar structure type in which an n-type semiconductor formed by diffusing a dopant such as phosphorus into a part of a p-type silicon substrate is embedded in the p-type silicon substrate, and a p-type semiconductor formed by diffusing a dopant such as boron into a part of the n-type silicon substrate is embedded in the n-type silicon substrate, for example. In the case where the n-type semiconductor is embedded in the photoelectric conversion layer of the p-type silicon substrate, the n-type semiconductor is in contact with the upper electrode 14b and is formed so that the extinction coefficient and the doping concentration of the n-type semiconductor become larger as they approach the upper electrode 14b. In the case where the p-type semiconductor is embedded in the photoelectric conversion layer of the n-type silicon substrate, the p-type semiconductor is in contact with the upper electrode 14b, and is formed so that the extinction coefficient and the doping concentration of the p-type semiconductor become larger as they approach the upper electrode 14b.
The imaging panel and the method for manufacturing the same can be described as follows.
The imaging panel according to the first configuration includes: a substrate; and a photoelectric conversion element disposed on the substrate, the photoelectric conversion element including: a cathode electrode; a first semiconductor layer of a first conductivity type in contact with the cathode electrode; a second semiconductor layer which is bonded to the first semiconductor layer and has a second conductivity type different from the first conductivity type; and an anode electrode in contact with the second semiconductor layer, the extinction coefficient in the second semiconductor layer being larger as it approaches the anode electrode (first configuration).
According to the first configuration, the photoelectric conversion element provided on the substrate includes: the semiconductor device includes an anode electrode, a second semiconductor layer connected to the anode electrode, a first semiconductor layer bonded to the second semiconductor layer, and a cathode electrode connected to the first semiconductor layer. Since the extinction coefficient in the second semiconductor layer is larger closer to the anode electrode side, the leakage current of the photoelectric conversion element is less likely to flow between the second semiconductor layer and the anode electrode. In addition, in the second semiconductor layer, since the extinction coefficient is smaller as it is closer to the cathode electrode side, light is easily transmitted to the second semiconductor layer, and quantum efficiency can be improved.
In the first configuration, the second semiconductor layer may be formed of a plurality of layers having different extinction coefficients, and the extinction coefficient of a layer closer to the anode electrode among the plurality of layers may be larger (second configuration).
According to the second configuration, the second semiconductor layer is composed of a plurality of layers having different extinction coefficients, and the extinction coefficient of the layer closer to the cathode electrode is larger. Therefore, a leakage current is difficult to flow between the second semiconductor layer and the cathode electrode, and light is easily transmitted to the second semiconductor layer, and quantum efficiency can be improved.
In the first or second configuration, the photoelectric conversion element may further include an intrinsic semiconductor layer between the first semiconductor layer and the second semiconductor layer (third configuration).
According to the third configuration, since the intrinsic semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer, the depletion layer becomes large in a reverse bias state as compared with the case where the intrinsic semiconductor layer is not provided, and the moving speed of carriers can be improved.
In the second or third configuration, a difference in extinction coefficient between a first layer closest to the anode electrode and a second layer farthest from the anode electrode among the plurality of layers may be 0.005 or more (a fourth configuration).
In the second semiconductor layer having any of the first to fourth configurations, the concentration of the dopant added to the second semiconductor layer may be higher as the second semiconductor layer is closer to the anode electrode (fifth configuration).
According to the fifth configuration, since the concentration of the dopant added to the second semiconductor layer is higher as the anode electrode is closer, the depletion layer expands and the leak current is hard to flow to the interface between the anode electrode and the second semiconductor layer, as compared with the case where the concentration of the dopant in the second semiconductor layer is uniform.
The method for manufacturing the camera panel comprises the following steps: forming a cathode electrode on a substrate; forming a first semiconductor layer of a first conductivity type in contact with the cathode electrode; forming a second semiconductor layer having a second conductivity type different from the first conductivity type, the second semiconductor layer being bonded to the first semiconductor layer; and forming an anode electrode in contact with the second semiconductor layer, wherein the extinction coefficient of the second semiconductor layer is larger as the second semiconductor layer is closer to the anode electrode (first manufacturing method).
According to the first manufacturing method, a cathode electrode, a first semiconductor layer having a first conductivity type on a substrate and in contact with the cathode electrode, a second semiconductor layer bonded to the first semiconductor layer and having a second conductivity type different from the first conductivity type, and an anode electrode in contact with the second semiconductor layer are formed on the substrate. The extinction coefficient in the second semiconductor layer is larger as it is closer to the anode electrode. Therefore, a leakage current hardly flows between the second semiconductor layer and the anode electrode. In addition, since the extinction coefficient is smaller closer to the cathode electrode side in the second semiconductor layer, light is easily transmitted to the second semiconductor layer, and the quantum efficiency is improved.
In the step of forming the second semiconductor layer in the first manufacturing method, the second semiconductor layer may be formed such that the concentration of the dopant added to the second semiconductor layer increases as the anode electrode approaches the second semiconductor layer (second manufacturing method).
According to the second manufacturing method, since the concentration of the dopant added to the second semiconductor layer is larger as closer to the anode electrode in the second semiconductor layer, the depletion layer spreads and the leak current is difficult to flow to the interface between the second semiconductor layer and the anode electrode, compared with the case where the concentration of the dopant in the second semiconductor layer is uniform.
Description of the reference numerals
1.. an image pickup panel, 1a.. a scintillator, 2.. a control section, 2a.. a gate control section, 2b.. a signal readout section, 3.. an X-ray source, 10.. a source wiring, 11.. a gate wiring, 12.. a photodiode, 13.. a Thin Film Transistor (TFT), 13a.. a gate electrode, 13b.. a semiconductor active layer, 13c.. a source electrode, 13d.. a drain electrode, 14a.. a lower electrode, 14b.. an upper electrode, 15.. a photoelectric conversion layer, 16.. a bias wiring, 17.. a conductive film, 100.. an X-ray image pickup device, 101.. a substrate, 102.. a gate insulating film, 103.. a first insulating film, 104.. a second insulating film, 105.. a third insulating film, 106, 107. a fourth insulating film, 107.. a 108.. sixth insulating film, 151.. n-type amorphous semiconductor layer, 152.. intrinsic amorphous semiconductor layer, 153.. p-type amorphous semiconductor layer, 1531.. first p-type amorphous semiconductor layer, 1532.. second p-type amorphous semiconductor layer.
Claims (7)
1. A camera panel, comprising:
a substrate; and
a photoelectric conversion element disposed on the substrate,
the photoelectric conversion element includes:
a cathode electrode;
a first semiconductor layer of a first conductivity type in contact with the cathode electrode;
a second semiconductor layer which is bonded to the first semiconductor layer and has a second conductivity type different from the first conductivity type; and
an anode electrode in contact with the second semiconductor layer,
the extinction coefficient in the second semiconductor layer is larger closer to the anode electrode.
2. The camera panel of claim 1,
the second semiconductor layer is composed of a plurality of layers having different extinction coefficients,
among the plurality of layers, the closer to the anode electrode, the larger the extinction coefficient of the layer.
3. The image pickup panel according to claim 1 or 2, wherein the photoelectric conversion element further includes an intrinsic semiconductor layer between the first semiconductor layer and the second semiconductor layer.
4. The image pickup panel according to claim 2, wherein a difference in extinction coefficient between a first layer closest to the anode electrode and a second layer farthest from the anode electrode among the plurality of layers is 0.005 or more.
5. The imaging panel according to claim 1 or 2, wherein a concentration of the dopant added to the second semiconductor layer is higher in the second semiconductor layer as closer to the anode electrode.
6. A method for manufacturing an imaging panel, comprising:
forming a cathode electrode on a substrate;
forming a first semiconductor layer of a first conductivity type in contact with the cathode electrode;
forming a second semiconductor layer having a second conductivity type different from the first conductivity type, the second semiconductor layer being bonded to the first semiconductor layer; and
a step of forming an anode electrode in contact with the second semiconductor layer,
the extinction coefficient in the second semiconductor layer is larger closer to the anode electrode.
7. The manufacturing method according to claim 6, wherein in the step of forming the second semiconductor layer, the second semiconductor layer is formed such that a concentration of a dopant added to the second semiconductor layer increases as the anode electrode approaches.
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