CN110880353B

CN110880353B - Electronic device and operation method thereof

Info

Publication number: CN110880353B
Application number: CN201811037728.6A
Authority: CN
Inventors: 柳弼相; 何文乔
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2018-09-06
Filing date: 2018-09-06
Publication date: 2022-06-07
Anticipated expiration: 2038-09-06
Also published as: CN110880353A

Abstract

The invention provides an electronic device and an operation method thereof, which are used for correctly triggering the initialization operation of the electronic device. The electronic device includes a plurality of latches and a power-on reset generator. The plurality of latches are coupled to the plurality of memory cells and configured to monitor memory data of the plurality of memory cells. The power-on reset generator is coupled to the latches and configured to generate a power-on reset pulse to reset the electronic device according to data corruption of the at least one memory cell. Data corruption is detected during an initialization operation of the electronic device based on stored data of the plurality of storage cells and corresponding hardware encoded data.

Description

Electronic device and operation method thereof

Technical Field

The present invention relates to an electronic device and an operating method thereof, and more particularly, to an electronic device for correctly triggering an initialization operation of the electronic device and an operating method thereof.

Background

In modern times, memory devices are widely used in many electronic devices to store data. Among the different Memory cell types, Content Addressable Memory (CAM) is preferred for applications that require relatively high speed searching for data. However, one of the key issues that leads to corruption of the memory cell device's stored data is sudden power down or a power drop that is too low. Therefore, it is desirable to detect a Power-down and trigger a Power-On Reset (POR) signal to properly Reset the electronic device, thereby recovering corrupted data and improving the reliability of the electronic device.

Disclosure of Invention

The invention provides an electronic device for correctly triggering initialization operation of the electronic device and an operation method thereof.

The invention provides an electronic device, which is provided with a plurality of storage units and comprises a plurality of latches and a power-on reset generator. The plurality of latches are coupled to the plurality of memory cells and configured to monitor memory data of the plurality of memory cells. The power-on reset generator is coupled to the latches and configured to generate a power-on reset pulse to reset the electronic device according to data corruption of the at least one memory cell. Data corruption is detected during an initialization operation of the electronic device based on stored data of the plurality of storage cells and corresponding hardware encoded data.

The invention provides an operation method, which is suitable for an electronic device with a plurality of storage units and comprises the following steps: monitoring stored data sensed from a plurality of memory cells; detecting data corruption during an initialization operation of the electronic device based on the stored data and corresponding hardware encoded data; a power-on reset pulse is generated to reset the electronic device based on the detected data corruption.

Based on the above, in some embodiments of the present invention, when the stored data is corrupted due to a power drop, a POR pulse is generated to reset the electronic device in order to recover the corrupted stored data. In this way, corrupted stored data may be recovered and the reliability of the electronic device improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a circuit diagram of an electronic device according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a latch circuit of an electronic device according to an embodiment of the invention.

Fig. 3 is a circuit diagram of a hardware encoding circuit of the electronic device according to an embodiment of the invention.

Fig. 4 is a flowchart illustrating an initialization operation of the electronic device according to an embodiment of the invention.

Fig. 5A-5C are schematic diagrams illustrating power droop, according to an embodiment of the present invention.

Fig. 6 is a flow chart illustrating a method of operation in accordance with an embodiment of the present invention.

Description of reference numerals:

100: an electronic device;

110: an array of memory cells;

120: a latch circuit;

130: a power-on reset circuit;

131. 133, 135, 137: an exclusive or circuit;

140: a hardware encoding circuit;

340: a hardware encoding circuit;

3401. 3403, 3405: a group of transistors;

01h, 02h, 03 h: an address;

l, L1, L2, L3: a latch;

d1, D2, D3, Dn: storing the data;

d1 ', D2', D3 ', Dn': hardware encoded data;

and (3) POR: a power-on reset pulse;

POR1, POR 2: a power-on reset pulse;

vcc: a working supply voltage;

GND: a ground voltage;

m, M10-M17, M20-M27, M30-M37, P1, P2, N1, N2: a transistor;

inv1, Inv 2: an inverter;

A. b, C: a node;

vpor: powering on to reset the threshold voltage;

vpwd: a power-off voltage;

vrst: resetting the trigger voltage;

FuseCAM: a content addressable memory cell fusing signal;

s410, S420, S430, S440, S450, S610, S620, S630: and (5) carrying out the following steps.

Detailed Description

It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having" and its associated terms herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Unless limited otherwise, the terms "connected," "coupled," and "mounted," and variations thereof herein are used broadly and encompass direct connections, indirect connections, couplings, and mountings.

Referring to fig. 1, the electronic device 100 may include a memory cell array 110, a latch circuit 120, a power-on reset generator 130, and a hardware encoding circuit 140. The memory cell array 110 may include a plurality of memory cells configured to store memory data. Each memory cell is associated with one of the memory cell addresses, for example,

address

01h, 02h or 03 h. In some embodiments, the Memory cells may be Content Addressable Memory Cells (CAM), although the invention is not limited to any particular type of Memory cell.

The latch circuit 120 may include a plurality of latches L1, L2, and L3, wherein each of the latches L1, L2, and L3 corresponds to one of the memory cells, and each of the latches L1, L2, and L3 is configured to monitor the stored data of the corresponding memory cell. For example, the latch L1 corresponds to a memory cell at the address 01h and is configured to monitor the storage data D1 stored in the corresponding memory cell; the latch L2 corresponds to the memory cell at the address 02h, and is configured to monitor the storage data D2 stored in the corresponding memory cell; the latch L3 corresponds to the memory cell at the address 03h, and is configured to monitor the storage data D3 stored in the corresponding memory cell. The latch circuit 120 may provide the stored data D1-D3 monitored by the latch L1-L3 to the power-on reset generation circuit 130. The latches L1, L2, and L3 may be Flip-flops (F/F), but the present invention is not limited to any particular type of latch.

In some embodiments, the electronic device 100 may further include a sense amplifier (not shown) configured to sense data stored in the memory cell. The sense amplifiers may output the sensed memory data to the latches L1-L3 of the latch circuit 120 so that the latch circuit 120 may monitor the memory data stored in the memory cells of the memory cell array 110.

The hardware-encoded circuitry 140 is configured to provide the hardware-encoded data D1 '-D3' of the corresponding stored data D1-D3, monitored by the latches L1-L3, respectively, to the power-up reset generation circuitry 130. For example, the hardware-encoded circuit 140 may provide hardware-encoded data D1 ' corresponding to the stored data D1, hardware-encoded data D2 ' corresponding to the stored data D2, and hardware-encoded data D3 ' corresponding to the stored data D3 to the upper electrical reset generation circuit 130.

The power-on reset generation circuit 130 may include a plurality of logic circuits, which may be Exclusive-OR (XOR)

circuits

131 and 137 in some embodiments. Each of the EXCLUSIVE-OR circuits 131-137 may receive the stored data monitored by the latch L1-L3 and the corresponding hardware encoded data (hardwired code data) provided by the hardware encoding circuit 140. As shown in FIG. 1, XOR circuit 135 receives the stored data D1 monitored by latch L1 and the corresponding hard coded data D1 ', and performs an XOR operation on the received stored data D1 and hard coded data D1' to output the result. When the stored data D1 is identical to the corresponding hardware encoded data D1', the XOR circuit 135 outputs a low logic value (e.g., logic value 0). Conversely, when the stored data D1 is different from the corresponding hardware encoded data D1', the XOR circuit 135 outputs a high logic value (e.g., logic value 1). Similarly, the XOR circuit 133 is configured to XOR the received stored data D2 with the hardware-encoded data D2' to output the result. The operation of the other exclusive-or

circuits

131, 137 may be analogized and will not be described in detail. In this manner, when the stored data stored in any memory cell is corrupted (e.g., when the stored data is different from the corresponding hardware-encoded data), the

xor circuit

131 and 137 will output a high logic value to generate a Power-On Reset pulse (POR pulse) to Reset the electronic device 100.

It should be noted that the logic circuit of the power-on reset generator 130 is not limited to the exclusive or circuit. Other logic circuits are also within the scope of the present invention as long as they can detect a difference between the stored data and the corresponding hardware encoded data.

In some embodiments, the power-on reset generator 130 is configured to generate a power-on reset pulse POR (or a power-on reset signal) according to the storage data corruption in the at least one memory cell. The power-on reset generator 130 may generate a power-on reset pulse POR when at least one of the

xor circuits

131 and 137 outputs a predefined logic value. For example, if at least one of the

XOR circuits

131 and 137 outputs a high logic value (e.g., logic value 1) to indicate that the stored data is different from the corresponding hardware-encoded data, a power-on reset pulse is generated. Therefore, when the voltage drop causes the memory data stored in the memory cell to be damaged, the power-on reset pulse POR is generated to trigger the initialization procedure for initializing the electronic device 100 regardless of the voltage drop. This way corrupted data can be recovered.

Referring to fig. 2, fig. 2 shows a detailed structure of the latch L of the latch circuit 120 according to an embodiment of the present invention. The latch L includes a transistor M, an inverter Inv1 and an inverter Inv2, wherein a control terminal of the transistor M is coupled to a drain terminal of the transistor M, so that the operating power voltage Vcc at the drain terminal of the transistor M is lowered by the threshold voltage Vth of the transistor M. In other words, the source terminal (or node C) of the transistor M is at Vcc-Vth. The inverter Inv1 and the inverter Inv2 operate at a voltage (Vcc-Vth) where the operating power supply voltage Vcc lowers the threshold voltage Vth. Thus, data corruption due to power down may be detected earlier and the electronic device 100 may be reset to avoid data corruption within the memory cells.

The inverter Inv1 is coupled back-to-back (back-to-back) to the inverter Inv 2. In other words, the output terminal of the inverter Inv1 is the input terminal of the inverter Inv2, and the output terminal of the inverter Inv2 is the input terminal of the inverter Inv 1. The inverter Inv1 may include a P-type transistor P1 and an N-type transistor N1; the inverter Inv2 may include a P-type transistor P2 and an N-type transistor N2. The control terminals of the transistors P1 and N1 are coupled to node B, which is electrically connected to the drain terminals of the transistors P2 and N2. The control terminals of the transistors P2 and N2 are coupled to node A, which is electrically connected to the drain terminals of the transistors P1 and N1. The transistors N1 and N2 are coupled to the ground voltage GND. The invention is not limited to any particular type of transistors P1, P2, N1, N2.

Referring to fig. 3, fig. 3 shows the structure of the hardware encoding circuit 340. The hardware-encoded circuit 340 may include a plurality of transistors M10-M17, M20-M27, M30-M37 configured in

transistor groups

3401, 3403, 3405 to provide hardware-encoded data to the power-on reset generator 130. The transistor group 3401 includes transistors M10-M17; the transistor group 3403 includes transistors M20-M27; the transistor group 3405 includes transistors M30-M37. As shown in FIG. 3, transistor cluster 3401 provides hardware encoded data to a memory cell corresponding to address 0h 1; transistor cluster 3403 providing hard coded data to the memory cell corresponding to address 0h 2; transistor cluster 3405 provides hard coded data to the memory cell corresponding to address 0h 3. It should be noted that the structure of the hardware encoding circuit 340 is not limited to the structure illustrated in fig. 3. Any configuration of the hardware encoding circuit is within the scope of the present invention as long as the hardware encoding circuit 340 can provide the hardware encoded data corresponding to the memory cell to the power-on reset generator 130.

Fig. 4 shows a flow chart during an initialization operation (or power-up operation) in accordance with an embodiment of the invention. Referring to FIGS. 1 and 4, after power up (step S410), the stored data of the memory cells are monitored by the latches L1-L3 (step S420). Next, in step S430, data corruption in at least one storage unit is detected according to the storage data and the corresponding hardware encoded data. The stored data is monitored by latches L1-L3, and corresponding hardware encoded data is provided by hardware encoding circuitry 140. In step S440, the power-on reset generator 130 may generate a power-on reset pulse according to the detected data corruption. In step S450, the initialization operation (or power-on operation) is completed. Accordingly, the electronic apparatus 100 may detect data corruption due to power down in the memory cell and output a power-on reset pulse in an initialization procedure to reset the electronic apparatus 100.

Fig. 5A-5C illustrate examples of power droop, according to some embodiments of the present invention. The arrows in fig. 5A to 5C indicate the power drop that occurs at the operating supply voltage Vcc. Referring to fig. 5A, when the operating power supply voltage Vcc reaches the power-on reset threshold voltage Vpor, a first power-on reset pulse POR1 is generated. When the operating power voltage Vcc is lowered to the reset trigger voltage Vrst, the stored data stored in at least one memory cell is corrupted (relative to the valid state, the content addressable memory cell fusing signal FuseCAM is in the invalid state). In this case, the electronic device 100 will detect the data corruption in at least one memory cell (e.g., the electronic device 100 shown in fig. 1), and will generate a second power-on reset pulse POR2 to reset the electronic device 100, thereby recovering the corrupted data.

Referring to fig. 5B, when the operating power supply voltage Vcc is lowered to a voltage level higher than the power-down voltage Vpwd, the stored data stored in the memory cell will not be damaged and the second power-on reset pulse POR2 will not be generated. It should be noted that the power down voltage Vpwd is higher than the reset trigger voltage Vrst and lower than the power up reset threshold voltage Vpor.

Referring to fig. 5C, when the operating power voltage Vcc is lowered to a voltage level higher than the reset trigger voltage Vrst and lower than the power-down voltage Vpwd, the stored data stored in at least one of the memory cells is damaged (relative to the valid state, the content addressable memory cell fusing signal FuseCAM is in the invalid state). In this case, even if the operating power supply voltage Vcc does not drop to the reset trigger voltage Vrst, the storage data stored in the memory cell may be damaged. The electronic device will detect the data corruption in at least one memory cell (e.g., the electronic device 100 shown in fig. 1), and will generate a second power-on reset pulse POR2 to reset the electronic device 100, thereby recovering the corrupted data.

From fig. 5A to fig. 5C, when the storage data stored in at least one of the memory cells is damaged, the electronic device 100 generates a second power-on reset pulse POR 2. Therefore, no matter how much the power is dropped, once the stored data is corrupted, a power-on reset pulse POR2 will be generated to reset the electronic device 100.

Referring to FIG. 6, a flow diagram of a method of operation is shown, in accordance with an embodiment of the present invention. In step S610, the storage data sensed from the plurality of storage cells is monitored. For example, the

latches

131 and 137 shown in FIG. 1 can be used to monitor the storage data sensed from the memory cells. In step S620, data corruption is detected during an initialization operation of the electronic device 100, based on the stored data and the corresponding hardware encoded data. For example, the power-on reset generator 130 shown in fig. 1 can detect data corruption in each memory cell according to the stored data and the corresponding hardware encoded data. In step S630, a power-on reset pulse is generated to reset the electronic apparatus 100 according to the detected data corruption. If data corruption is detected in at least one of the memory cells, a power-on reset pulse is generated to reset the electronic device 100 to avoid data loss.

In summary, in some embodiments of the present invention, an electronic device and an operating method thereof are provided to correctly trigger an initialization operation of the electronic device and prevent data loss of a memory cell in the electronic device. Data corruption is detected in at least one of the memory cells based on the stored data monitored by the plurality of latches and corresponding hardware encoded data provided by the hardware encoding circuitry. A power-on reset pulse is generated to reset the electronic device to recover corrupted stored data based on the detected data corruption in the at least one memory cell. The latches may be operated with a voltage that lowers the threshold voltage by a predetermined operating power supply voltage to early detect data corruption and early reset the electronic device. Since data corruption is detected based on the stored data stored in the memory cell, data corruption can be detected regardless of power down.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. An electronic device having a plurality of memory cells, comprising:

a plurality of latches coupled to the plurality of memory cells and configured to monitor storage data of the plurality of memory cells, respectively;

a power-on reset generator coupled to the plurality of latches and configured to generate a power-on reset pulse to reset the electronic device according to data corruption of at least one memory cell; and

a hardware encoding circuit coupled to the power-on reset generator and configured to provide hardware encoded data to the power-on reset generator,

wherein the data corruption is detected during an initialization operation of the electronic device based on the stored data of the plurality of storage cells and the corresponding hardware encoded data,

wherein the plurality of latches operate at a voltage that drops the threshold voltage from the preset operating supply voltage.

2. The electronic device of claim 1, wherein the plurality of memory cells are content addressable memory cells.

3. The electronic device of claim 1, wherein each of the plurality of latches comprises:

a first inverter;

a second inverter coupled to the first inverter; and

a transistor having the threshold voltage, coupled to the first inverter and the second inverter,

wherein an output of the first inverter is coupled to an input of the second inverter and an input of the first inverter is coupled to an output of the second inverter.

4. The electronic device of claim 3, wherein a control terminal of the transistor is coupled to a drain terminal of the transistor.

5. The electronic device of claim 1, wherein

The power-on reset generator comprises a plurality of logic circuits;

each of the plurality of logic circuits is coupled to one of the plurality of latches and the hardware encoding circuit to receive the stored data monitored by the plurality of latches and the corresponding hardware encoded data and configured to perform a logic operation in the received stored data and the received hardware encoded data to output a result; and

generating the power-on reset pulse according to the result of the logical operation.

6. The electronic device of claim 5, wherein the logic circuit is an exclusive OR circuit, the logic operation is an exclusive OR operation, and the power-on reset pulse is generated when the stored data of at least one memory cell is different from the corresponding hardware-encoded data.

7. The electronic device of claim 1, wherein each of the plurality of latches comprises:

a plurality of inverters; and

a transistor having the threshold voltage directly connected between the preset operating power supply voltage and a plurality of first terminals of the plurality of inverters,

wherein the operating voltage of the plurality of inverters is equal to a voltage difference between the preset operating power supply voltage and the threshold voltage.

8. An operating method applicable to an electronic device having a plurality of memory cells, comprising:

monitoring stored data sensed from the plurality of memory cells;

detecting data corruption during an initialization operation of the electronic device based on the stored data and corresponding hardware encoded data; and

generating a power-on reset pulse to reset the electronic device according to the detected data corruption,

wherein the storage data sensed by the plurality of memory cells are respectively monitored by a plurality of latches, and the plurality of latches are operated at a voltage where a preset operation power voltage is lowered by a threshold voltage.

9. The method of operation of claim 8, wherein the step of detecting the data corruption and generating the power-on reset pulse comprises:

performing a logical operation in the stored data and the corresponding hardware encoded data to output a result; and

10. The method of operation of claim 9, wherein the logical operation is an exclusive-or operation and the power-on reset pulse is generated when the stored data is different than the corresponding hardware-encoded data.