CN110875755A

CN110875755A - Chip system, circuit and wireless communication equipment

Info

Publication number: CN110875755A
Application number: CN201910935565.1A
Authority: CN
Inventors: 黄腾飞; 俞泉; 朱松; 范保民; 夏芳; 刘进
Original assignee: Huawei Technologies Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2019-09-29
Filing date: 2019-09-29
Publication date: 2020-03-10
Anticipated expiration: 2039-09-29
Also published as: WO2021057637A1; CN110875755B

Abstract

The embodiment of the application provides a chip system, a circuit and wireless communication equipment, and the chip system comprises: the communication device comprises an antenna port, at least one communication port and at least two channel circuits corresponding to each communication port, wherein a first end of each channel circuit is connected with the corresponding communication port, and a second end of each channel circuit is connected with the antenna port; the third end of each channel circuit is connected with the controller, each channel circuit is used for receiving a control signal sent by the controller, and the control signal is used for controlling the data received or sent by the channel circuit through the antenna port; the control signal is generated by the controller according to the first information and/or the second information of the chip system, and the first information comprises at least one of the following: the hardware version or the country code, and the second information includes at least one of: location information, power, rate, or packet error rate. The universality of the chip system is improved.

Description

Chip system, circuit and wireless communication equipment

Technical Field

The present application relates to the field of circuit technologies, and in particular, to a chip system, a circuit, and a wireless communication device.

Background

In a wireless communication system, in order for a wireless communication device to implement functions of receiving and transmitting data, a transceiver, a chip system and an antenna are generally provided in the wireless communication device, and the chip system is generally provided between the transceiver and the antenna.

A transmit path, a receive path, and a single-pole double-throw switch are typically provided in a system-on-chip. When the wireless communication equipment sends data, the single-pole double-throw switch connects the sending path with the antenna, the transceiver transmits the data to be sent to the chip system, and the data are sent out through the sending path and the antenna in the chip system. When the wireless communication equipment receives data, the single-pole double-throw switch connects the receiving path and the antenna, the antenna receives the data, and sends the received data to the transceiver through the receiving path in the chip system, so that the wireless communication equipment receives the data through the transceiver. However, the circuit structure of the above-described chip system is fixed, resulting in poor versatility of the chip system.

Disclosure of Invention

The application provides a chip system, a circuit and wireless communication equipment, and improves the universality of the chip system.

In a first aspect, an embodiment of the present application provides a chip system, where the chip system includes: the antenna port, at least one communication port, at least two channel circuits that each communication port corresponds to. The first end of each channel circuit is connected with the corresponding communication port, and the second end of each channel circuit is connected with the antenna port; the third end of each channel circuit is connected with the controller, each channel circuit is used for receiving a control signal sent by the controller, and the control signal is used for controlling the channel circuit to receive or send data through the antenna port; the control signal is generated by the controller according to the first information and/or the second information of the chip system, and the first information comprises at least one of the following: the hardware version or the country code, and the second information includes at least one of: location information, power, rate, or packet error rate.

In the chip system shown in the present application, each communication port corresponds to at least two channel circuits, that is, at least two channel circuits are included in one channel (receiving channel or sending channel), so that the chip system can receive data through at least two channel circuits, or the chip system can send data through at least two channel circuits, different channel circuits perform different processing on data, and further, the effect achieved by data transmission is different, in an actual application process, different channel circuits can be controlled to be turned on according to actual requirements (the effect achieved by data transmission is needed), so that the chip system can be applied to a plurality of communication scenes with different transmission effect requirements, and the universality of the chip system is improved.

The pathway includes a corresponding communication port, and circuitry between the communication port and the antenna port. For example, the transmit path includes a transmit port and a circuit between the transmit port and an antenna port. The receive path includes a receive port and a circuit between the receive port and the antenna port.

In a possible implementation mode, the data transmission mode adopted by the chip system is time division multiplexing; and one of all the channel circuits in the chip system receives or transmits data through the antenna port. In the process, the chip system only receives data through one channel circuit or only sends data through one channel circuit at the same time, so that interference among data on different channel circuits is avoided in the data transmission process.

In another possible implementation, the data transmission mode adopted by the chip system is frequency division multiplexing; m channel circuits in all channel circuits in the chip system receive or send data through antenna ports; when M is greater than or equal to 2, any two channel circuits in the M channel circuits do not correspond to the same communication port. In the process, the chip system can receive and/or send data through one or more channel circuits at the same time, so that the data transmission efficiency of the chip system is high.

In one possible embodiment, the channel circuit comprises a switch circuit and a peripheral circuit port, wherein the switch circuit is connected with the controller, and the switch circuit is used for receiving a control signal; the peripheral circuit ports of the different channel circuits corresponding to the same communication port are used for connecting different peripheral circuits.

In the above process, the channel circuit includes a peripheral circuit port, and the peripheral circuit is disposed outside the chip system. In the practical application process, the functions of the chip system can be changed by changing the peripheral circuit, so that the complexity of the circuit in the chip system can be reduced, and the flexibility of the design of the chip system can be improved.

In one possible embodiment, the channel circuit comprises a switch circuit and a peripheral circuit, wherein the switch circuit is connected with the controller, and the switch circuit is used for receiving a control signal; the peripheral circuits in different channel circuits are different.

In the process, the peripheral circuit is arranged inside the chip system, and the peripheral circuit does not need to be arranged outside the chip system, so that the use convenience of the chip system is higher.

In one possible embodiment, the at least two channel circuits include a first channel circuit and a second channel circuit, wherein the first channel circuit includes a first switch circuit, the first switch circuit is connected to the controller, and the first switch circuit is configured to receive a control signal; the second channel circuit comprises a second switch circuit and a second peripheral circuit port, the second switch circuit is connected with the controller, the second switch circuit is used for receiving control signals, and the second peripheral circuit port is used for connecting a peripheral circuit.

In one possible embodiment, the first channel circuit further comprises a first impedance matching circuit, or the first channel circuit further comprises a first peripheral circuit port for connecting the first impedance matching circuit.

In the process, in the process of transmitting the signal in the first channel circuit, the first impedance matching circuit can reduce the attenuation of the signal and improve the performance of signal transmission.

In one possible embodiment, the second channel circuit further comprises a second impedance matching circuit; alternatively, the second peripheral port circuit is also used to connect a second impedance matching circuit.

In the process, in the process of transmitting the signal in the second channel circuit, the second impedance matching circuit can reduce the attenuation of the signal and improve the performance of signal transmission.

In a possible implementation, at least one communication port includes a sending port, and at least two channel circuits are channel circuits corresponding to the sending port; the chip system further comprises a power amplifier, wherein the power amplifier is respectively connected with the transmitting port and the at least two channel circuits.

In the above process, the power amplifier may perform power amplification processing on the signal to be transmitted, so that the power for transmitting the signal is higher.

In a possible implementation, at least one communication port includes a receiving port, and at least two channel circuits are channel circuits corresponding to the receiving port; the chip system further comprises a low noise amplifier, wherein the low noise amplifier is respectively connected with the receiving port and the at least two channel circuits.

In the above process, the low noise amplifier may process the received signal, so that the quality of the processed signal is high.

In a possible implementation, the at least one communication port includes a sending port and a receiving port, and the at least two channel circuits include at least two channel circuits corresponding to the sending port and at least two channel circuits corresponding to the receiving port; the chip system further comprises a power amplifier and a low noise amplifier, wherein the power amplifier is respectively connected with the transmitting port and at least two channel circuits corresponding to the transmitting port. The low noise amplifier is respectively connected with the receiving port and at least two channel circuits corresponding to the receiving port.

In the above process, the system chip includes both the transmission path and the reception path, and thus, data transmission and data reception can be performed by one system chip.

In a possible implementation, the number of the at least one communication port is greater than 1, and the chip system further includes a filter, wherein a first end of the filter is connected to the at least two channel circuits; the second end of the filter is connected to the antenna port.

In the above process, when the at least one communication port includes a receiving port and a transmitting port, simultaneous transmission and reception of data may be achieved by the FEM. When two or more receiving ports are included in at least one communication port, simultaneous reception of two or more data paths can be realized by the FEM. When two or more transmission ports are included in at least one communication port, simultaneous transmission of two or more paths of data can be realized by the FEM. So that the data transmission efficiency is high.

In one possible implementation, the chip system further includes a controller.

In a second aspect, an embodiment of the present application provides a circuit, where the circuit includes a radio frequency chip and the chip system of any one of the first aspect, and the radio frequency chip includes a controller, and the radio frequency chip is configured to send data to the communication port, and/or the radio frequency chip is configured to receive data from the communication port.

In the above process, the path (receiving path or sending path) includes at least two channel circuits, so that the chip system can receive data through the at least two channel circuits, or the chip system can send data through the at least two channel circuits, and communication scenarios applicable to different channel circuits are different, so that the chip system can be applicable to various communication scenarios, and the universality of the chip system is improved, thereby improving the universality of the circuit.

In a third aspect, an embodiment of the present application provides a wireless communication device, including the circuit described in the second aspect.

In the above process, the path (receiving path or transmitting path) includes at least two channel circuits, so that the chip system can receive data through the at least two channel circuits, or the chip system can transmit data through the at least two channel circuits, and communication scenarios applicable to different channel circuits are different, so that the chip system can be applicable to various communication scenarios, and the universality of the chip system is improved, thereby improving the universality of the wireless communication device.

In one possible implementation, the wireless communication device further includes a memory coupled to the controller, the information stored in the memory including the first information. The first information is stored in the memory, so that the controller can conveniently and quickly acquire the obtained first information.

In one possible implementation, the radio frequency chip includes a memory. The memory is arranged inside the radio frequency chip, so that the volume of the wireless communication device can be smaller.

In one possible implementation, the wireless communication device further includes a GPS module, and the GPS module is connected to the controller, wherein the GPS module is configured to acquire the location information of the wireless communication device and send the location information to the controller. Therefore, the controller can conveniently acquire the position information with higher accuracy.

The embodiment of the application provides a chip system, circuit and wireless communication equipment, every communication port corresponds two at least channel circuit, namely, include two at least channel circuit in a route (receiving access or route of sending), make chip system can carry out data reception through two at least channel circuit, or, make chip system can carry out data transmission through two at least channel circuit, different channel circuit is different to the processing that data go on, and then make the effect that data transmission reaches different, in the practical application process, can be according to actual demand (the effect that needs data transmission to reach), control different channel circuit and switch on, make chip system can be applicable to a plurality of communication scenes that have different transmission effect demands, chip system's commonality has been improved.

Drawings

FIG. 1A is a schematic diagram of a system architecture according to an embodiment of the present application;

FIG. 1B is a schematic diagram of another system architecture according to an embodiment of the present application;

fig. 1C is a schematic diagram of another system architecture provided in the embodiment of the present application;

fig. 1D is a schematic diagram of another system architecture provided in the embodiment of the present application;

fig. 2 is a schematic structural diagram of an FEM provided in an embodiment of the present application;

fig. 3 is a schematic structural diagram of a wireless communication device according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of another FEM provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of another FEM provided in an embodiment of the present application;

fig. 6 is a schematic structural diagram of another FEM provided in an embodiment of the present application;

fig. 7 is a schematic diagram illustrating state switching of a switch circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram illustrating state switching of another switching circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another FEM provided in an embodiment of the present application;

fig. 10 is a schematic structural diagram of another FEM provided in an embodiment of the present application;

fig. 11 is a schematic structural diagram of another FEM provided in an embodiment of the present application;

fig. 12 is a schematic structural diagram of another FEM provided in an embodiment of the present application;

fig. 13 is a schematic structural diagram of another FEM provided in an embodiment of the present application;

fig. 14 is a schematic structural diagram of another FEM provided in an embodiment of the present application;

fig. 15 is a schematic structural diagram of another FEM provided in an embodiment of the present application;

fig. 16 is a schematic structural diagram of another FEM provided in the embodiment of the present application;

fig. 17 is a schematic structural diagram of another FEM according to an embodiment of the present application

Fig. 18 is a schematic structural diagram of another FEM provided in an embodiment of the present application;

fig. 19 is a schematic structural diagram of a circuit according to an embodiment of the present application;

fig. 20 is a schematic structural diagram of another wireless communication device according to an embodiment of the present application.

Detailed Description

The chip system shown in the embodiment of the present application may be applied to a wireless communication device, for example, the wireless communication device may be a router, a mobile phone, a computer, a television, a sound box, an in-vehicle device, a wearable device, an industrial device, an artificial intelligence device, an Augmented Reality (AR) device, a Virtual Reality (VR) device, or the like. The wireless communication device may be adapted to a variety of wireless communication networks, such as a wireless fidelity (WiFi) communication network, a bluetooth communication network, a mobile cellular communication network, a Wireless Local Area Network (WLAN) communication network, and so on.

The system-on-chip may be a front-end module (FEM), and for convenience of description, the system-on-chip is hereinafter described as an FEM.

For ease of understanding, the system architecture in which the FEM is located will be described below with reference to fig. 1A to 1D.

Fig. 1A is a schematic diagram of a system architecture according to an embodiment of the present application. Referring to fig. 1A, a transceiver 10, a FEM20, and an antenna 30 are included. The transceiver 10, the FEM20 and the antenna 30 may be provided in a wireless communication device. The transceiver 10 may include a receiver and/or a transmitter, and when the transceiver 10 includes a receiver and a transmitter, the hardware corresponding to the receiver and the hardware corresponding to the transmitter may be independent of each other, or the receiver and the transmitter may be located on the same hardware, and the receiver and the transmitter are logically independent. The transmitter may acquire data generated by the wireless communication device and transmit the data to the FEM20 for transmission via the antenna 30. The antenna 30 may also receive data from other wireless communication devices and pass the data to the FEM20 for transmission to the wireless communication device via the receiver. In the process of data transceiving, the FEM20 is configured to perform processing such as power amplification and filtering on data, so as to improve the transmission performance of the data.

In practical applications, FEM20 may include a Transmit (TX) path and/or a Receive (RX) path. When the wireless communication device in which the FEM20 is located has a data transmission function, a TX path may be included in the FEM 20. When the wireless communication device in which the FEM20 is located has a data reception function, an RX path may be included in the FEM 20. When the wireless communication device in which the FEM20 is located has a data transmission function and a data reception function, the FEM20 may include a TX path and an RX path, or at least two FEMs 20 are provided in the wireless communication device, where at least one FEM20 includes the TX path and at least one FEM20 includes the RX path.

Next, a system configuration in which the FEM20 is located in a plurality of different configurations will be described with reference to fig. 1B to 1D.

Fig. 1B is a schematic diagram of another system architecture according to an embodiment of the present disclosure. Referring to fig. 1B, a receiver 40, a FEM20 and an antenna 30 are included, wherein the FEM20 includes an RX path. The receiver 40, FEM20 and antenna 30 may be provided in a wireless communication device. In practical applications, the antenna 30 may receive data transmitted by another communication device and transmit the received data to the RX path, and the RX path may perform filtering and other processing on the data and transmit the processed data to the receiver 40, so that the wireless communication device obtains the data transmitted by the other wireless communication device through the receiver 40.

Fig. 1C is a schematic diagram of another system architecture provided in the embodiment of the present application. Referring to fig. 1C, a transmitter 50, an FEM20 and an antenna 30 are included, wherein the FEM20 includes a TX path. The transmitter 50, the FEM20, and the antenna 30 may be provided in a wireless communication device. In practical applications, the transmitter 50 may acquire data generated by the wireless communication device and transmit the data to the FEM20, and the FEM20 may perform power amplification, filtering, and other processing on the data and transmit the processed data to the antenna 30, so that the antenna 30 transmits the data.

Fig. 1D is a schematic diagram of another system architecture provided in the embodiment of the present application. Referring to fig. 1D, a transmitter 50, a receiver 40, a FEM20 and an antenna 30 are included, wherein the FEM20 includes an RX path, a TX path and a single pole double throw switch. The transmitter 50, receiver 40, FEM20 and antenna 30 may be provided in a wireless communication device. In the data transmission process, the single-pole double-throw switch is communicated with the TX path, the transmitter 50 may acquire data generated by the wireless communication device and transmit the data to the FEM20, and the FEM20 may perform power amplification, filtering, and other processing on the data and transmit the processed data to the antenna 30, so that the antenna 30 transmits the data. In the data receiving process, the single-pole double-throw switch is connected to the RX path, the antenna 30 may receive data sent by other communication devices and send the received data to the RX path, and the RX path may perform processing such as filtering on the data and transmit the processed data to the receiver 40, so that the wireless communication device obtains the data sent by other wireless communication devices through the receiver 40. In this case, the hardware corresponding to the receiver 40 and the hardware corresponding to the transmitter 50 shown in fig. 1D may be independent of each other, or the receiver 40 and the transmitter 50 are located in the same hardware, and the receiver 40 and the transmitter 50 are logically independent.

In the conventional FEM, the RX path usually includes one channel circuit, and data transmission can be performed only through the one channel circuit. The TX path typically includes a lane circuit through which data can be received. The FEM can only receive data through the fixed channel circuit and transmit data through the fixed channel circuit, so that the FEM is only suitable for a specific communication scene, and the versatility of the FEM is poor. In order to solve the technical problem, the present application designs an FEM, where a path (RX path or TX path) in the FEM in the present application includes at least two channel circuits, so that the FEM can receive data through the at least two channel circuits, or the FEM can transmit data through the at least two channel circuits, and communication scenarios applicable to different channel circuits are different, so that the FEM can be applicable to multiple communication scenarios, so as to improve the versatility of the FEM.

Next, the structure of the FEM20 shown in the present application will be described by specific examples. It should be noted that the following embodiments may exist independently or may be combined with each other, and description of the same or similar contents is not repeated in different embodiments.

Fig. 2 is a schematic structural diagram of an FEM according to an embodiment of the present application. Referring to fig. 2, the FEM20 includes at least one communication port P-X, at least two channel circuits X corresponding to each communication port P-X, and an antenna port P-ANT, wherein one end of each channel circuit X is connected to the corresponding communication port P-X, and the other end of each channel circuit X is connected to the antenna port P-ANT. Each channel circuit X is further connected to a controller (not shown in the figure), and each channel circuit X is configured to receive a control signal sent by the controller, where the control signal is used to control a channel state of the channel circuit X; the channel state includes a conducting state and a disconnecting state, a state in which at most one channel circuit X exists in at least two channel circuits X corresponding to at least one communication port P-X at the same time is the conducting state, and the control signal is generated by the controller according to the first information and/or the second information of the FEM 20. The first information may include one or more of a hardware version, a country code, and the second information may include one or more of location information, power, rate (modulation coding scheme), or packet error rate of the FEM 20.

The at least one communication port P-X may comprise a transmit port and/or a receive port. The transmit port is for connecting with a transmitter in a wireless communication device. The receive port is for connection with a receiver in a wireless communication device. One communication port P-X corresponds to one path. The transmit port corresponds to a TX path that includes the transmit port and circuitry between the transmit port and the antenna port. For example, as shown in fig. 4 to 10, the circuits in the FEM20 other than the antenna port are TX paths, and as shown in fig. 15, the circuit in the frame where the TX paths are located is a TX path. The receive port corresponds to an RX path that includes the receive port and circuitry between the receive port and the antenna port. For example, as shown in fig. 11 to 14, the circuits other than the antenna port in the FEM20 are RX paths, and as shown in fig. 15, the circuit in the housing in which the RX paths are located is an RX path.

The same communication port P-X corresponds to at least two channel circuits, and the at least two communication circuits corresponding to the same communication port P-X are different. For example, each of the at least two channel circuits corresponding to the receiving port is different, and each of the at least two channel circuits corresponding to the transmitting port is different. The channel circuit difference may refer to: the channel circuits include different devices, or the connection relationships of the devices included in the channel circuits are different, or the parameters of the devices included in the channel circuits are different. For example, referring to fig. 4, the devices included in the channel circuit TX1 are a first switch circuit, the devices included in the channel circuit TX2 are a second switch circuit and a second peripheral circuit port P2, and the channel circuit TX1 and the channel circuit TX2 are different because the devices included in the channel circuit TX1 and the channel circuit TX2 are different. For example, referring to fig. 10, the devices included in the channel circuit TX1 are a first switch circuit and a first peripheral circuit port P1, the devices included in the channel circuit TX2 are a second switch circuit and a second peripheral circuit port P2, and the parameters of the first switch circuit and the second switch circuit are different, so that the channel circuit TX1 and the channel circuit TX2 are different.

It should be noted that, one communication port P-X corresponds to one path, and therefore, one communication port P-X corresponds to at least two channel circuits, and it can also be understood that at least two channel circuits are included in the path corresponding to the communication port P-X.

When data passes through different channel circuits corresponding to the same communication port P-X, different channel circuits perform different processing on the data, and further, the effect achieved by data transmission is different, for example, when data sent by wireless communication equipment passes through a first channel circuit corresponding to a sending port, the rate of data transmission can be optimized, and when data sent by the wireless communication equipment passes through a second channel circuit corresponding to the sending port, the quality of data transmission can be optimized. In the practical application process, different channel circuits can be controlled to be conducted according to the practical requirements (the effect achieved by data transmission is needed).

The antenna port P-ANT is used to connect with an antenna in the wireless communication device. The transmitter of the wireless communication device may transmit data to be transmitted to the antenna through the transmission port, one channel circuit corresponding to the transmission port, and the antenna port P-ANT, so that the antenna transmits the data. The antenna can also receive data from other wireless communication devices and transmit the received data to the wireless communication devices through the antenna port P-ANT, one channel circuit corresponding to the receiving port and the communication port.

The controller may be disposed in the FEM20, and may also be disposed in a radio frequency chip, for example, the radio frequency chip may be a WIFI chip, a bluetooth chip, a WLAN chip, or the like. The rf chip may also include rf circuitry therein, for example, the rf circuitry may include the transmitter 50 and/or the receiver 40 shown in fig. 1A-1D.

The number of the controllers may be one or more. When the number of the controllers is one, the controller may control at least two channel circuits corresponding to each communication port. When the number of the controllers is plural, the number of the controllers may be the same as the number of the communication ports, that is, the communication ports and the controllers may correspond to each other one by one, and accordingly, one controller may control at least two channel circuits corresponding to the communication port corresponding to the controller. Or, the number of the controllers may also be greater than 1 and smaller than the number of the communication ports, for example, a corresponding relationship between the controllers and the communication ports may be set, where the corresponding relationship may be that one controller corresponds to one or more communication ports, a corresponding relationship between the controllers and the communication ports may be set according to actual needs, and correspondingly, one controller may control at least two channel circuits corresponding to the communication ports corresponding thereto.

The controller may acquire the first information and/or the second information of the FEM20 and generate a control signal according to the first information and/or the second information. The control signal is used for controlling the channel states of at least two channel circuits corresponding to at least one communication port, and the channel states comprise a conducting state and a disconnecting state. The fact that the channel state of one channel circuit is in a conducting state means that a channel is formed between the channel circuit and the corresponding communication port and antenna port, and data can be transmitted through the channel. The fact that the channel state of one channel circuit is in the off state means that a channel is not formed between the channel circuit and the corresponding communication port and antenna port, and data cannot be transmitted through the channel.

For example, if the FEM20 includes two communication ports and each communication port corresponds to two channel circuits, a total of 4 channel circuits are included in the FEM20, and at most one channel circuit in the 4 channel circuits is in a conducting state. For example, if at least one communication port includes a receiving port and a transmitting port, the control signal may control one channel circuit corresponding to the transmitting port to be conducted when data is transmitted, and the control signal may control one channel circuit corresponding to the receiving port to be conducted when data is received.

Next, taking the controller disposed in the rf chip as an example, a process of acquiring the first information and/or the second information by the controller will be described with reference to fig. 3.

Fig. 3 is a schematic structural diagram of a wireless communication device according to an embodiment of the present application. Referring to fig. 3, the wireless communication device 90 includes an FEM20, a radio frequency chip 60, a memory 70 and a Global Positioning System (GPS) module, and the radio frequency chip 60 includes a controller. The memory 70 may be disposed inside the rf chip 60 or disposed outside the rf chip 60. The memory 70 stores the first information and program instructions, and optionally, the first information and program instructions may also be stored in a different memory 70, which is not specifically limited in this embodiment of the present application.

The first information may include one or more of a hardware version, a country code of the FEM 20. The first information may be determined at the time of shipment of the FEM20 and stored in the memory 70, and accordingly, the controller may acquire the first information in the memory 70

The first information. For example, when the FEM20 is shipped from the factory, the country code may be determined from the country to which the FEM20 is going to be sold, and when the FEM20 shipped from the factory is going to be sold to country a, the country code of the FEM20 may be determined to be country a. The hardware version refers to a version of a hardware device in the FEM20, and for example, the hardware version may include a hardware version number or the like.

The second information may include one or more of position information, power, rate (modulation coding scheme), or packet error rate of the FEM 20. The power may be a transmission power or a reception power. The rate may be a transmission rate or a reception rate. For example, when the communication port is a transmission port (a communication port corresponding to a TX path), the power may be a transmission power, and the rate may be a transmission rate. When the communication port is a receiving port (a communication port corresponding to the RX path), the power may be a receiving power, and the rate may be a receiving rate. The second information may be detected by the detection device. For example, for the position information, the detection device may be a GPS module 80, that is, the position information may be detected by the GPS module 80. The location information may also be determined according to an Internet Protocol (IP) address of the wireless communication device, where the IP address and the location information have a preset correspondence. For power, rate or packet error rate, the detecting device may be a controller (e.g., the controller shown in fig. 3), for example, the controller may perform power detection on the signal transmitted by the FEM20 to obtain the transmission power of the FEM20, and the controller may perform power detection on the signal received by the FEM20 to obtain the reception power of the FEM 20. The controller may obtain a modulation and coding scheme corresponding to the FEM20 (may also be referred to as a modulation and coding scheme corresponding to the wireless communication device where the FEM20 is located), and determine the rate of the FEM20 according to the modulation and coding scheme corresponding to the FEM20, for example, a preset correspondence exists between the modulation and coding scheme and the rate, the controller may determine the rate of the FEM20 according to the modulation and coding scheme corresponding to the FEM20 and the correspondence, when the wireless communication device performs modulation and coding by using one coding and modulation scheme, the wireless communication device may write the currently used modulation and coding scheme into a configuration file, and store the configuration file into the memory, and accordingly, the controller may obtain the modulation and coding scheme currently used by the wireless communication device in the memory. The controller may analyze the data packets transmitted and/or received by the FEM20 in a preset time period and determine a packet error rate according to the analysis result.

The controller may read the program instructions in the memory 70 and generate the control signal based on the acquired first information and/or second information and the program instructions. It should be noted that, in the following embodiments, a process of generating a control signal by a controller is described, and details are not described here.

In the embodiment shown in fig. 2, each communication port in the FEM20 corresponds to at least two channel circuits, that is, one path (RX path or TX path) includes at least two channel circuits, so that the FEM20 can receive data through the at least two channel circuits, or the FEM20 can transmit data through the at least two channel circuits, different channel circuits process data differently, and further, the data transmission effects are different, in an actual application process, different channel circuits can be controlled to be turned on according to an actual requirement (an effect that needs data transmission, and thus, the FEM20 can be applied to a plurality of communication scenarios with different transmission effect requirements, and the universality of the FEM20 is improved.

In practical applications, the FEM20 may include a TX path and/or an RX path. Next, the structure of the FEM20 when different paths are included in the FEM20 will be described.

Next, the structure of the FEM20 including one TX path will be explained. When the FEM20 includes one TX path, at least one communication port includes a transmission port. Next, the structure of the FEM20 will be described with reference to fig. 4 to 10, taking two channel circuits (a first channel circuit and a second channel circuit) corresponding to the transmission port as an example.

Fig. 4 is a schematic structural diagram of another FEM according to an embodiment of the present disclosure. Referring to fig. 4, the FEM20 includes a transmission port P-TX, a power amplifier PA, a first channel circuit TX1, a second channel circuit TX2, and an antenna port P-ANT, the first channel circuit TX1 includes a first switch circuit, and the second channel circuit TX2 includes a second switch circuit and a second peripheral circuit port P2P 2. One end of a power amplifier PA is connected with a transmitting port P-TX, the other end of the power amplifier PA is respectively connected with one ends of a first switch circuit and a second switch circuit, the other end of the first switch circuit is connected with an antenna port P-ANT, the other end of the second switch circuit is connected with a second peripheral circuit port P2, and the second peripheral circuit port P2 is further connected with the antenna port P-ANT. The first switch circuit and the second switch circuit are also respectively connected with the controller.

When the state of the first switch circuit is the on state, the first channel circuit TX1 is a straight-through circuit, so that when a signal passes through the first channel circuit TX1, no additional processing is required, so that the signal can be transmitted to the antenna port P-ANT through the first channel circuit TX1 with high efficiency and transmitted by the antenna.

When the second switch circuit is turned on, the second channel circuit TX2 includes a peripheral circuit, so that when a signal passes through the second channel circuit TX2, the peripheral circuit can process the signal, transmit the processed signal to the antenna port P-ANT, and transmit the signal from the antenna. The peripheral circuit may be a processing circuit that improves signal quality, e.g., the peripheral circuit may include a filter or the like. After the peripheral circuit processes the signal, the transmission quality of the signal can be made high. Optionally, when the peripheral circuit includes a filter, signals in a partial frequency band may be filtered by the filter, so as to change the corresponding operating frequency of the wireless communication device.

At the same time, the state in which at most one of the first switch circuit and the second switch circuit exists is the on state. The controller may generate a control signal corresponding to each switch circuit, and send the control signal corresponding to the first switch circuit, and send the control signal corresponding to the second switch circuit, where the control signal corresponding to the first switch circuit may control a state of the first switch circuit, and the control signal corresponding to the second switch circuit may control a state of the second switch circuit. The states of the first and second switch circuits include an on state and an off state. When the state of the first switch circuit is an on state, the channel state of the first channel circuit TX1 is an on state, and when the state of the first switch circuit is an off state, the channel state of the first channel circuit TX1 is an off state. When the state of the second switch circuit is an on state, the channel state of the second channel circuit TX2 is an on state, and when the state of the second switch circuit is an off state, the channel state of the second channel circuit TX2 is an off state.

At the same time, the control signal corresponding to the first switch circuit and the control signal corresponding to the second switch circuit sent by the controller may be the same. For example, the first switch circuit is turned on at a low level, the second switch circuit is turned on at a high level, when the first switch circuit needs to be turned on and the second switch circuit needs to be turned off, the controller may send low level signals to the first switch circuit and the second switch circuit, respectively, and when the first switch circuit needs to be turned off and the second switch circuit needs to be turned on, the controller may send high level signals to the first switch circuit and the second switch circuit, respectively.

At the same time, the control signal corresponding to the first switch circuit and the control signal corresponding to the second switch circuit sent by the controller may be different, for example, the first switch circuit is turned on at a low level, the second switch circuit is also turned on at a low level, when the first switch circuit is required to be turned on and the second switch circuit is required to be turned off, the controller may send a low level signal to the first switch circuit and a high level signal to the second switch circuit, and when the first switch circuit is required to be turned off and the second switch circuit is required to be turned on, the controller may send a high level signal to the first switch circuit and a low level signal to the second switch circuit.

In the embodiment shown in fig. 4, the TX path includes two channel circuits (a first channel circuit TX1 and a second channel circuit TX2), so that the FEM20 can transmit data through the two channel circuits, and different channel circuits process data differently, so that the data transmission effects are different, and in the actual application process, different channel circuits can be controlled to be conducted according to actual requirements (the effects that the data transmission needs to achieve), so that the FEM20 can be applied to a plurality of communication scenarios with different transmission effect requirements, and the universality of the FEM20 is improved. The second channel circuit TX2 includes a second peripheral circuit port P2, the peripheral circuit is disposed outside the FEM20, and in the practical application process, the peripheral circuit may be disposed according to practical requirements, for example, when the second channel circuit TX2 is required to have a filtering function, a filter may be disposed in the peripheral circuit, and when the transmission of the required signal through the second channel circuit TX2 has a smaller attenuation, an impedance matching circuit may be disposed in the peripheral circuit. The peripheral circuit is arranged outside the FEM20, and the function of the FEM can be changed by changing the peripheral circuit, so that the complexity of the circuit in the FEM20 can be reduced, and the flexibility of the FEM design can be improved.

Fig. 5 is a schematic structural diagram of another FEM according to an embodiment of the present application. Referring to fig. 5, the FEM20 includes a transmission port P-TX, a power amplifier PA, a first channel circuit TX1, a second channel circuit TX2, and an antenna port P-ANT, the first channel circuit TX1 includes a first switch circuit, and the second channel circuit TX2 includes a second switch circuit and a peripheral circuit. One end of a power amplifier PA is connected with a transmitting port P-TX, the other end of the power amplifier PA is respectively connected with one ends of a first switch circuit and a second switch circuit, the other end of the first switch circuit is connected with an antenna port P-ANT, the other end of the second switch circuit is connected with a peripheral circuit, and the peripheral circuit is also connected with the antenna port P-ANT. The first switch circuit and the second switch circuit are also respectively connected with the controller.

It should be noted that the functions of the components in fig. 5 are similar to those in fig. 4, and are not described again here.

In the embodiment shown in fig. 5, the TX path includes two channel circuits (a first channel circuit TX1 and a second channel circuit TX2), so that the FEM20 can transmit data through the two channel circuits, and different channel circuits process data differently, so that the data transmission effects are different, and in the actual application process, different channel circuits can be controlled to be conducted according to actual requirements (the effects that the data transmission needs to achieve), so that the FEM20 can be applied to a plurality of communication scenarios with different transmission effect requirements, and the universality of the FEM20 is improved. The peripheral circuit is arranged inside the EFM, and there is no need to arrange a peripheral circuit outside the FEM20, so that the FEM20 is high in convenience in use.

Next, the configuration of the switch circuits (the first switch circuit and the second switch circuit) will be described with reference to fig. 6, in addition to the embodiment shown in fig. 4.

Fig. 6 is a schematic structural diagram of another FEM according to an embodiment of the present application. In the embodiment shown in fig. 4, please refer to fig. 6, the first switch circuit includes a capacitor C1, a capacitor C2, an inductor L1 and a diode D1. The second switch circuits respectively include a capacitor C3, a capacitor C4, an inductor L2, and a diode D2.

When the first switch circuit is required to be turned on and the second switch circuit is required to be turned off, the control signal 1 output by the controller may be at a low level and the control signal 2 may be at a high level. When the control signal 1 is low, D1 is negatively biased, and when the control signal 2 is high, D2 is positively biased, in which case the input impedance from the output of the PA to the second channel circuit is very large, corresponding to an open circuit, causing the second channel circuit to be in an off state and the first channel circuit to be in an on state.

When the first switch circuit is required to be turned off and the second switch circuit is required to be turned on, the control signal 1 output by the controller may be at a high level and the control signal 2 may be at a low level. When the control signal 1 is at high level, D1 is biased positively, and when the control signal 2 is at low level, D2 is biased negatively, the input impedance from the output terminal of PA to the first channel circuit is very large, which is equivalent to an open circuit, so that the first channel circuit is in an off state and the second channel circuit is in an on state.

It should be noted that fig. 6 illustrates the configuration of the switch circuit by way of example only, and the configuration of the switch circuit is not limited, but may be other configurations, and the embodiment of the present application is not particularly limited thereto.

Optionally, the controller obtains the first information and/or the second information of the FEM20, and generates the control signal according to the first information and/or the second information. The first information may include one or more of a hardware version, a country code, and the second information may include one or more of location information, power, rate (modulation coding scheme), or packet error rate of the FEM 20. The process of the controller acquiring the first information and/or the second information of the FEM20 may refer to the embodiment shown in fig. 3, and will not be described herein again. The controller may generate the control signal from the first information and/or the second information in two ways.

One possible implementation is:

the controller determines the corresponding transmission requirement according to the first information and/or the second information, and generates a control signal according to the transmission requirement. Wherein, the transmission requirement is that the transmission efficiency is prior or the transmission quality is prior.

Optionally, the transmission effects corresponding to different channel circuits in one channel are different, for example, the transmission effect may be higher transmission efficiency or higher transmission quality. The controller may generate a control signal according to the determined transmission requirement, where the control signal is used to control one of the channel circuits to be turned on, and a transmission effect of the turned-on channel circuit matches the transmission requirement determined by the controller.

For example, assuming that the TX path includes the first path circuit TX1 and the second path circuit TX2, the transmission effect of the first path circuit TX1 is that the transmission efficiency is high, and the transmission effect of the second path circuit TX2 is that the transmission quality is high. Assuming that the controller determines that the obtained transmission requirement is prioritized by transmission efficiency according to the first information and/or the second information, the control signal generated by the controller may control the first channel circuit TX1 to be turned on and the second channel circuit TX2 to be turned off, so that the signal may be transmitted through the first channel circuit TX 1.

Another possible implementation:

the controller determines the corresponding working frequency according to the first information and/or the second information, and generates a control signal according to the working frequency. The operating frequency may be a transmission frequency of a signal transmitted by the antenna, or a reception frequency of a signal received by the receiver.

Optionally, the operating frequencies corresponding to different channel circuits in a channel may be different. The controller may generate a control signal according to the determined operating frequency, where the control signal is used to control one of the channel circuits to be turned on, and the operating frequency corresponding to the turned-on channel circuit is consistent with the operating frequency determined by the controller.

Optionally, a filter may be provided in the channel circuit, and the operating frequency of the channel circuit may be changed by the filter. For example, the filter may perform frequency filtering processing on the signal to be transmitted, so that after the signal subjected to the frequency filtering processing is transmitted through the antenna, the frequency of the transmitted signal is within a preset frequency range corresponding to the filter.

For example, it is assumed that the TX path includes a first path circuit TX1 and a second path circuit TX2, the transmission frequency of the first path circuit TX1 is frequency range 1, and the transmission frequency of the second path circuit TX2 is frequency range 2. Assuming that the controller determines that the obtained transmission frequency is the frequency range 2 according to the first information and/or the second information, the controller may generate a control signal to control the second channel circuit TX2 to be turned on and the first channel circuit TX1 to be turned off so that a signal may be transmitted through the second channel circuit TX 2.

Of course, the controller may also generate the control information in other manners, which is not specifically limited in this embodiment of the application.

When the capacities according to which the controllers generate the control signals are different, the processes of the controllers generating the control signals are also different, and several possible implementation manners of the controllers generating the control signals are described below:

one possible implementation is: the controller generates a control signal according to the position information in the second information.

The location information may indicate the area where the FEM20 is currently located. For example, the location information may include longitude and latitude, and the area where the FEM20 is currently located may be determined according to the longitude and latitude. For example, referring to fig. 3, the controller may obtain location information from a GPS module.

Alternatively, the transmission requirements for the signals may be different in different areas, for example, in the area a, the transmission requirements for the signals are transmission efficiency priority, and in the area B, the transmission requirements for the signals are transmission quality priority. The correspondence between the areas and the transmission requirements may be preset and stored in the memory. Accordingly, the controller may determine the current area of the FEM20 according to the position information, obtain a transmission requirement (rate-first or quality-first) corresponding to the current area of the FEM20 according to the correspondence, and generate the control signal according to the transmission requirement corresponding to the current area of the FEM 20. For example, the controller may read program instructions in the memory and execute the program instructions to enable generation of the control signal based on the location information and the correspondence.

Alternatively, the operating frequency requirements may be different in different regions. For example, in region a, the operating frequency may be frequency a to frequency B, and in region B, the operating frequency may be frequency c to frequency d. The correspondence between the region and the operating frequency may be set in advance and stored in the memory. Accordingly, the controller may determine the current region of the FEM20 according to the position information, obtain the operating frequency corresponding to the current region of the FEM20 according to the correspondence, and generate the control signal according to the operating frequency corresponding to the current region of the FEM 20. For example, the controller may read program instructions in the memory and execute the program instructions to enable generation of the control signal based on the location information and the correspondence.

Next, a description will be given of a state of a switching circuit in the FEM20 when the position of the FEM20 is changed, with reference to fig. 7, in addition to the structure of the FEM20 shown in fig. 4.

Fig. 7 is a schematic diagram illustrating state switching of a switch circuit according to an embodiment of the present disclosure. Referring to fig. 7, the states of the switching circuits in the FEM20 at time 1 and time 2 are included.

At time 1, the FEM20 is located at location 1, where location 1 belongs to area 1. Assuming that the transmission requirement corresponding to the area 1 is rate-first, the controller generates a control signal 1 corresponding to the first switch circuit and a control signal 2 corresponding to the second switch circuit, and sends the control signal 1 to the first switch circuit and the control signal 2 to the second switch circuit, where the control signal 1 is used to control the first switch circuit to be turned on and the control signal 2 is used to control the second switch circuit to be turned off. When a signal is transmitted through the FEM20 after the first switching circuit is turned on and the second switching circuit is turned off, the signal is transmitted to the antenna through the transmission port, the PA, the first channel circuit, and the antenna interface, and the signal is transmitted by the antenna. Because the first channel circuit is a through channel, additional processing on signals is not needed, so that the signals can be efficiently transmitted through the first channel circuit, and the transmission efficiency of the signals is higher.

At time 2, it is assumed that FEM20 has moved to position 2, which is region 2. Assuming that the transmission requirement corresponding to the area 2 is quality priority, the controller generates a control signal 3 corresponding to the first switch circuit and a control signal 4 corresponding to the second switch circuit, and sends the control signal 3 to the first switch circuit and the control signal 4 to the second switch circuit, wherein the control signal 3 is used for controlling the first switch circuit to be switched off, and the control signal 4 is used for controlling the second switch circuit to be switched on. When a signal is transmitted through the FEM20 after the first switch circuit is turned off and the second switch circuit is turned on, the signal is transmitted to the antenna through the transmission port, the PA, the second channel circuit, and the antenna interface, and the signal is transmitted by the antenna. The peripheral circuit in the second channel circuit can process the signal, so that the quality of the processed signal is higher, and the transmission quality of the signal is higher.

While one FEM20 in the prior art can be applied only to areas with the same transmission requirements, in the present application, the FEM20 can be applied to areas with a plurality of different transmission requirements, which improves the versatility of the FEM 20. For example, in the prior art, when the information transmission requirements of the area a and the area B are different, different FEMs 20 need to be designed for the area a and the area B, respectively, but in the present application, the same FEM20 may be designed for the area a and the area B, that is, one FEM20 may be used in both the area a and the area B.

Another possible implementation: the controller generates a control signal according to the hardware version in the first information.

The hardware version refers to a version of a hardware device in the FEM20, and for example, the hardware version may include a hardware version number or the like. The transmission requirements of signals corresponding to different hardware versions may be different, for example, the transmission requirement of the signal corresponding to version 1 is transmission efficiency priority, and the transmission requirement of the signal corresponding to version 2 is quality priority. The correspondence between the hardware version and the transmission requirement may be set in advance and stored in the memory. Correspondingly, the controller may obtain a transmission requirement (rate-first or quality-first) corresponding to the hardware version according to the correspondence, and generate the control signal according to the transmission requirement. For example, the controller may read program instructions in the memory and execute the program instructions to enable generation of the control signals according to the hardware version and the correspondence.

One FEM20 structure in the prior art can only be applied to hardware versions corresponding to the same transmission requirements, and in the present application, one FEM20 structure can be applied to hardware versions corresponding to a plurality of different transmission requirements, so that the universality of the FEM20 is improved. For example, in the prior art, when the transmission requirements of the hardware version a and the hardware version B for information are different, FEMs 20 with different structures need to be designed for the hardware version a and the hardware version B, respectively, whereas in the present application, FEMs 20 with the same structure can be designed for the hardware version a and the hardware version B.

Yet another possible implementation: the controller generates a control signal according to the country code in the first information.

Different countries have different country codes, and the transmission requirements of different countries for signals may be different, for example, country 1 has a priority on transmission efficiency, and country 2 has a priority on quality. The correspondence between the country code and the transmission requirement may be set in advance and stored in the memory. Correspondingly, the controller may obtain the transmission requirement corresponding to the country code according to the corresponding relationship, and generate the control signal according to the transmission requirement, for example, the controller may read the program instruction in the memory, and execute the program instruction, so as to generate the control signal according to the country code and the corresponding relationship.

While one FEM20 in the prior art can only be applied to countries with the same transmission requirements, in the present application, the FEM20 can be applied to countries with a plurality of different transmission requirements, improving the versatility of the FEM 20. For example, in the prior art, when the transmission requirements of the country a and the country B for information are different, different FEMs 20 need to be designed for the country a and the country B, respectively, while in the present application, the same FEM20 may be designed for the country a and the country B, that is, one FEM20 may be used in both the country a and the country B.

Alternatively, the operating frequency requirements may be different in different countries. For example, the operating frequencies required by country 1 may be frequency a to frequency b, and the operating frequencies required by country 2 may be frequency c to frequency d. The correspondence between the country and the operating frequency may be set in advance and stored in the memory. Accordingly, the controller may obtain the operating frequency corresponding to the country code according to the corresponding relationship, and generate the control signal according to the operating frequency, for example, the controller may read the program instruction in the memory, and execute the program instruction, so as to generate the control signal according to the country code and the corresponding relationship.

One FEM20 in the prior art can only be applied to countries with the same operating frequency requirement, but in the present application, the FEM20 can be applied to a plurality of countries with different operating frequency requirements, thereby improving the universality of the FEM 20. For example, in the prior art, when the requirement of the operating frequency is different between country a and country B, different FEMs 20 need to be designed for country a and country B, respectively, whereas in the present application, the same FEM20 may be designed for country a and country B, that is, one FEM20 may be used in both country a and country B.

Yet another possible implementation: the controller generates a control signal according to the power in the second information.

The power at which the transmitter transmits the signal may be different and the transmission requirements may be different for different powers. For example, when the power is less than the preset power threshold, the transmission requirement is transmission efficiency priority, and when the power is greater than or equal to the preset power threshold, the transmission requirement is transmission quality priority. In the actual application process, the preset power threshold may be set according to actual needs, and the preset power threshold is stored in the memory. Accordingly, the controller may obtain the power of the transmitter transmission signal and generate the control signal according to the power and the preset power threshold, for example, the controller may read a program instruction in a memory and execute the program instruction to generate the control signal according to the power of the transmitter transmission signal and the preset power threshold.

Next, with reference to fig. 8, a description will be given of a state of a switching circuit in the FEM20 when the power of the transmitter transmission signal is different, based on the configuration of the FEM20 shown in fig. 4.

Fig. 8 is a schematic diagram illustrating state switching of another switching circuit according to an embodiment of the present disclosure. Referring to fig. 8, the state of the switching circuit in FEM20 at time 1 and time 2 is included.

At time 1, the signal to be transmitted by the transmitter (connected to the transmission port, not shown in fig. 8) is signal 1, and the power of the signal 1 transmitted by the transmitter is power 1. Assuming that the power 1 is smaller than the preset power threshold, the controller generates a control signal 1 corresponding to the first switch circuit and a control signal 2 corresponding to the second switch circuit according to the magnitude relation between the power 1 and the preset power threshold, and sends the control signal 1 to the first switch circuit and the control signal 2 to the second switch circuit, wherein the control signal 1 is used for controlling the first switch circuit to be switched on, and the control signal 2 is used for controlling the second switch circuit to be switched off. When the transmitter transmits a signal 1 through the FEM20 after the first switching circuit is turned on and the second switching circuit is turned off, the signal 1 is transmitted to the antenna through the transmission port, the PA, the first channel circuit, and the antenna interface, and the antenna transmits the signal 1. Because the first channel circuit is a through channel, additional processing on the signal 1 is not needed, so that the signal 1 can be efficiently transmitted through the first channel circuit, and the transmission efficiency of the signal 1 is higher.

At time 2, the signal to be transmitted by the transmitter (connected to the transmission port, not shown in fig. 7) is signal 2, and the power of the transmitter transmission signal 2 is power 2. Assuming that the power 2 is greater than the preset power threshold, the controller generates a control signal 3 corresponding to the first switch circuit and a control signal 4 corresponding to the second switch circuit according to a magnitude relation between the power 2 and the preset power threshold, and sends the control signal 3 to the first switch circuit and the control signal 4 to the second switch circuit, wherein the control signal 3 is used for controlling the first switch circuit to be turned off, and the control signal 4 is used for controlling the second switch circuit to be turned on. When the transmitter transmits a signal 2 through the FEM20 after the first switch circuit is turned off and the second switch circuit is turned on, the signal 2 is transmitted to the antenna through the transmission port, the PA, the second channel circuit, and the antenna interface, and the antenna transmits the signal 2. Since the peripheral circuit in the second channel circuit can process the signal 2, the quality of the processed signal 2 is high, and therefore, the transmission quality of the signal 2 can be high.

The power in different communication scenarios is typically within a corresponding range, which may be different. For example, the communication scenario may be an industrial communication scenario, a home communication scenario, or the like. For example, the power in communication scenario 1 may be in power range 1 and the power in communication scenario 2 may be in power range 2. In the prior art, different FEMs 20 need to be designed for communication scenarios in which the power is smaller than the preset power threshold and communication scenarios in which the power is greater than or equal to the preset power threshold, that is, one FEM20 can only be applied to communication scenarios in which the power is smaller than the preset power threshold, or only to communication scenarios in which the power is greater than or equal to the preset power threshold. In the present application, for a communication scenario in which the power is less than the preset power threshold and a communication scenario in which the power is greater than or equal to the preset power threshold, the same FEM20 may be designed, that is, one FEM20 may be applied to both a communication scenario in which the power is less than the preset power threshold and a communication scenario in which the power is greater than or equal to the preset power threshold, so that the FEM20 has high versatility.

Another possible implementation: a control signal is generated based on the rate in the first information.

The rate at which the transmitter transmits the signal may be different and the transmission requirements may be different for different rates. For example, when the rate is less than the preset rate threshold, the transmission requirement is transmission efficiency first, and when the rate is greater than or equal to the preset rate threshold, the transmission requirement is transmission quality first. In the actual application process, the preset rate threshold may be set according to actual needs, and the preset rate threshold is stored in the memory. Accordingly, the controller obtains the rate at which the transmitter transmits the signal and generates the control signal according to the rate and the preset rate threshold, for example, the controller may read program instructions in the memory and execute the program instructions to generate the control signal according to the rate at which the transmitter transmits the signal and the preset rate threshold.

It should be noted that when the rates are different, the states of the switch circuits in the FEM20 are also different, and the switching process of the states of the switch circuits in the FEM20 may refer to the switching process of the switch circuits shown in the embodiment of fig. 8, which is not described herein again.

The rates in different communication scenarios are usually within corresponding ranges, which may be different. For example, the communication scenario may be an industrial communication scenario, a home communication scenario, or the like. For example, the rate in communication scenario 1 may be in rate range 1, and the rate in communication scenario 2 may be in rate range 2. In the prior art, for a communication scenario in which a rate is less than a preset rate threshold and a communication scenario in which the rate is greater than or equal to the preset rate threshold, different FEMs 20 need to be designed, that is, one FEM20 can only be applied to a communication scenario in which the rate is less than the preset rate threshold, or only to a communication scenario in which the rate is greater than or equal to the preset rate threshold. In the present application, for a communication scenario in which the rate is less than the preset rate threshold and a communication scenario in which the rate is greater than or equal to the preset rate threshold, the same FEM20 may be designed, that is, one FEM20 may be applied to a communication scenario in which the rate is less than the preset rate threshold and may also be applied to a communication scenario in which the rate is greater than or equal to the preset rate threshold, so that the FEM20 has high versatility.

Another possible implementation: and generating a control signal according to the packet error rate in the first information.

The packet error rate is the ratio of the number of erroneous data packets in transmission to the total number of data packets transmitted. The transmission requirements may be different for different packet error rates. For example, when the packet error rate is less than the predetermined packet error rate threshold, the transmission requirement is transmission efficiency priority, and when the packet error rate is greater than or equal to the predetermined packet error rate threshold, the transmission requirement is transmission quality priority. In the actual application process, the preset packet error rate threshold value can be set according to actual needs, and is stored in the memory. Correspondingly, the controller obtains the packet error rate of the transmitter in a preset time period before the current time, and generates the control signal according to the packet error rate and the preset packet error rate threshold, for example, the controller may read a program instruction in the memory, and execute the program instruction, so as to generate the control signal according to the packet error rate of the signal sent by the transmitter and the preset packet error rate threshold.

It should be noted that, when the packet error rates are different, the states of the switch circuits in the FEM20 are also different, and the switching process of the states of the switch circuits in the FEM20 may refer to the switching process of the switch circuits shown in the embodiment of fig. 8, which is not described herein again.

The packet error rate under different communication scenarios is usually in a corresponding range, and the ranges corresponding to the packet error rates under different communication scenarios may be different. For example, the communication scenario may be an industrial communication scenario, a home communication scenario, or the like. For example, the packet error rate in communication scenario 1 may be in packet error rate range 1, and the packet error rate in communication scenario 2 may be in packet error rate range 2. In the prior art, different FEMs 20 need to be designed for communication scenarios in which the packet error rate is smaller than the preset packet error rate threshold and communication scenarios in which the packet error rate is greater than or equal to the preset packet error rate threshold, that is, one FEM20 may only be applicable to communication scenarios in which the packet error rate is smaller than the preset packet error rate threshold, or may only be applicable to communication scenarios in which the packet error rate is greater than or equal to the preset packet error rate threshold. In the present application, the same FEM20 may be designed for a communication scenario in which the packet error rate is less than the preset packet error rate threshold and a communication scenario in which the packet error rate is greater than or equal to the preset packet error rate threshold, that is, one FEM20 may be applied to both a communication scenario in which the packet error rate is less than the preset packet error rate threshold and a communication scenario in which the packet error rate is greater than or equal to the preset packet error rate threshold, so that the FEM20 has high versatility.

Optionally, when the first information and the second information include two or more of location information, hardware version, country code, power, rate, or packet error rate, a priority corresponding to each of the above information may be set, and the controller may generate the control signal according to the priority of each of the information. For example, assuming that the second information includes position information and power, the controller generates the control signal according to the position information assuming that the priority of the position information is greater than the priority of the power.

On the basis of the FEM20 shown in fig. 4, optionally, in order to improve the signal transmission quality, a first impedance matching circuit may be further provided in the first channel circuit, and a second impedance matching circuit may be further provided in the second channel circuit. Next, the structure of the FEM20 will be described with reference to fig. 9 to 10.

Fig. 9 is a schematic structural diagram of another FEM according to an embodiment of the present application. In addition to the embodiment shown in fig. 4, referring to fig. 9, the first channel circuit TX1 further includes a first impedance matching circuit, one end of the first impedance matching circuit is connected to the first switch circuit, and the other end of the first impedance matching circuit is connected to the antenna port P-ANT. The second channel circuit TX2 further includes a second impedance matching circuit, one end of which is connected to the second switch circuit, and the other end of which is connected to the second peripheral circuit port P2.

Fig. 10 is a schematic structural diagram of another FEM according to an embodiment of the present application. Based on the embodiment shown in fig. 4, referring to fig. 10, the first channel circuit TX1 further includes a first peripheral circuit port, where the first peripheral circuit port is used for connecting with a first impedance matching circuit, and the first impedance matching circuit is located outside the FEM 20. The second channel circuit TX2 further includes a second impedance matching circuit connected to the second peripheral circuit port P2, which is located outside the FEM 20. By arranging the first impedance matching circuit and the second impedance matching circuit outside the FEM20, the circuit complexity of the FEM20 can be reduced, and the first impedance matching circuit and the second impedance matching circuit can be designed according to actual needs, for example, in the actual application process, the first impedance matching circuit can be changed according to actual needs to enable the first channel circuit TX1 to achieve different impedance matching effects, or the second impedance matching circuit can be changed according to actual needs to enable the second channel circuit TX2 to achieve different impedance matching effects, so that the flexibility of circuit design is high.

In the FEM20 shown in fig. 9 to 10, the first impedance matching circuit may be formed of one or more of a resistor, a capacitor, and an inductor. The first impedance matching circuit may reduce attenuation of the signal during transmission of the signal in the first channel circuit. The second impedance matching circuit may be formed of one or more of a resistor, a capacitor, and an inductor. The second impedance matching circuit may reduce attenuation of the signal during transmission of the signal in the second channel circuit.

It should be noted that fig. 9-10 illustrate the structure of the FEM20 by way of example only, and the structure of the FEM20 is not limited, for example, the first impedance matching circuit may be disposed inside the FEM20, and the second impedance matching circuit may be disposed outside the FEM20, or the first impedance matching circuit may be disposed inside the FEM20, and the second impedance matching circuit may be disposed outside the FEM 20. For example, the connection order between the transmission port, the PA, the first channel circuit, the second channel circuit, and the antenna port may also be other, and for example, the PA may also be provided between the first channel circuit, the second channel circuit, and the antenna port. For example, the number of the PAs may be two, which are respectively referred to as a first PA and a second PA, where one end of the first PA is connected to the transmission port, the other end of the first PA is connected to the first switch circuit, one end of the second PA is connected to the transmission port, and the other end of the second PA is connected to the second switch circuit.

It should be noted that, when the above TX path is included in the FEM20, other paths may also be included in the FEM20, for example, an RX path in the prior art or the RX path shown in fig. 11 to 14 described below may also be included in the FEM 20.

When one RX path is included in the FEM20, a reception port is included in at least one communication port. Next, the structure of the FEM20 will be described with reference to fig. 11 to 14, taking an example in which the transmission port corresponds to two channel circuits (a first channel circuit and a second channel circuit).

Fig. 11 is a schematic structural diagram of another FEM according to an embodiment of the present application. Referring to fig. 11, the FEM20 includes a receiving port P-RX, a low noise amplifier LNA, a first channel circuit RX1, a second channel circuit RX2, and an antenna port P-ANT, the first channel circuit RX1 includes a first switch circuit, and the second channel circuit RX2 includes a second switch circuit and a second peripheral circuit port P2. One end of a low noise amplifier LNA is connected with a receiving port P-RX, the other end of the low noise amplifier LNA is connected with one ends of circuits of a first switch circuit and a second switch respectively, the other end of the first switch circuit is connected with an antenna port P-ANT, the other end of the second switch circuit is connected with a second peripheral circuit port P2, and the second peripheral circuit port P2 is further connected with the antenna port P-ANT. The first switch circuit and the second switch circuit are also respectively connected with the controller.

Fig. 12 is a schematic structural diagram of another FEM according to an embodiment of the present application. Referring to fig. 12, the FEM20 includes a reception port P-RX, a low noise amplifier LNA, a first channel circuit RX1, and an antenna port P-ANT, the first channel circuit RX1 includes a first switch circuit, and the second channel circuit RX2 includes a second switch circuit and peripheral circuits. One end of a low noise amplifier LNA is connected with a receiving port P-RX, the other end of the low noise amplifier LNA is respectively connected with one ends of circuits of a first switch circuit and a second switch, the other end of the first switch circuit is connected with an antenna port P-ANT, the other end of the second switch circuit is connected with a peripheral circuit, and the peripheral circuit is further connected with the antenna port P-ANT. The first switch circuit and the second switch circuit are also respectively connected with the controller.

Fig. 13 is a schematic structural diagram of another FEM according to an embodiment of the present application. On the basis of the FEM20 shown in fig. 11, the first channel circuit RX1 further includes a first impedance matching circuit, and the second channel circuit RX2 further includes a second impedance matching circuit.

Fig. 14 is a schematic structural diagram of another FEM according to an embodiment of the present application. On the basis of the FEM20 shown in fig. 11, the first channel circuit RX1 further includes a first peripheral circuit port for connecting a first impedance matching circuit, which is located outside the FEM 20. The second peripheral circuit port P2 is also used to connect a second impedance matching circuit, which is located outside the FEM 20.

In the embodiments shown in fig. 11 to 14, reference may be made to the embodiment shown in fig. 3 for a process of acquiring the first information and/or the second information by the controller, and reference may be made to the above-mentioned embodiment for a process of generating the control signal by the controller according to the first information and/or the second information, which is not described herein again.

It should be noted that the first channel circuit in the embodiments of fig. 11 to 14 is not the same as the first channel circuit in fig. 4 to 10, and the same description is used for convenience of description. Similarly, the second channel circuit in the embodiment of fig. 11-14 is not the same channel circuit as the first channel circuit in fig. 4-10. The first switching circuit in the embodiment of fig. 11-14 is not the same switching circuit as the first switching circuit of fig. 4-10. The second switching circuit in the embodiment of fig. 11-14 is not the same switching circuit as the second switching circuit in fig. 4-10. The first peripheral circuit interface in the embodiment of fig. 11-14 is not the same interface as the first peripheral circuit interface in fig. 4-10. The second peripheral circuit interface in the embodiment of fig. 11-14 is not the same interface as the second peripheral circuit interface in fig. 4-10.

It should be noted that the structure and the working process of the FEM20 shown in fig. 11-14 can refer to the embodiments shown in fig. 4-10, and are not described herein again.

It should be noted that, when the above RX path is included in the FEM20, other paths may also be included in the FEM20, for example, an RX path in the prior art or the TX path in the above embodiments shown in fig. 4 to fig. 10 may also be included in the FEM 20.

When the FEM20 includes one TX path and one RX path, at least one communication port includes a transmission port and a reception port. In this case, the FEM20 includes circuitry in the TX path shown in any of the embodiments of fig. 4-5, 9-10, and circuitry in the RX path shown in any of the embodiments of fig. 11-14. Next, with reference to fig. 15, a structure of the FEM20 when including one TX path and one RX path will be described.

It should be noted that fig. 11 to 14 illustrate the structure of the FEM20 by way of example only, and the structure of the FEM20 is not limited, for example, the first impedance matching circuit may be disposed inside the FEM20, and the second impedance matching circuit may be disposed outside the FEM20, or the first impedance matching circuit may be disposed inside the FEM20, and the second impedance matching circuit may be disposed outside the FEM 20. For example, the connection order between the transmission port, the LNA, the first channel circuit, the second channel circuit, and the antenna port may also be other, and for example, the LNA may also be provided between the first channel circuit, the second channel circuit, and the antenna port. For example, the number of the LNAs may be two, which are respectively referred to as a first LNA and a second LNA, one end of the first LNA is connected to the receiving port, the other end of the first LNA is connected to the first switch circuit, one end of the second LNA is connected to the receiving port, and the other end of the second LNA is connected to the second switch circuit.

Fig. 15 is a schematic structural diagram of another FEM according to an embodiment of the present application. Fig. 15 includes the circuits in the TX path shown in fig. 9 and the circuits in the RX path shown in fig. 13. The connection relationship and the working process can be referred to the above embodiments, and are not described herein again. It should be noted that, when the FEM20 includes the TX path and the RX path, the FEM20 may include the TX path in any embodiment of fig. 4-10, and the RX path in any embodiment of fig. 11-14.

In the embodiment shown in fig. 15, the data transmission scheme adopted by the FEM is time division multiplexing, in other words, only one of the RX1 channel circuit, the RX2 channel circuit, the TX1 channel circuit and the TX2 channel circuit is usually turned on at one time.

In the practical application process, the data transmission mode adopted by the FEM is time division multiplexing or frequency division multiplexing.

When the data transmission mode adopted by the FEM is time division multiplexing, one of all the channel circuits in the FEM receives or transmits data through the antenna port, in other words, at most one of all the channel circuits in the FEM has data received or transmitted through the antenna port at one time.

When the data transmission mode adopted by the FEM is frequency division multiplexing, M channel circuits in all channel circuits in the chip system receive or send data through antenna ports; when M is greater than or equal to 2, any two channel circuits in the M channel circuits do not correspond to the same communication port. In other words, for any one communication port, at most one of the at least two channel circuits corresponding to the communication port receives or transmits data through the antenna port.

Next, a process of data transmission by the FEM using time division multiplexing or frequency division multiplexing will be described with reference to the embodiments shown in fig. 16 to 17.

Fig. 16 is a schematic structural diagram of another FEM according to an embodiment of the present application. Referring to fig. 16, including the circuits in the TX path shown in fig. 9, the circuits in the RX path shown in fig. 13, and the filter, a first end of the filter is connected to the RX1 channel circuit, the RX2 channel circuit, the TX1 channel circuit, and the TX2 channel circuit, and the other end of the filter is connected to the antenna port P-ANT. The connection relationship and operation process of each component in the TX path and the RX path can be referred to the above embodiments, and are not described herein again. It should be noted that, when the FEM20 includes the TX path and the RX path, the FEM20 may include the TX path in any embodiment of fig. 4-10, and the RX path in any embodiment of fig. 11-14.

In the embodiment shown in fig. 16, the data transmission method adopted by the FEM may be time division multiplexing or frequency division multiplexing. For example, in a WIFI communication scenario, the data transmission method adopted by the FEM is usually time division multiplexing. In scenarios such as Long Term Evolution (LTE), fifth generation mobile communication technology (5G), etc., a data transmission method adopted by the FEM is usually frequency division multiplexing.

When the data transmission mode adopted by the FEM is time division multiplexing, only one of the RX1 channel circuit, the RX2 channel circuit, the TX1 channel circuit and the TX2 channel circuit usually receives or transmits data through the antenna port.

When the data transmission mode adopted by the FEM is frequency division multiplexing, one of the RX1 channel circuit and the RX2 channel circuit receives data through an antenna port, or neither the RX1 channel circuit nor the RX2 channel circuit receives data; one of the TX1 channel circuit and the TX2 channel circuit transmits data through the antenna port, or neither the TX1 channel circuit nor the TX2 channel circuit transmits data. In this case, the frequency corresponding to the RX path and the frequency corresponding to the TX path are different, and at the same time, data may be transmitted and received simultaneously through the RX path and the TX path, for example, the filter may perform filtering processing on the transmitted data to limit the frequency of the transmitted data within the frequency range corresponding to the TX path, and the filter may also perform filtering processing on the received data to limit the frequency of the received data within the frequency range corresponding to the RX path.

Optionally, the FEM may further include two or more receiving paths, or the FEM may further include two or more transmitting paths. Next, with reference to fig. 17, an example in which the FEM includes two reception paths will be described.

Fig. 17 is a schematic structural diagram of another FEM according to an embodiment of the present application. Referring to fig. 17, the RX antenna comprises two circuits in the RX paths (referred to as RX path 1 and RX path 2, respectively) shown in fig. 13 and a filter, wherein a first end of the filter is connected to an RX11 channel circuit, an RX12 channel circuit, an RX21 channel circuit and an RX22 channel circuit, and the other end of the filter is connected to an antenna port P-ANT. The connection relationship and the operation process of each component in the RX paths 1 and 2 can be referred to the above embodiments, and are not described herein again. It should be noted that the RX paths included in the FEM20 may be the RX paths in any of the embodiments of fig. 11-14.

In the embodiment shown in fig. 17, the data transmission method adopted by the FEM may be time division multiplexing or frequency division multiplexing. For example, in a WIFI communication scenario, the data transmission method adopted by the FEM is usually time division multiplexing. In scenarios such as LTE and 5G, the data transmission scheme adopted by FEM is usually frequency division multiplexing.

When the data transmission method adopted by the FEM is time division multiplexing, only one of the RX11 channel circuit, the RX12 channel circuit, the RX21 channel circuit and the RX22 channel circuit usually receives or transmits data through the antenna port.

When the data transmission mode adopted by the FEM is frequency division multiplexing, one of the RX11 channel circuit and the RX12 channel circuit receives data through an antenna port, or neither the RX11 channel circuit nor the RX12 channel circuit receives data; one of the RX21 channel circuit and the RX22 channel circuit exists to receive data through the antenna port, or neither the RX21 channel circuit nor the RX22 channel circuit transmits data. In this case, the frequency corresponding to RX path 1 is different from the frequency corresponding to RX path 2, and data reception may be performed simultaneously through RX path 1 and RX path 2 at one time, for example, the filter may perform a first filtering process on the received data to obtain data with a frequency in the frequency range corresponding to RX path 1, and transmit the data to RX path 1; the filter may also perform a second filtering process on the received data to obtain data having a frequency in a frequency range corresponding to the RX path 2, and transmit the data to the RX path 2.

It should be noted that, when a plurality (greater than 2) of receiving paths are included in the FEM, the structure and the working process of the FEM may be referred to in fig. 17, and are not described herein again. When two or more transmission paths are included in the FEM, the structure and operation of the FEM can be referred to fig. 17, and will not be described herein again.

Fig. 18 is a schematic structural diagram of another FEM according to an embodiment of the present application. In addition to the embodiment shown in fig. 4, referring to fig. 18, the FEM20 further includes a controller. The functions of the controller shown in the embodiment of fig. 18 are the same as those of the controller in the above-described embodiment and the connection relationship with each component in the FEM20, and the description thereof is omitted.

Fig. 19 is a schematic structural diagram of a circuit according to an embodiment of the present application. Referring to fig. 19, the circuit 100 includes the FEM20 and the rf chip 60 shown in any of the above embodiments, and the rf chip 50 includes the controller shown in any of the above embodiments, and the rf chip is configured to transmit data to the communication port and/or receive data from the communication port. The rf chip 60 can be referred to the description of the rf chip in the embodiment of fig. 3, and the description thereof is omitted here.

Fig. 20 is a schematic structural diagram of another wireless communication device according to an embodiment of the present application. Referring to fig. 20, the wireless communication device 90 includes the circuit 100 shown in the embodiment of fig. 19, that is, the wireless communication device 90 includes the FEM20 (the FEM20 shown in any of the above embodiments) and the rf chip 60.

Referring to fig. 3, the wireless communication device 90 further includes a memory 70, the memory 70 is connected to the controller, and the information stored in the memory 70 includes the first information. Alternatively, the memory 70 may be disposed outside the rf chip 60.

Referring to fig. 3, the wireless communication device 90 may further include a GPS module 80, and the GPS module 80 is configured to acquire the location information of the wireless communication device and send the location information to the controller.

It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.

In the present application, the terms "include" and variations thereof may refer to non-limiting inclusions; the term "or" and variations thereof may mean "and/or". The terms "first," "second," and the like in this application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. In the present application, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Claims

1. A chip system, comprising: an antenna port, at least one communication port, at least two channel circuits corresponding to each communication port, wherein,

the first end of each channel circuit is connected with the corresponding communication port, and the second end of each channel circuit is connected with the antenna port;

the third end of each channel circuit is connected with the controller, each channel circuit is used for receiving a control signal sent by the controller, and the control signal is used for controlling the channel circuit to receive or send data through the antenna port; the control signal is generated by the controller according to first information and/or second information of the chip system, and the first information includes at least one of the following: hardware version or country code, the second information includes at least one of: location information, power, rate, or packet error rate.

2. The system on a chip of claim 1, wherein the data transmission scheme adopted by the system on a chip is time division multiplexing;

and one of all the channel circuits in the chip system receives or transmits data through the antenna port.

3. The system on a chip of claim 1, wherein the data transmission scheme adopted by the system on a chip is frequency division multiplexing;

m channel circuits in all the channel circuits in the chip system receive or send data through the antenna port;

when M is greater than or equal to 2, any two channel circuits in the M channel circuits do not correspond to the same communication port.

4. The chip system according to any of claims 1-3, wherein the channel circuit comprises a switch circuit and a peripheral circuit port, wherein,

the switch circuit is connected with the controller and is used for receiving the control signal;

the peripheral circuit ports of the different channel circuits corresponding to the same communication port are used for connecting different peripheral circuits.

5. The chip system according to any of claims 1 to 3, wherein the channel circuit includes a switch circuit and a peripheral circuit, wherein,

the peripheral circuits in different channel circuits are different.

6. The chip system according to any of claims 1 to 3, wherein the at least two channel circuits comprise a first channel circuit and a second channel circuit, wherein,

the first channel circuit comprises a first switch circuit, the first switch circuit is connected with the controller, and the first switch circuit is used for receiving the control signal;

the second channel circuit comprises a second switch circuit and a second peripheral circuit port, the second switch circuit is connected with the controller, the second switch circuit is used for receiving the control signal, and the second peripheral circuit port is used for connecting a peripheral circuit.

7. The chip system according to claim 6,

the first channel circuit further includes a first impedance matching circuit, or,

the first channel circuit also includes a first peripheral circuit port for connecting a first impedance matching circuit.

8. The chip system according to claim 6 or 7,

the second channel circuit further comprises a second impedance matching circuit; alternatively, the first and second electrodes may be,

the second peripheral port circuit is also for connection to a second impedance matching circuit.

9. The chip system according to any one of claims 1 to 8, wherein the at least one communication port includes a transmission port, and at least two channel circuits are channel circuits corresponding to the transmission port; the chip system further comprises a power amplifier, wherein the power amplifier is respectively connected with the transmitting port and the at least two channel circuits.

10. The chip system according to any one of claims 1 to 8, wherein the at least one communication port includes a receiving port, and at least two channel circuits are corresponding channel circuits of the receiving port; the chip system further comprises a low noise amplifier, wherein the low noise amplifier is respectively connected with the receiving port and the at least two channel circuits.

11. The chip system according to any of claims 1 to 8, wherein the at least one communication port comprises a transmitting port and a receiving port, and the at least two channel circuits comprise at least two channel circuits corresponding to the transmitting port and at least two channel circuits corresponding to the receiving port; the chip system further comprises a power amplifier and a low noise amplifier, wherein,

the power amplifier is respectively connected with the sending port and at least two channel circuits corresponding to the sending port;

the low noise amplifier is respectively connected with the receiving port and at least two channel circuits corresponding to the receiving port.

12. The chip system according to any of the preceding claims 9 to 11, wherein the number of said at least one communication port is larger than 1, said chip system further comprising a filter, wherein,

the first end of the filter is connected with the at least two channel circuits;

a second end of the filter is connected to the antenna port.

13. The chip system according to any of the preceding claims 1 to 12, further comprising the controller.

14. A circuit comprising a radio-frequency chip and a chip-system according to any one of claims 1 to 12, the radio-frequency chip comprising the controller, the radio-frequency chip being configured to transmit data to the communication port and/or the radio-frequency chip being configured to receive data from the communication port.

15. A wireless communication device comprising the circuit of claim 14.

16. The wireless communication device of claim 15, further comprising a memory coupled to the controller, wherein the information stored in the memory comprises the first information.

17. The wireless communication device of claim 16, wherein the radio frequency chip comprises the memory.

18. The wireless communication device of claim 16 or 17, further comprising a Global Positioning System (GPS) module, the GPS module coupled to the controller, wherein,

the GPS module is used for acquiring the position information of the wireless communication equipment and sending the position information to the controller.