CN110875301A - Semiconductor package - Google Patents

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Publication number
CN110875301A
CN110875301A CN201910796548.4A CN201910796548A CN110875301A CN 110875301 A CN110875301 A CN 110875301A CN 201910796548 A CN201910796548 A CN 201910796548A CN 110875301 A CN110875301 A CN 110875301A
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China
Prior art keywords
semiconductor
semiconductor substrate
regions
chip
semiconductor chip
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CN201910796548.4A
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Chinese (zh)
Inventor
洪志硕
朴辰遇
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN110875301A publication Critical patent/CN110875301A/en
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    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention may provide a semiconductor package, comprising: a first device layer comprising a first semiconductor device, a first cap insulating layer, and a first through electrode passing through at least a portion of the first device layer; a second device layer including a second semiconductor device, a second cover insulating layer, and a second through electrode penetrating at least a portion of the second device layer, the second semiconductor device being vertically overlapped with the first semiconductor device, respectively, the second cover insulating layer being in contact with the first cover insulating layer; a third device layer comprising an upper semiconductor chip vertically overlapping at least two of the first semiconductor devices and at least two of the second semiconductor devices; and a device bonding pad passing through the first and second cover insulating layers, the device bonding pad electrically connecting the first and second through electrodes to the upper semiconductor chip.

Description

Semiconductor package
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application claims priority from korean patent application No. 10-2018-0104702 filed by the korean intellectual property office on 3/9/2018, the disclosure of which is incorporated herein by reference in its entirety.
Technical Field
The present inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a plurality of semiconductor chips.
Background
As the electronics industry develops and user demand increases, electronic devices are being manufactured with more compact designs, more functionality and/or higher storage capacities. Therefore, there is a need for a semiconductor package including two or more types of semiconductor chips, and a Printed Circuit Board (PCB) or an interposer may be used for electrical connection between the different types of semiconductor chips. However, it is difficult to achieve a fine pitch when using a PCB, and to avoid an increase in manufacturing costs when using a via.
Disclosure of Invention
At least one or more of the present concepts provide a semiconductor package including a plurality of semiconductor chips having a relatively small form factor (small form factor), a relatively fine pitch, and/or a relatively low cost.
According to an example embodiment, a semiconductor package includes: a first device layer comprising a plurality of first semiconductor devices, a first capping insulating layer, and a plurality of first through electrodes passing through at least a portion of the first device layer; a second device layer including a plurality of second semiconductor devices vertically overlapped with the plurality of first semiconductor devices, respectively, a second capping insulating layer contacting the first capping insulating layer, and a plurality of second through electrodes penetrating at least a portion of the second device layer; a third device layer including an upper semiconductor chip vertically overlapping at least two of the plurality of first semiconductor devices and vertically overlapping at least two of the plurality of second semiconductor devices; and a plurality of device bonding pads passing through the first and second cover insulating layers, the plurality of device bonding pads electrically connecting the plurality of first and second through electrodes to the upper semiconductor chip.
According to example embodiments, a semiconductor package includes a first device layer, a second device layer, a third device layer, and a plurality of device bond pads. The first device layer may include: (1) a first semiconductor substrate; (2) a plurality of first through electrodes located in the plurality of first semiconductor chip regions and penetrating the first semiconductor substrate; and (3) a first cover insulating layer covering the active surface of the first semiconductor substrate. The first semiconductor substrate may have an active surface and may include one or more first scribe lines and a plurality of first semiconductor chip regions spaced apart from one another by the one or more first scribe line regions therebetween, each of the plurality of first semiconductor chip regions having a first semiconductor device disposed on the active surface of the first semiconductor substrate. The second device layer may comprise: (1) a second semiconductor substrate; (2) a plurality of second through electrodes in the plurality of second semiconductor chip regions and passing through the second semiconductor substrate; and (3) a second insulating layer covering the active surface of the second semiconductor substrate and in contact with the first insulating cover layer. The second semiconductor substrate has an active surface and may include one or more second scribe areas and a plurality of second semiconductor chip areas spaced apart from each other by one or more second scribe areas therebetween, each of the plurality of second semiconductor chip areas having a second semiconductor device disposed on the active surface of the second semiconductor substrate, the second semiconductor device being of the same type as the first semiconductor device. The third device layer may include an upper semiconductor chip on the second device layer and electrically connected to the plurality of second through electrodes. A plurality of device bond pads may pass through the first and second blanket insulating layers and electrically connect the first device layer to the second device layer.
According to an example embodiment, a semiconductor package includes: a first semiconductor substrate having an active surface and including a plurality of scribe line regions and a plurality of first semiconductor chip regions spaced apart from each other by corresponding ones of the plurality of scribe line regions therebetween, each of the plurality of first semiconductor chip regions having at least one first semiconductor device disposed on the active surface of the first semiconductor substrate; a plurality of first through electrodes located in the plurality of first semiconductor chip regions and penetrating the first semiconductor substrate; a first cover insulating layer covering an active surface of the first semiconductor substrate; a plurality of lower semiconductor chips located on the first semiconductor substrate and respectively corresponding to the plurality of first semiconductor chip regions, each of the plurality of lower semiconductor chips including a second semiconductor substrate having an active surface on which a second semiconductor device is located, the second semiconductor substrate including a plurality of second through electrodes passing therethrough and a second cover insulating layer covering the active surface of the second semiconductor substrate and contacting the first cover insulating layer; a plurality of device bonding pads penetrating the first and second cover insulating layers and electrically connecting the plurality of first through electrodes to the plurality of second through electrodes; and an upper semiconductor chip including a third semiconductor device and vertically overlapped with at least two of the plurality of lower semiconductor chips and electrically connected to the plurality of second through electrodes.
Drawings
Example embodiments of the present inventive concept will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
fig. 1A to 1I are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment.
Fig. 2 is a cross-sectional view of a semiconductor package according to an example embodiment.
Fig. 3A to 3C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment.
Fig. 4 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 3A through 3C according to an example embodiment.
Fig. 5A to 5D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment.
Fig. 6 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 5A through 5D according to an example embodiment.
Fig. 7A to 7C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment.
Fig. 8 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 7A through 7C according to an example embodiment.
Fig. 9A to 9C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment.
Fig. 10 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 9A through 9C according to an example embodiment.
Fig. 11A to 11E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment.
Fig. 12 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 11A through 11E according to an example embodiment.
Fig. 13A and 13B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment.
Fig. 14 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 13A-13B, according to an example embodiment.
Fig. 15A and 15B are cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to an example embodiment.
Fig. 16 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 15A and 15B, according to an example embodiment.
Fig. 17A and 17B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment.
Fig. 18 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 17A and 17B, according to an example embodiment.
Fig. 19A to 19C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment.
Fig. 20 and 21 are plan views illustrating layouts of a plurality of semiconductor chips of a semiconductor package according to some example embodiments.
Fig. 22(a) to 24(d) are cross-sectional views for conceptually describing processes of forming a device bonding pad, a chip bonding pad, and an additional bonding pad according to a method of manufacturing a semiconductor package according to an embodiment.
Description of the reference numerals
1. 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 2 a: a semiconductor package;
10: a carrier substrate;
20: adhering a film;
100: a first semiconductor substrate;
110: a first semiconductor device;
120: a wiring structure;
130: a device bond pad;
132: a first internal connection pad;
134: a second internal connection pad;
135. 135 d: an additional bond pad;
136. 136 d: a first additional connection pad;
138. 138 d: a second additional connection pad;
142: a first cover insulating layer;
144: a second cover insulating layer;
150: a through electrode;
152. 152 d: an additional through electrode;
160: an upper connection pad;
162. 162 d: an additional upper connection pad;
170: a third cover insulating layer;
180. 180 f: penetrating a plastic hole;
190. 190e, 190f, 190 h: filling the molded member;
195. 195 f: a through hole;
200: a second semiconductor substrate;
210: a second semiconductor device;
250: a chip connection terminal;
252. 252d, 252e, 252 f: an additional chip connection terminal; 260. 260 a: a chip connection pad;
262. 262 d: an additional chip connection pad;
265: a chip bonding pad;
270: the chip covers the insulating layer;
300. 300 g: a molded member;
510. 510c, 510 d: rewiring the conductive pattern;
520. 520c, 520 d: rewiring the via pattern;
530: rewiring the insulating layer;
550: an external connection terminal;
552. 552 d: an additional external connection terminal;
CR, CR-1, CR-2: a semiconductor chip region;
DC: a lower semiconductor chip;
DL1, DL1c, DL1d, DL1e, DL1 h: a first device layer;
DL2, DL2a, DL2b, DL2c, DL2d, DL2e, DL2f, DL2 g: a second device layer;
DL3, DL3a, DL3c, DL3d, DL3e, DL3 f: a third device layer;
IR, IR-2: an intermediary region;
RS and RSh: a recess space;
RDS, RDSc, RDSd, RDSe: a rewiring structure;
SL, SLd, SL-1, SL-2: a scribing region;
SLR: a residual scribing region;
UC, UCa, UCc, UCd, UC-1 and UC-2: an upper semiconductor chip;
w1: a first width;
w2: a second width;
WF1, WF1c, WF1 d: a first wafer;
WF2, WF2c, WF2 d: a second wafer.
Detailed Description
Fig. 1A to 1I are cross-sectional views sequentially showing a method of manufacturing a semiconductor package 1 according to an example embodiment. Fig. 2 is a cross-sectional view of a semiconductor package 1 according to an example embodiment.
Referring to fig. 1A, a first wafer WF1 and a second wafer WF2 are prepared. Each of the first and second wafers WF1 and WF2 may include a plurality of semiconductor chip regions CR divided by scribe lines SL. The plurality of semiconductor chip regions CR refer to portions separated from the first wafer WF1 or the second wafer WF2 by a sawing process performed along the scribe line region SL, and may operate as individual semiconductor chips.
In some example embodiments, the first wafer WF1 and the second wafer WF2 may be fabricated by using the same or substantially similar processes. Therefore, elements other than elements to be distinguished from each other or different elements among the elements of the first and second wafers WF1 and WF2 may be denoted by the same reference numerals.
Each of the first and second wafers WF1 and WF2 may include a first semiconductor substrate 100 including a plurality of semiconductor chip regions CR and scribe line regions SL. The first semiconductor device 110, the wiring structure 120, the plurality of first internal connection pads 132, the first cover insulating layer 142, and the plurality of through electrodes 150 may be located in each of the plurality of semiconductor chip regions CR of the first wafer WF 1. The first semiconductor device 110, the wiring structure 120, the plurality of second internal connection pads 134, the second cover insulating layer 144, and the plurality of through electrodes 150 may be located in each of the plurality of semiconductor chip regions CR of the second wafer WF 2.
The first semiconductor substrate 100 may include a semiconductor such as silicon (Si) or germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The first semiconductor substrate 100 may have an active surface and a passive surface opposite the active surface. For example, the first semiconductor device 110 and the wiring structure 120 may be located on an active surface of the first semiconductor substrate 100.
The first semiconductor device 110 may be, for example, a memory device. In some example embodiments, the first semiconductor device 110 may be a High Bandwidth Memory (HBM) Dynamic Random Access Memory (DRAM) device. The first semiconductor devices 110 of the plurality of semiconductor chip regions CR of the first and second wafers WF1 and WF2 may be the same type of semiconductor chips.
The wiring structure 120 may be electrically connected to the first semiconductor device 110 and/or the through electrode 150. The wiring structure 120 may include at least one metal wiring layer and at least one via plug connected to the at least one metal wiring layer.
The first and second cover insulating layers 142 and 144 may cover sidewalls of the plurality of first and second internal connection pads 132 and 134, respectively, and may not cover and may expose top surfaces of the plurality of first and second internal connection pads 132 and 134, respectively. The first and second cover insulating layers 142 and 144 may cover the first semiconductor substrate 100 even in the scribe line region SL of the first wafer WF1 and the scribe line region SL of the second wafer WF 2. Each of the first and second capping insulating layers 142 and 144 may be formed of SiO, SiN, SiCN, SiCO, or a polymer material. Examples of the polymer material may include benzocyclobutene (BCB), Polyimide (PI), Polybenzoxazole (PBO), silicone, acrylate, and epoxy.
In some example embodiments, after the plurality of first and second internal connection pads 132 and 134 are formed, the first and second cover insulating layers 142 and 144 may be formed. In other example embodiments, after the first and second cover insulating layers 142 and 144 having a plurality of holes corresponding to the plurality of first and second internal connection pads 132 and 134 are formed, the plurality of first and second internal connection pads 132 and 134 filling the plurality of holes may be formed. Each of the plurality of first and second internal connection pads 132 and 134 may be formed of a material including, for example, copper (Cu).
In some example embodiments, the top surfaces of the plurality of first internal connection pads 132, the first capping insulating layer 142, the plurality of second internal connection pads 134, and the second capping insulating layer 144 may be on the same plane (e.g., may be coplanar). In other example embodiments, one of the first or second internal connection pads 132 or 134 may protrude from a corresponding one of the top surface of the first or second insulating cover layer 142 or 144, and the other of the first or second internal connection pads 132 or 134 may be recessed from a corresponding one of the top surface of the first or second insulating cover layer 142 or 144. The width of the plurality of first internal connection pads 132 and the width of the plurality of second internal connection pads 134 may be the same in some example embodiments, and may be different in other example embodiments.
The through electrode 150 may have a first end connected to the wiring structure 120 and a second end extending into the first semiconductor substrate 100. The through electrode 150 may have at least a part having a columnar shape. The through electrode 150 may include a barrier film formed on a surface of the member having the pillar shape and a buried conductive layer filling the barrier film, and an insulating film may be located between the first semiconductor substrate 100 and the through electrode 150.
Referring to fig. 1B, the second wafer WF2 is attached to the first wafer WF1 such that the first and second cover insulating layers 142 and 144 contact each other, and the plurality of first and second internal connection pads 132 and 134 correspond to each other. The first and second cover insulating layers 142 and 144 may be adhered to each other by applying heat and/or pressure in the process of attaching the second wafer WF2 to the first wafer WF 1. For example, heat at a first temperature may be applied in the process of attaching the second wafer WF2 to the first wafer WF 1.
Referring to fig. 1B and 1C, the plurality of first internal connection pads 132 and the plurality of second internal connection pads 134 may be bonded to correspond to each other by applying heat of a second temperature higher than the first temperature to obtain the plurality of device bonding pads 130. Corresponding ones of the plurality of first and second internal connection pads 132 and 134 may expand into contact with each other due to heat, and then metal atoms may be integrated through diffusion, thereby forming a plurality of device bonding pads 130.
Referring to fig. 1D, a portion of the first semiconductor substrate 100 of the second wafer WF2 is removed to expose the through electrode 150 of the second wafer WF 2. In some example embodiments, after removing a portion of the edge of the first semiconductor substrate 100 of the second wafer WF2, an upper portion of the first semiconductor substrate 100 of the second wafer WF2 may be removed to expose the through electrode 150 of the second wafer WF 2.
Referring to fig. 1E, a plurality of upper connection pads 160 electrically connected to respective ones of the plurality of through electrodes 150 are formed on the first semiconductor substrate 100 of the second wafer WF 2. In some example embodiments, a protective insulating layer (not shown) may be additionally formed, covering the top surface of the first semiconductor substrate 100 of the second wafer WF2 and exposing the plurality of upper connection pads 160. Although the plurality of upper connection pads 160 are directly connected with the plurality of through electrodes 150 in fig. 1E, example embodiments are not limited thereto. In some example embodiments, the plurality of upper connection pads 160 and the plurality of through electrodes 150 may be electrically connected to each other via a conductive rewiring pattern (not shown).
Referring to fig. 1F, an upper semiconductor chip UC is attached to the second wafer WF2, the upper semiconductor chip UC including a plurality of chip connection pads 260 electrically connected to a plurality of upper connection pads 160, respectively. One upper semiconductor chip UC may be attached to the second wafer WF2 to correspond to the at least two semiconductor chip regions CR of each of the first wafer WF1 and the second wafer WF 2. That is, one upper semiconductor chip UC may correspond to at least four semiconductor chip regions CR of the first wafer WF1 and the second wafer WF 2.
Each upper semiconductor chip UC may include a second semiconductor substrate 200, a second semiconductor device 210, and a plurality of chip attach pads 260. The second semiconductor substrate 200 may include a semiconductor or a compound semiconductor. The second semiconductor substrate 200 may have an active surface and a passive surface opposite to the active surface. For example, the second semiconductor device 210 and the plurality of chip connection pads 260 may be located on the active surface of the second semiconductor substrate 200.
The second semiconductor device 210 may be, for example, a Central Processing Unit (CPU) chip, a Graphics Processing Unit (GPU) chip, or an Application Processor (AP) chip.
The plurality of chip connection terminals 250 may be located between the plurality of upper connection pads 160 and corresponding chip connection pads of the plurality of chip connection pads 260. The plurality of chip connection terminals 250 may be, for example, bumps or solder balls.
A molding member 300 surrounding the upper semiconductor chip UC is formed on the second wafer WF 2. The molding member 300 may be formed of, for example, Epoxy Molding Compound (EMC). The molding member 300 may surround the top surface of the second wafer WF2 and the side surfaces of the upper semiconductor chip UC. In some example embodiments, the molding member 300 may not cover and may expose the top surface of the upper semiconductor chip UC.
Referring to fig. 1G, after inverting (e.g., flipping) the resulting structure of fig. 1F such that the first wafer WF1 is located above (e.g., over) the second wafer WF2, a portion of the first semiconductor substrate 100 of the first wafer WF1 is removed to expose the through-electrodes 150 of the first wafer WF 1. In some example embodiments, after removing a portion of the edge of the first semiconductor substrate 100 of the first wafer WF1, an upper portion of the first semiconductor substrate 100 may be removed to expose the through electrode 150 of the first wafer WF 1.
Referring to fig. 1H, the re-wiring structure RDS is formed on the first chip WF 1. The rerouting structure RDS may include a plurality of rerouting insulating layers 530, a plurality of rerouting conductive patterns 510 on at least one of top and bottom surfaces of the plurality of rerouting insulating layers 530, and a plurality of rerouting via patterns 520 respectively passing through at least one of the plurality of rerouting insulating layers 530 and connected to corresponding one or more of the plurality of rerouting conductive patterns 510. Each of the plurality of re-wiring conductive patterns 510 and the plurality of re-wiring via patterns 520 may include a seed layer in contact with the re-wiring insulating layer 530 and a conductive material layer on the seed layer.
Each of the plurality of re-wiring conductive patterns 510 and the plurality of re-wiring via patterns 520 may include, but is not limited to, a metal alloy, or a metal nitride. Each of the plurality of re-wiring insulating layers 530 may include, for example, an organic compound. In some example embodiments, each of the plurality of re-wiring insulating layers 530 may include an organic polymer material (e.g., photosensitive polyimide (PSPI)).
The re-wiring conductive pattern 510 and the re-wiring via pattern 520 may be electrically connected to the through electrode 150 of the first wafer WF 1. A plurality of external connection terminals 550, which are in contact with the rewiring conductive pattern 510 and electrically connected to the plurality of through electrodes 150 of the first wafer WF1, may be attached to the rewiring structure RDS.
In some example embodiments, a plurality of lower connection pads (not shown) electrically connected to the plurality of through electrodes 150 and/or a protective insulating layer (not shown) covering the top surface of the first semiconductor substrate 100 and exposing the plurality of lower connection pads may be formed on the first semiconductor substrate 100 of the first wafer WF1 before the re-wiring structure RDS is formed. The plurality of lower connection pads may be formed in the same or substantially similar manner as used to form the plurality of upper connection pads 160. In other example embodiments, when some of the plurality of re-wiring conductive patterns 510 and some of the plurality of re-wiring insulating layers 530 perform the functions of the plurality of lower connection pads and the protective insulating layer, the plurality of lower connection pads and the protective insulating layer may not be additionally formed.
Referring to fig. 1H and 1I, a plurality of semiconductor packages 1 spaced apart from each other are formed by dividing the re-wiring structure RDS, the first wafer WF1, the second wafer WF2, and the molding member 300 along the scribe line region SL which does not vertically overlap the upper semiconductor chip UC. In each semiconductor package 1, a rewiring structure RDS, a first device layer DL1 (which is a portion of the first wafer WF1 spaced apart by dicing to have at least two semiconductor chip regions CR), a second device layer DL2 (which is a portion of the second wafer WF2 spaced apart by dicing to have at least two semiconductor chip regions CR), and a third device layer DL3 (which includes an upper semiconductor chip UC) may be stacked in this order.
Referring to fig. 2, in the semiconductor package 1, a re-wiring structure RDS, a first device layer DL1 including at least two semiconductor chip regions CR, a second device layer DL2 including at least two semiconductor chip regions CR, and a third device layer DL3 including an upper semiconductor chip UC may be sequentially stacked. Corresponding semiconductor chip regions among the at least two semiconductor chip regions CR of the first device layer DL1 and the at least two semiconductor chip regions CR of the second device layer DL2 may vertically overlap each other.
The first device layer DL1 may include a first semiconductor substrate 100, a first semiconductor device 110, a wiring structure 120, a plurality of through electrodes 150 penetrating the first semiconductor substrate 100, and a first cover insulating layer 142. The second device layer DL2 may include a first semiconductor substrate 100, a first semiconductor device 110, a wiring structure 120, a plurality of through electrodes 150 penetrating the first semiconductor substrate 100, and a second cover insulating layer 144. The second device layer DL2 may be positioned on the first device layer DL1 such that the first and second cover insulating layers 142 and 144 are in contact with each other. The device bonding pads 130 may pass through the first and second cover insulating layers 142 and 144 and may electrically connect the wiring structure 120 of the first device layer DL1 to the wiring structure 120 of the second device layer DL 2. Accordingly, the device bonding pads 130 may electrically connect the through electrodes 150 of the first device layer DL1 to the through electrodes 150 of the second device layer DL 2. A plurality of upper connection pads 160 electrically connected to the plurality of through electrodes 150 of the second device layer DL2, respectively, may be positioned on the second device layer DL 2. At least some of the plurality of through-electrodes 150 of each of the first and second device layers DL1 and DL2 may be electrically connected to the first semiconductor device 110 of each of the first and second device layers DL1 and DL 2. In some example embodiments, at least some of the plurality of through electrodes 150 of each of the first and second device layers DL1 and DL2 may be used only for electrical connection with the second semiconductor device 210.
Each of the first and second device layers DL1 and DL2 may include a scribe line region SL that separates at least two semiconductor chip regions CR (in each of which the first semiconductor device 110 is positioned) and may include a residual scribe line region SLR that surrounds the at least two semiconductor chip regions CR at an edge of each of the first and second device layers DL1 and DL 2.
In the process of forming the plurality of semiconductor packages 1 spaced apart from each other by dicing the re-wiring structure RDS, the first wafer WF1, the second wafer WF2, and the molding member 300 as described with reference to fig. 1H and 1I, the residual scribe region SLR refers to a portion of the scribe region SL remaining after dicing.
For example, when the wafer is cut along the scribe line region into a plurality of semiconductor chips spaced apart from each other, only a part of the scribe line region may be left along the edge of each semiconductor chip as the residual scribe line region SLR.
However, in the semiconductor package 1 according to example embodiments, since each of the first and second device layers DL1 and DL2 includes at least two semiconductor chip regions CR, an unslit scribe region SL may be located between the at least two semiconductor chip regions CR, and a diced residual scribe region SLR may be located at an edge of each of the first and second device layers DL1 and DL 2. The first width W1, which is the width of the scribe region SL of each of the first and second device layers DL1 and DL2, may be greater than the second width W2, which is the width of each of the sliced residual scribe regions SLR. In some example embodiments, the first width W1 may be greater than twice the second width W2.
The rerouting structure RDS may include a plurality of rerouting insulating layers 530, a plurality of rerouting conductive patterns 510 on at least one of top and bottom surfaces of the plurality of rerouting insulating layers 530, and a plurality of rerouting via patterns 520 respectively passing through at least one of the plurality of rerouting insulating layers 530 and connected to corresponding one or more of the plurality of rerouting conductive patterns 510. The re-routing conductive pattern 510 and the re-routing via pattern 520 may be electrically connected to the through electrode 150 of the first device layer DL 1. The external connection terminal 550 electrically connected to the rerouting conductive pattern 510 may be attached to the rerouting structure RDS facing the first device layer DL 1. The external connection terminal 550 may be attached to a bottom surface of the redistribution structure RDS, and the first device layer DL1 may be located on a top surface of the redistribution structure RDS.
The third device layer DL3 includes an upper semiconductor chip UC that includes a plurality of chip connection pads 260 electrically connected to a plurality of upper connection pads 160. The upper semiconductor chip UC may vertically overlap at least two semiconductor chip regions CR of the first and second device layers DL1 and DL 2. That is, the upper semiconductor chip UC may correspond to at least four semiconductor chip regions CR of the first and second device layers DL1 and DL 2. The plurality of chip connection terminals 250 may be located between the plurality of upper connection pads 160 and corresponding chip connection pads of the plurality of chip connection pads 260.
The molding member 300 surrounding the upper semiconductor chip UC may be located on the second device layer DL 2. The molding member 300 may surround the top surface of the second device layer DL2 and the side surfaces of the upper semiconductor chip UC. In some example embodiments, the molding member 300 may not cover and may expose the top surface of the upper semiconductor chip UC. In some example embodiments, the top surface of the molding member 300 and the top surface of the upper semiconductor chip UC may be on the same plane (e.g., may be coplanar).
In some example embodiments, heat dissipation means (not shown) may be attached to the top surface of the upper semiconductor chip UC. A Thermal Interface Material (TIM) layer may be located between the top surface of the upper semiconductor chip UC and the heat dissipation member. In some example embodiments, electromagnetic interference (EMI) shielding layers (not shown) may be formed on the side and top surfaces of the semiconductor package 1.
In the semiconductor package 1 according to the example embodiment of the inventive concept, the active surfaces of the first semiconductor substrate 100 of the first and second device layers DL1 and DL2 are adhered to each other via face-to-face bonding, and the third device layer DL3 including the upper semiconductor chip UC is located on the first and second device layers DL1 and DL 2. Also, in each of the first and second device layers DL1 and DL2, at least two semiconductor chip regions CR respectively including the first semiconductor device 110 may be horizontally positioned, and an upper semiconductor chip UC including the second semiconductor device 210 different from the first semiconductor device 110 may be positioned above the at least two semiconductor chip regions CR of each of the first and second device layers DL1 and DL 2.
In the semiconductor package 1 according to the example embodiment of the inventive concept, since the upper semiconductor chip UC is attached to the second device layer DL2 having a larger area than the upper semiconductor chip UC, a relatively fine pitch may be achieved without using an additional interposer, thereby reducing the manufacturing cost of the semiconductor package. Also, in the semiconductor package 1 according to the example embodiment of the inventive concept, since the re-wiring structure RDS to which the external connection terminals 550 are connected is formed on the first device layer DL1 having a larger area than the upper semiconductor chip UC, it is possible to realize a relatively small external size without using an additional printed circuit board.
In the present invention, the semiconductor chip region CR, the scribe line region SL, the first semiconductor substrate 100, the first semiconductor device 110, and the through electrode 150 of the first device layer DL1 may be referred to as a first semiconductor chip region, a first scribe line region, a first semiconductor substrate, a first semiconductor device, and a first through electrode, respectively. The semiconductor chip region CR, the scribe line region SL, the first semiconductor substrate 100, the first semiconductor device 110, and the through electrode 150 of the second device layer DL2 may be referred to as a second semiconductor chip region, a second scribe line region, a second semiconductor substrate, a second semiconductor device, and a second through electrode, respectively. The second semiconductor substrate 200 and the second semiconductor device 210 of the third device layer DL3 may be referred to as a third semiconductor substrate and a third semiconductor device, respectively.
Fig. 3A to 3C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment. Fig. 4 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 3A to 3C according to an example embodiment, and the same description as that made with reference to fig. 1A to 2 will not be given. In detail, fig. 3A illustrates steps subsequent to fig. 1D.
Referring to fig. 3A, a plurality of upper connection pads 160 electrically connected to the plurality of through electrodes 150, respectively, and a third cover insulating layer 170 covering sidewalls of the plurality of upper connection pads 160 and not covering top surfaces of the plurality of upper connection pads 160 are formed on the first semiconductor substrate 100 of the second wafer WF 2. The plurality of upper connection pads 160 and the third insulating cover layer 170 may be formed by using the same or substantially similar method as that used for forming the first internal connection pads 132 and the first insulating cover layer 142 or the plurality of second internal connection pads 134 and the second insulating cover layer 144.
Referring to fig. 3B, an upper semiconductor chip UCa including a plurality of chip connection pads 260a is attached to the second wafer WF 2. The upper semiconductor chip UCa may be attached to the second wafer WF2 such that the plurality of chip connection pads 260a correspond to the plurality of upper connection pads 160. The upper semiconductor chip UCa may include a second semiconductor substrate 200, a second semiconductor device 210, a plurality of chip connection pads 260a, and a chip cover insulating layer 270. The chip cover insulating layer 270 may cover sidewalls of the plurality of chip connection pads 260a and may not cover top surfaces of the plurality of chip connection pads 260a on the second semiconductor substrate 200.
The third insulating cover layer 170 and the chip insulating cover layer 270 may be adhered to each other by applying heat and/or pressure in a process of attaching the upper semiconductor chips UCa to the second wafer WF 2. For example, heat at a third temperature may be applied in the process of attaching the upper semiconductor chips UCa to the second wafer WF 2. The molding member 300 surrounding the upper semiconductor chip UCa is formed on the second wafer WF 2.
Referring to fig. 3B and 3C, a plurality of chip bonding pads 265 obtained by bonding the plurality of upper connection pads 160 with corresponding chip connection pads of the plurality of chip connection pads 260a are formed by applying heat of a fourth temperature higher than the third temperature. Corresponding ones of the plurality of upper connection pads 160 and the plurality of chip connection pads 260a may expand into contact with each other due to heat, and then metal atoms from the corresponding ones of the plurality of upper connection pads 160 and the plurality of chip connection pads 260a are diffused to be unified, thereby forming a plurality of chip bonding pads 265.
Referring to fig. 4, a semiconductor package 1a is formed by performing the above processes of fig. 1G to 1I on the resultant structure of fig. 3C. In the semiconductor package 1a, the re-wiring structure RDS, the first device layer DL1 including at least two semiconductor chip regions CR, the second device layer DL2 including at least two semiconductor chip regions CR, and the third device layer DL3a including the upper semiconductor chip UCa may be stacked in order.
The third device layer DL3a may be positioned on the second device layer DL2 such that the third insulating cover layer 170 and the chip insulating cover layer 270 contact each other. The chip bonding pad 265 may pass through the third insulating cover layer 170 and the chip insulating cover layer 270, and may electrically connect the through electrode 150 of the second device layer DL2 to the second semiconductor device 210 of the upper semiconductor chip UCa.
Fig. 5A to 5D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment. Fig. 6 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 5A through 5D according to an example embodiment, and thus the same description as that made with reference to fig. 1A through 2 will not be given. In detail, fig. 5A illustrates steps subsequent to fig. 1A.
Referring to fig. 1A and 5A, the second wafer WF2 may be diced along the scribe line regions SL to separate the plurality of semiconductor chip regions CR into a plurality of lower semiconductor chips DC. Although the lower semiconductor chip DC does not include the scribe line region SL in fig. 5A, example embodiments are not limited thereto, and the lower semiconductor chip DC may further include a portion of the scribe line region SL, such as the residual scribe line region SLR of fig. 2.
A plurality of lower semiconductor chips DC are attached to the first wafer WF1 to correspond to the plurality of semiconductor chip regions CR of the first wafer WF1, respectively. Each of the lower semiconductor chips DC may include a first semiconductor substrate 100, a first semiconductor device 110, a wiring structure 120, a plurality of first internal connection pads 132, a first capping insulating layer 142, and a plurality of through electrodes 150.
The plurality of lower semiconductor chips DC may be attached to the first wafer WF1 such that the first and second cover insulating layers 142 and 144 contact each other and the plurality of first and second internal connection pads 132 and 134 correspond to each other. The first and second cover insulating layers 142 and 144 may be adhered to each other by applying heat and/or pressure in the process of attaching the plurality of lower semiconductor chips DC to the first wafer WF 1.
Referring to fig. 5A and 5B, a plurality of device bonding pads 130 obtained by bonding corresponding second internal connection pads of a plurality of first internal connection pads 132 and a plurality of second internal connection pads 134 are formed.
Referring to fig. 5C, filling molding members (190) filling spaces between and covering the plurality of lower semiconductor chips DC are formed on the first wafer WF 1. The filling mold member 190 may include EMC, for example.
Referring to fig. 5D, a portion of the first semiconductor substrate 100 of the second wafer WF2 and a portion of the filling mold member 190 are removed in the plurality of lower semiconductor chips DC to expose the through electrodes 150 of the plurality of lower semiconductor chips DC.
Referring to fig. 6, a semiconductor package 1b is formed by performing the above processes of fig. 1E to 1I on the resultant structure of fig. 5D. In the semiconductor package 1b, a re-wiring structure RDS, a first device layer DL1 (the first device layer including at least two semiconductor chip regions CR spaced apart from each other by a scribe region SL), a second device layer DL2b (the second device layer including at least two lower semiconductor chips DC spaced apart from each other by a filling mold member 190 therebetween), and a third device layer DL3 (the third device layer including an upper semiconductor chip UC) may be sequentially stacked.
Unlike the semiconductor package 1 of fig. 2 in which the second device layer DL2 is formed on the first device layer DL1 by using a wafer-to-wafer (W2W) bonding method, the semiconductor package 1b of fig. 6 may form the second device layer DL2b on the first device layer DL1 by using a chip-to-wafer/die-to-wafer (C2W/D2W) bonding method.
Fig. 7A to 7C are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment. Fig. 8 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 7A to 7C according to an example embodiment, and thus the same description as made with reference to fig. 1A to 2 will not be given.
Referring to FIG. 7A, a first wafer WF1c and a second wafer WF2c are prepared. Each of the first and second wafers WF1c and WF2c may include a plurality of semiconductor chip regions CR and a plurality of intervening regions IR spaced apart from each other by scribe lines SL. In each of the first and second wafers WF1c and WF2c, a plurality of intervening regions IR are located in place of some of the plurality of semiconductor chip regions CR of each of the first and second wafers WF1 and WF2 of fig. 1A, and the emphasis of the description will be placed on the plurality of intervening regions IR. The number of the plurality of semiconductor chip regions CR of each of the first and second wafers WF1c and WF2c may be less than the number of the plurality of semiconductor chip regions CR of each of the first and second wafers WF1 and WF2 of fig. 1A.
The size (area) of each of the intervening regions IR may be the same as the size (area) of each of the semiconductor chip regions CR in some example embodiments, and may be smaller than the size (area) of the semiconductor chip regions CR in other example embodiments. Accordingly, the sum of the number of the plurality of semiconductor chip regions CR of each of the first and second wafers WF1c and WF2c and the number of the plurality of intervening regions IR may be the same as the total number of the plurality of semiconductor chip regions CR of each of the first and second wafers WF1 and WF2 of fig. 1A in some example embodiments, and may be greater than the total number of the plurality of semiconductor chip regions CR of each of the first and second wafers WF1 and WF2 of fig. 1A in other example embodiments.
Each of the intermediate areas IR of the first wafer WF1c includes a plurality of first additional connection pads 136 and a plurality of additional through electrodes 152 connected to the plurality of first additional connection pads 136, and each of the intermediate areas IR of the second wafer WF2c includes a plurality of second additional connection pads 138 and a plurality of additional through electrodes 152 connected to the plurality of second additional connection pads 138. The first and second cover insulating layers 142 and 144 may cover sidewalls of the plurality of first and second additional connection pads 136 and 138, and may not cover and may expose top surfaces of the plurality of first and second additional connection pads 136 and 138 in the intermediate area IR of the first and second wafers WF1c and WF2 c.
Although the first and second additional connection pads 136 and 138 are thicker than the first and second internal connection pads 132 and 134 for convenience of explanation in fig. 7A, example embodiments are not limited thereto. For example, the thickness of the first and second additional connection pads 136 and 138 may be the same as the thickness of the first and second internal connection pads 132 and 134. The wiring structure 120 may be located between the first additional connection pad 136 and the additional through electrode 152 and between the second additional connection pad 138 and the additional through electrode 152.
Referring to fig. 7B, the second wafer WF2c is attached to the first wafer WF1c such that the first and second cover insulating layers 142 and 144 are in contact with each other, the plurality of first and second internal connection pads 132 and 134 correspond to each other and the plurality of first and second additional connection pads 136 and 138 correspond to each other.
Referring to fig. 7B and 7C, a plurality of device bonding pads 130 obtained by bonding corresponding ones of a plurality of first internal connection pads 132 and a plurality of second internal connection pads 134 and a plurality of additional bonding pads 135 obtained by bonding corresponding ones of a plurality of first additional connection pads 136 and a plurality of second additional connection pads 138 to form an integrated structure by diffusion bonding are formed.
Referring to fig. 8, a semiconductor package 1C is formed by performing the same or substantially similar process as the process of fig. 1D-1I above on the resulting structure of fig. 7C. In the semiconductor package 1c, the re-wiring structure RDSc, the first device layer DL1c including at least two semiconductor chip regions CR and at least one intermediate region IR, the second device layer DL2c including at least two semiconductor chip regions CR and at least one intermediate region IR, and the third device layer DL3c including the upper semiconductor chip UCc may be stacked in order.
The first device layer DL1c may include a first semiconductor substrate 100 including at least two semiconductor chip regions CR and at least one intervening region IR, a wiring structure 120, a first cover insulating layer 142, a first semiconductor device 110 of the semiconductor chip region CR, and a plurality of through electrodes 150, and a plurality of additional through-electrodes 152 of the intermediate region IR, the second device layer DL2c may include a first semiconductor substrate 100 (which includes at least two semiconductor chip regions CR and at least one intermediate region IR), a wiring structure 120, a second capping insulating layer 144, a first semiconductor device 110 of the semiconductor chip region CR, and a plurality of through-electrodes 150, and a plurality of additional through electrodes 152 of the intermediate region IR, and a second device layer DL2c may be positioned on the first device layer DL1c such that the first and second cover insulating layers 142 and 144 contact each other. The device bonding pad 130 may pass through the first and second cover insulating layers 142 and 144 in the semiconductor chip region CR, and may electrically connect the through electrode 150 of the first device layer DL1c to the through electrode 150 of the second device layer DL2 c. The additional bonding pads 135 may pass through the first and second cover insulating layers 142 and 144 in the intermediate region IR and may electrically connect the additional through electrodes 152 of the first device layer DL1c to the additional through electrodes 152 of the second device layer DL2 c.
A plurality of upper connection pads 160 electrically connected to the plurality of through electrodes 150 and a plurality of additional upper connection pads 162 electrically connected to the plurality of additional through electrodes 152 may be positioned on the second device layer DL2 c.
The upper semiconductor chip UCc may include a second semiconductor substrate 200, a second semiconductor device 210, a plurality of chip attach pads 260, and a plurality of additional chip attach pads 262. The plurality of chip connection terminals 250 may be located between the plurality of upper connection pads 160 and the plurality of chip connection pads 260 corresponding to each other, and the plurality of additional chip connection terminals 252 may be located between the plurality of additional upper connection pads 162 and the plurality of additional chip connection pads 262 corresponding to each other.
The re-wiring structure RDSc may include a plurality of re-wiring insulating layers 530, a plurality of re-wiring conductive patterns 510c on at least one of top and bottom surfaces of the plurality of re-wiring insulating layers 530, and a plurality of re-wiring via patterns 520c passing through at least one of the plurality of re-wiring insulating layers 530 and connected to the plurality of re-wiring conductive patterns 510 c.
The rerouting conductive pattern 510c and the rerouting via pattern 520c may be electrically connected to the through electrode 150 and the additional through electrode 152 of the first device layer DL1 c. To the rewiring structure RDSc, an external connection terminal 550 contacting the rewiring conductive pattern 510c and electrically connected to the plurality of through electrodes 150 of the first device layer DL1c and an additional external connection terminal 552 electrically or thermally connected to the plurality of additional through electrodes 152 may be attached.
In the semiconductor package 1c according to the example embodiment of the inventive concept, when the number of electrical paths required for the upper semiconductor chip UCc is relatively large, the intermediate region IR including the plurality of additional through electrodes 152 may be located in each of the first device layer DL1c and the second device layer DL2c, and the plurality of additional through electrodes 152 may be used as the additional electrical paths.
Alternatively, in the semiconductor package 1c according to the example embodiment of the inventive concept, when the heat generated in the upper semiconductor chip UCc is relatively large, the plurality of additional chip connection pads 262, the plurality of additional through electrodes 152, and the plurality of additional external connection terminals 552 may be used as heat transfer paths, and the heat generated in the upper semiconductor chip UCc may be discharged to the outside.
Fig. 9A to 9C are cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to an embodiment. Fig. 10 is a cross-sectional view of a semiconductor package according to an example embodiment, and the same description as that made with reference to fig. 1A to 2 and fig. 7A to 8 will not be given again in fig. 9A to 10.
Referring to fig. 9A, a first wafer WF1d and a second wafer WF2d are prepared. Each of the first and second wafers WF1d and WF2d may include a plurality of semiconductor chip areas CR divided by scribe lines SLd. The scribing region SL of each of the first and second wafers WF1 and WF2 of fig. 1A is replaced with the scribing region SLd of each of the first and second wafers WF1d and WF2d, and thus the description will be focused on the scribing region SLd.
Each of the scribe regions SLd of the first wafer WF1d includes a plurality of first additional connection pads 136d and a plurality of additional through electrodes 152d connected to the plurality of first additional connection pads 136d, and each of the scribe regions SLd of the second wafer WF2d includes a plurality of second additional connection pads 138d and a plurality of additional through electrodes 152d connected to the plurality of second additional connection pads 138 d. The first and second cover insulating layers 142 and 144 may cover side surfaces of the plurality of first and second additional connection pads 136d and 138d, and may not cover and may expose top surfaces of the plurality of first and second additional connection pads 136d and 138d in the scribe region SLd of the first and second wafers WF1d and WF2 d.
Although the first and second additional connection pads 136d and 138d are thicker than the first and second internal connection pads 132 and 134 for convenience of explanation in fig. 9A, example embodiments are not limited thereto.
Referring to fig. 9B, the second wafer WF2d is attached to the first wafer WF1d such that the first and second cover insulating layers 142 and 144 contact each other, the plurality of first and second internal connection pads 132 and 134 correspond to each other, and the plurality of first and second additional connection pads 136d and 138d correspond to each other.
Referring to fig. 9B and 9C, a plurality of device bonding pads 130 obtained by bonding a plurality of first internal connection pads 132 to corresponding second internal connection pads of a plurality of second internal connection pads 134 and a plurality of additional bonding pads 135d obtained by bonding a plurality of first additional connection pads 136d and a plurality of second additional connection pads 138d are formed.
Referring to fig. 10, a semiconductor package 1D is formed by performing the same or substantially similar process as the process of fig. 1D-1I above on the resulting structure of fig. 9C. In the semiconductor package 1d, the re-wiring structure RDSd, the first device layer DL1d including at least two semiconductor chip regions CR divided by the scribe line region SLd, the second device layer DL2d including at least two semiconductor chip regions CR divided by the scribe line region SLd, and the third device layer DLdc including the upper semiconductor chip UCd may be sequentially stacked.
The first device layer DL1d may include a first semiconductor substrate 100 including at least two semiconductor chip regions CR divided by a scribe line region SLd, a wiring structure 120, a first cover insulating layer 142, a first semiconductor device 110 of the semiconductor chip region CR, and a plurality of through electrodes 150, and a plurality of additional through-electrodes 152d of the scribe line region SLd, the second device layer DL2d may include a first semiconductor substrate 100 including at least two semiconductor chip regions CR divided by the scribe line region SLd, a wiring structure 120, a second cover insulating layer 144, a first semiconductor device 110 of the semiconductor chip region CR, and a plurality of through-electrodes 150, and a plurality of additional through electrodes 152d of the scribing region SLd, and the second device layer DL2d may be positioned on the first device layer DL1d such that the first and second cover insulating layers 142 and 144 contact each other. The device bonding pads 130 may pass through the first and second cover insulating layers 142 and 144 in the semiconductor chip region CR, and may electrically connect the through electrodes 150 of the first device layer DL1d to the through electrodes 150 of the second device layer DL2 d. The additional bonding pad 135d may pass through the first and second cover insulating layers 142 and 144 in the scribe line region SLd and may electrically connect the additional through electrode 152d of the first device layer DL1d to the additional through electrode 152d of the second device layer DL2 d.
A plurality of upper connection pads 160 electrically connected to the plurality of through electrodes 150 and a plurality of additional upper connection pads 162d electrically connected to the plurality of additional through electrodes 152d may be positioned on the second device layer DL2 d.
The upper semiconductor chip UCd may include a second semiconductor substrate 200, a second semiconductor device 210, a plurality of chip attach pads 260, and a plurality of additional chip attach pads 262 d. The plurality of chip connection terminals 250 may be located between the plurality of upper connection pads 160 and the plurality of chip connection pads 260 corresponding to each other, and the plurality of additional chip connection terminals 252d may be located between the plurality of additional upper connection pads 162d and the plurality of additional chip connection pads 262d corresponding to each other.
The rerouting structure RDSd may include a plurality of rerouting insulating layers 530, a plurality of rerouting conductive patterns 510d on at least one of top and bottom surfaces of the plurality of rerouting insulating layers 530, and a plurality of rerouting via patterns 520c passing through at least one of the plurality of rerouting insulating layers 530 and connected to the plurality of rerouting conductive patterns 510 d. The rerouting conductive pattern 510d and the rerouting via pattern 520d may be electrically connected to the through electrode 150 and the additional through electrode 152 of the first device layer DL1 d. To the redistribution structure RDSd, an external connection terminal 550 contacting the redistribution conductive pattern 510d and electrically connected to the plurality of through electrodes 150 of the first device layer DL1d and an additional external connection terminal 552d electrically or thermally connected to the plurality of additional through electrodes 152d may be attached.
Although only one additional through electrode 152d, one additional upper connection pad 162d, one additional chip connection terminal 252d, one additional chip connection pad 262d, and one additional external connection terminal 552d for each of the one additional bonding pad 135d, the first device layer DL1d, and the second device layer DL2d are illustrated in fig. 10, example embodiments are not limited thereto, and a plurality of elements may be located between the two semiconductor chip regions CR in a direction in which the scribe region SLd extends or in a direction between the two semiconductor chip regions CR.
Fig. 11A to 11E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment. Fig. 12 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 11A to 11E according to an example embodiment, and the same description as that made with reference to fig. 5A to 6 and 7A to 8 will not be given.
Referring to fig. 11A, a plurality of lower semiconductor chips DC are attached to the first wafer WF1c to correspond to the plurality of semiconductor chip regions CR of the first wafer WF1 c. The first wafer WF1c and the lower semiconductor chip DC are substantially the same as the first wafer WF1c of fig. 7A and the lower semiconductor chip DC of fig. 5A, and thus a detailed explanation thereof will not be given.
Referring to fig. 11A and 11B, a plurality of device bonding pads 130 obtained by bonding a plurality of first internal connection pads 132 and a plurality of second internal connection pads 134 corresponding to each other are formed.
Referring to fig. 11C, a filling mold member 190e filling the space between the plurality of lower semiconductor chips DC and covering the plurality of lower semiconductor chips DC is formed on the first wafer WF 1C. The filling mold member 190e may be formed of EMC, for example.
Referring to fig. 11D, a portion of the first semiconductor substrate 100 and a portion of the filling mold member 190e are removed in the plurality of lower semiconductor chips DC to expose the through electrodes 150 of the plurality of lower semiconductor chips DC.
Next, a plurality of upper connection pads 160 electrically connected to the plurality of through electrodes 150, respectively, are formed on the first semiconductor substrate 100 of the plurality of lower semiconductor chips DC. After a plurality of through holes 195 through which the plurality of first additional connection pads 136 are exposed are formed in the intermediate region IR of the first wafer WF1c by further removing a portion of the filling mold member 190e, a plurality of through-mold holes (through-mold vias) 180 filling at least portions of the plurality of through holes 195 and connected to the plurality of first additional connection pads 136 are formed.
Referring to fig. 11E, the upper semiconductor chip UCc is attached to the plurality of lower semiconductor chips DC and the filling mold member 190E. The upper semiconductor chip UCc may include a second semiconductor substrate 200, a second semiconductor device 210, a plurality of chip attach pads 260, and a plurality of additional chip attach pads 262. The plurality of chip connection terminals 250 may be located between the plurality of upper connection pads 160 and the plurality of chip connection pads 260 corresponding to each other, and the plurality of additional chip connection terminals 252e may be located between the plurality of molding through holes 180 and the plurality of additional chip connection pads 262 corresponding to each other. The molding member 300 surrounding the upper semiconductor chip UCc is formed on the plurality of lower semiconductor chips DC and the filling molding member 190 e.
Referring to fig. 12, a semiconductor package 1E is formed by performing the above processes of fig. 1G to 1I on the resultant structure of fig. 11E. The second device layer DL2c of the semiconductor package 1c of fig. 8 is replaced with the second device layer DL2e of the semiconductor package 1e, and the additional chip connection terminal 252 of the third device layer DL3c of fig. 8 is replaced with the additional chip connection terminal 252e of the third device layer DL3e of the semiconductor package 1e, and thus the emphasis of the description will be placed on the differences.
In the semiconductor package 1e, a re-wiring structure RDSe, a first device layer DL1e including at least two semiconductor chip regions CR and at least one intermediate region IR, a second device layer DL2e including at least two lower semiconductor chips DC, and a third device layer DL3e including an upper semiconductor chip UCc may be sequentially stacked. The second device layer DL2e of the semiconductor package 1e includes at least two lower semiconductor chips DC (instead of the at least two semiconductor chip regions CR of the second device layer DL2c of fig. 8) and includes a filling mold member 190e (instead of the intermediate region IR) having a plurality of through holes 195 and a plurality of through-mold holes 180 formed in the plurality of through holes 195. The plurality of additional chip connection terminals 252e may be located between the plurality of molding through holes 180 and the plurality of additional chip connection pads 262, and the plurality of molding through holes 180 and the plurality of additional chip connection terminals 252e corresponding to each other may be directly connected to each other. Accordingly, the semiconductor package 1e may not include the additional upper connection pad 162 of the semiconductor package 1c of fig. 8.
Fig. 13A and 13B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment, and fig. 14 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 13A to 13B according to an example embodiment, and the same description made with reference to fig. 1A to 2, 5A to 6, and 9A to 10 will not be given.
Referring to fig. 13A, a plurality of lower semiconductor chips DC are attached to the first wafer WF1d to correspond to the plurality of semiconductor chip regions CR of the first wafer WF1 d. The first wafer WF1d and the lower semiconductor chip DC are the same as or substantially similar to the first wafer WF1d of fig. 9A and the lower semiconductor chip DC of fig. 5A, and thus a detailed explanation thereof will not be given.
Referring to fig. 13B, a plurality of device bonding pads 130 are formed by performing the above process of fig. 11B, and a plurality of upper connection pads 160 electrically connected to the plurality of through electrodes 150, respectively, are formed on the first semiconductor substrate 100 of the plurality of lower semiconductor chips DC by performing processes similar to fig. 11C and 11D. Also, a filling mold member 190f filling the spaces between the plurality of lower semiconductor chips DC and having a plurality of through holes 195f is formed on the first wafer WF1d, and a plurality of through-mold holes 180f filling at least portions of the plurality of through holes 195f and connected to the plurality of first additional connection pads 136d is formed.
Next, the upper semiconductor chip UCd is attached to the plurality of lower semiconductor chips DC and the filling mold member 190 f. The upper semiconductor chip UCd may include a second semiconductor substrate 200, a second semiconductor device 210, a plurality of chip attach pads 260, and a plurality of additional chip attach pads 262 d. The plurality of chip connection terminals 250 may be located between the plurality of upper connection pads 160 and the plurality of chip connection pads 260 corresponding to each other, and the plurality of additional chip connection terminals 252f may be located between the plurality of through-molding holes 180f and the plurality of additional chip connection pads 262d corresponding to each other. The molding member 300 surrounding the upper semiconductor chip UCd is formed on the plurality of lower semiconductor chips DC and the filling molding member 190 f.
Referring to fig. 14, a semiconductor package 1f is formed by performing the above processes of fig. 11E and fig. 1G to 1I on the resultant structure of fig. 13B. The second device layer DL2d of the semiconductor package 1d of fig. 10 is replaced with the second device layer DL2f of the semiconductor package 1f, and the additional chip connection terminal 252d of the third device layer DL3d of fig. 10 is replaced with the additional chip connection terminal 252f of the third device layer DL3f, and thus the emphasis of the description will be placed on the differences.
In the semiconductor package 1f, the re-wiring structure RDSd, the first device layer DL1d including at least two semiconductor chip regions CR divided by the scribe line region SLd, the second device layer DL2f including at least two lower semiconductor chips DC, and the third device layer DL3f including the upper semiconductor chip UCd may be sequentially stacked. The second device layer DL2f of the semiconductor package 1f includes at least two lower semiconductor chips DC (instead of the at least two semiconductor chip regions CR of the second device layer DL2d of fig. 10) and includes a filling mold member 190f (instead of the scribe line region SLd) having a plurality of through holes 195f and a plurality of through-mold holes 180f formed in the plurality of through holes 195 f. The plurality of additional chip connection terminals 252f may be located between the plurality of molding through holes 180f and the plurality of additional chip connection pads 262d, and the plurality of molding through holes 180f and the plurality of additional chip connection terminals 252f corresponding to each other may be directly connected to each other. Therefore, the semiconductor package 1f may not include the additional upper connection pad 162d of the semiconductor package 1d of fig. 10.
Fig. 15A and 15B are cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to an example embodiment, and fig. 16 is a cross-sectional view of a semiconductor package according to an example embodiment, and the same description made with reference to fig. 3A to 4 will not be given. In detail, fig. 15A shows a step subsequent to fig. 3A.
Referring to fig. 15A, a recess space (recess space) RS is formed by removing a portion of the third cover insulating layer 170 of the second wafer WF2 and an upper portion of the first semiconductor substrate 100. A portion of the third cover insulating layer 170 of the second wafer WF2 and an upper portion of the first semiconductor substrate 100 may be removed to form the recess space RS by forming a mask pattern covering the remaining portion of the third cover insulating layer 170 and the plurality of upper connection pads 160 on the second wafer WF2 and then by using the mask pattern as an etching mask. The width of the mask pattern may be equal to or greater than the width of the upper semiconductor chip UCa of fig. 15B.
Referring to fig. 15B, an upper semiconductor chip UCa including a plurality of chip connection pads 260a is attached to a second wafer WF2 including a recess space RS. The upper semiconductor chip UCa may be attached to the second wafer WF2 such that the plurality of chip connection pads 260a correspond to the plurality of upper connection pads 160. The upper semiconductor chip UCa may be attached to the second wafer WF2 to be aligned with respect to the recess space RS, and the third insulating cover layer 170 and the insulating chip cover layer 270 may be adhered to each other.
Referring to fig. 16, a plurality of chip bonding pads 265 obtained by bonding a plurality of upper connection pads 160 and a plurality of chip connection pads 260a corresponding to each other and a molding member 300g filling the recess RS in the second wafer WF2 and surrounding the upper semiconductor chip UCa are formed by performing the above process of fig. 3C on the resultant structure of fig. 15B. Next, the semiconductor package 1G is formed by performing the above processes of fig. 1G to 1I. The second device layer DL2 and the mold member 300 of the semiconductor package 1a of fig. 4 are replaced with the second device layer DL2g and the mold member 300g of the semiconductor package 1g, and thus the description will be focused on the differences.
In the semiconductor package 1g, the re-wiring structure RDS, the first device layer DL1 including at least two semiconductor chip regions CR divided by the scribe line region SL, the second device layer DL2g including at least two lower semiconductor chips DC, and the third device layer DL3a including the upper semiconductor chip UCa may be stacked in order. The first semiconductor substrate 100 of the second device layer DL2g of the semiconductor package 1g may include a recess space RS, and the recess space RS may fill the molding member 300 g. The upper semiconductor chip UCa may be attached to a protrusion defined by the recess space RS of the first semiconductor substrate 100 of the second device layer DL2 g.
Fig. 17A and 17B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment. Fig. 18 is a cross-sectional view of a semiconductor package formed by the method illustrated in fig. 17A and 17B according to an example embodiment, and the same description as made with reference to fig. 5A to 6 will not be given. In detail, fig. 17A illustrates a step before the plurality of lower semiconductor chips DC in fig. 5A are attached to the first wafer WF 1.
Referring to fig. 17A, a recess space RSh is formed in the first wafer WF1 by removing a portion of the first cover insulating layer 142 and an upper portion of the first semiconductor substrate 100. The recess space RSh may be formed by forming a mask pattern covering the remaining portion of the first cover insulating layer 142 and the plurality of first internal connection pads 132 on the first wafer WF1 and then removing a portion of the first cover insulating layer 142 and an upper portion of the first semiconductor substrate 100 by using the mask pattern as an etching mask. The width of the mask pattern may be equal to or greater than the width of each of the lower semiconductor chips DC.
Referring to fig. 17B, a plurality of lower semiconductor chips DC are attached to the first wafer WF1 including the recess spaces RSh to correspond to the plurality of semiconductor chip regions CR of the first wafer WF 1. The plurality of lower semiconductor chips DC may be attached to the first wafer WF1 such that the first and second cover insulating layers 142 and 144 are in contact with each other and the plurality of first and second internal connection pads 132 and 134 correspond to each other.
The lower semiconductor chip DC may be attached to the first wafer WF1 to be aligned with respect to the recess space RSh, and the first and second cover insulating layers 142 and 144 may be adhered to each other.
Referring to fig. 18, a semiconductor package 1h is formed by performing the above processes of fig. 5C and 5D on the resultant structure of fig. 17B. The first device layer DL1 and the filling mold member 190 of the semiconductor package 1b of fig. 6 are replaced with the first device layer DL1h and the filling mold member 190h of the semiconductor package 1h, and thus the description will be focused on the differences.
In the semiconductor package 1h, the re-wiring structure RDS, the first device layer DL1h, the second device layer DL2b, and the third device layer DL3 may be stacked in order. The first semiconductor substrate 100 of the first device layer DL1h of the semiconductor package 1h may include a recess space RSh, and the recess space RSh may be filled with the filling mold member 190 h. The lower semiconductor chip DC is attached to a protrusion defined by the recess space RSh of the first semiconductor substrate 100 of the first device layer DL1 h.
Fig. 19A to 19C are cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to an example embodiment, and the same description made with reference to fig. 1A to 2 will not be given. In detail, fig. 19A to 19C illustrate steps subsequent to fig. 1D.
Referring to fig. 19A, a re-wiring structure RDS is formed on the first wafer WF1 by performing the above process of fig. 1H on the resulting structure of fig. 1D. The rerouting structure RDS may include a plurality of rerouting insulating layers 530, a plurality of rerouting conductive patterns 510 on at least one of top and bottom surfaces of the plurality of rerouting insulating layers 530, and a plurality of rerouting via patterns 520 passing through at least one of the plurality of rerouting insulating layers 530 and connected to the plurality of rerouting conductive patterns 510. A plurality of external connection terminals 550, which are in contact with the rewiring conductive pattern 510 and electrically connected to the plurality of through electrodes 150 of the first wafer WF1, may be attached to the rewiring structure RDS.
Referring to fig. 19B, after inverting the resulting structure of fig. 19B such that the re-wiring structure RDs is facing down, the first wafer WF1 having the re-wiring structure RDS formed thereon is attached to the carrier substrate 10 with the adhesive film (adhesive film)20 therebetween. The adhesive film 20 may fill a space between the re-wiring structure RDS and the carrier substrate 10, and may surround the external connection terminal 550.
Referring to fig. 19C, a plurality of upper connection pads 160 are formed by performing the above processes of fig. 1E and 1F, and an upper semiconductor chip UC including a plurality of chip connection pads 260 electrically connected to the plurality of upper connection pads 160 is attached. The plurality of chip connection terminals 250 may be located between the plurality of upper connection pads 160 and the plurality of chip connection pads 260 corresponding to each other. A molding member 300 surrounding the upper semiconductor chip UC is formed on the second wafer WF 2. Next, the semiconductor package 1 of fig. 2 may be formed by performing the above process of fig. 1I.
Further, it will be understood by those of ordinary skill in the art that any one of the semiconductor packages 1a, 1b, 1C, 1d, 1e, 1f, 1g, and 1h of fig. 4, 6, 8, 10, 12, 14, 16, and 18 may be formed by using the above processes of fig. 19A to 19C, and thus a detailed explanation will not be given.
Fig. 20 and 21 are plan views illustrating layouts of a plurality of semiconductor chips of a semiconductor package according to some example embodiments.
Referring to fig. 20, a semiconductor package 2 may include an upper semiconductor chip UC-1 located above a plurality of semiconductor chip regions CR-1 divided by a scribe line region SL-1. Each of the plurality of semiconductor chip regions CR-1 of fig. 20 includes two stacked semiconductor chip regions, or a lower semiconductor chip stacked on the semiconductor chip regions. Although the semiconductor package 2 includes 16 semiconductor chip regions CR-1 in fig. 20, example embodiments are not limited thereto, and the semiconductor package 2 may include two or more semiconductor chip regions CR-1.
The semiconductor chip region CR-1 may be the lower semiconductor chip DC of the semiconductor chip region CR of the first device layer DL1, the first device layer DL1d or the first device layer DL1h and the second device layer DL2, the second device layer DL2a or the second device layer DL2d of fig. 2, 4, 6, 10, 14, 16 or 18 or the second device layer DL 3538 or the second device layer DL2 b. Upper semiconductor chip UC-1 may be upper semiconductor chip UC, upper semiconductor chip UCa, or upper semiconductor chip UCd of fig. 2, 4, 6, 10, 14, 16, or 18. Scribe region SL-1 may be a scribe region SL or a scribe region SLd of first device layer DL1, first device layer DL1d, or first device layer DL1h of fig. 2, 4, 6, 10, 14, 16, or 18, and a scribe region SL or a scribe region SLd of second device layer DL2, second device layer DL2a, or second device layer DL2 d.
Referring to fig. 21, a semiconductor package 2a may include a plurality of semiconductor chip regions CR-2 divided by scribe line regions SL-2 and an upper semiconductor chip UC-2 located above a plurality of intermediate regions IR-2. Each of the plurality of semiconductor chip regions CR-2 of fig. 21 includes two stacked semiconductor chip regions, or a lower semiconductor chip stacked on the semiconductor chip regions. Although the semiconductor package 2a of fig. 21 includes 16 semiconductor chip regions CR-2 and 4 intermediate regions IR-2, example embodiments are not limited thereto, and the semiconductor package 2a may include two or more semiconductor chip regions CR-1 and one or more intermediate regions IR-2.
The semiconductor chip region CR-2 may be the semiconductor chip region CR of the first device layer DL1c and the semiconductor chip region CR or the lower semiconductor chip DC of the second device layer DL2c or the second device layer DL2e of fig. 8 or 12. The intermediate region IR-2 may be the intermediate region IR of the first device layer DL1c and the intermediate region IR of the second device layer DL2c of fig. 8 or 12. Scribe line region SL-2 may be a scribe line region SL of the first device layer DL1c and a scribe line region SL of the second device layer DL2c of fig. 8 or 12.
Fig. 22(a) to 24(d) are cross-sectional views for conceptually describing processes of forming device bonding pads, chip bonding pads, and additional bonding pads according to a method of manufacturing a semiconductor package according to example embodiments. A process of forming the device bonding pad 130 will be described with reference to fig. 22(a) to 24(d) and fig. 1A and 1C.
Referring to fig. 22(a) to 22(c), as shown in fig. 22(a), top surfaces of the first and second internal connection pads 132 and 134 and top surfaces of the first and second insulating cover layers 142 and 144 may be on the same plane (e.g., may be coplanar). As shown in fig. 22(b), the first and second cover insulating layers 142 and 144 may be in contact with each other by applying heat of a first temperature. As shown in fig. 22(c), when heat of a second temperature is applied, metal atoms of the first and second internal connection pads 132 and 134 may be diffused to be integrated, thereby forming a plurality of device bonding pads 130.
Referring to fig. 23(a) to 23(d), as shown in fig. 23(a), by adjusting the conditions of the planarization process for forming the first and second internal connection pads 132 and 134, the top surface of one of the first and second internal connection pads 132 and 134 may protrude and the top surface of the other may be recessed. As shown in fig. 23(b), when heat of a first temperature is applied, the first and second cover insulating layers 142 and 144 may contact each other. As shown in fig. 23(c), when heat of a second temperature is applied, the first and second internal connection pads 132 and 134 may expand to contact each other. Next, as shown in fig. 23(d), the metal atoms of the first and second internal connection pads 132 and 134 may be diffused to be integrated, thereby forming a plurality of device bonding pads 130.
Referring to fig. 24(a) to 24(d), as shown in fig. 24(a), the first and second internal connection pads 132 and 134 may have different widths. As shown in fig. 24(b), when heat of a first temperature is applied, the first and second cover insulating layers 142 and 144 may contact each other. As shown in fig. 24(c), when heat of the second temperature is applied, the first and second internal connection pads 132 and 134 may expand to contact each other. Next, as shown in fig. 24(d), the metal atoms of each of the first and second internal connection pads 132 and 134 may be diffused to be integrated, thereby forming a plurality of device bonding pads 130.
Since the semiconductor package according to some example embodiments of the inventive concept may achieve a relatively fine pitch without using an additional interposer, the manufacturing cost of the semiconductor package may be reduced. Since the semiconductor package has a re-wiring structure connected to the external connection terminals, an additional printed circuit board may not be used, thereby making it possible to have a relatively small external size.

Claims (20)

1. A semiconductor package, comprising:
a first device layer comprising a plurality of first semiconductor devices, a first capping insulating layer, and a plurality of first through electrodes passing through at least a portion of the first device layer;
a second device layer including a plurality of second semiconductor devices vertically overlapping the plurality of first semiconductor devices, respectively, a second capping insulating layer contacting the first capping insulating layer, and a plurality of second through electrodes penetrating at least a portion of the second device layer;
a third device layer including an upper semiconductor chip vertically overlapping at least two of the plurality of first semiconductor devices and vertically overlapping at least two of the plurality of second semiconductor devices; and
a plurality of device bonding pads passing through the first and second cover insulating layers, the plurality of device bonding pads electrically connecting the plurality of first and second through electrodes to the upper semiconductor chip.
2. The semiconductor package of claim 1, wherein
The first device layer comprises a first semiconductor substrate including a plurality of first semiconductor chip regions spaced apart from one another by one or more first scribe regions therebetween, the first semiconductor substrate including an active surface on which the plurality of first semiconductor devices are positioned, and one or more first scribe regions
The first cover insulating layer covers the active surface of the first semiconductor substrate.
3. The semiconductor package of claim 2, wherein
The second device layer comprises a second semiconductor substrate including a plurality of second semiconductor chip regions and one or more second scribe regions, the plurality of second semiconductor chip regions being spaced apart from each other by the one or more second scribe regions therebetween, the second semiconductor substrate including an active surface on which the plurality of second semiconductor devices are positioned, and
the second cover insulating layer covers the active surface of the second semiconductor substrate.
4. The semiconductor package of claim 3, wherein
The upper semiconductor chip includes:
a third semiconductor substrate having an active surface on which a third semiconductor device is positioned, an
A chip cover insulating layer covering the active surface of the third semiconductor substrate, an
The semiconductor package further includes a plurality of semiconductor chips,
a third insulating cover layer covering a surface of the second semiconductor substrate facing the third device layer and in contact with the chip insulating cover layer, an
A plurality of chip bonding pads passing through the third insulating cover layer and the chip insulating cover layer and electrically connecting the third semiconductor device to the plurality of second through electrodes.
5. The semiconductor package of claim 4, wherein the second semiconductor substrate has a recess on a surface facing the third device layer, and the upper semiconductor chip is attached to a protrusion of the second semiconductor substrate defined by the recess of the second semiconductor substrate.
6. The semiconductor package of claim 2, wherein the second device layer comprises a plurality of lower semiconductor chips and a fill mold member, the plurality of lower semiconductor chips being spaced apart from one another by the fill mold member therebetween, each of the plurality of lower semiconductor chips comprising a second semiconductor substrate having an active surface on which the plurality of second semiconductor devices are positioned and a second overlying insulating layer covering the active surface of the second semiconductor substrate.
7. The semiconductor package of claim 6, wherein
The filling mold member has a through-hole accommodating a through-mold hole connected to the upper semiconductor chip, an
The semiconductor package further includes additional through electrodes located in corresponding ones of the one or more first scribe regions, penetrating the first semiconductor substrate, and connected to the through-mold holes.
8. The semiconductor package according to claim 7, wherein the first semiconductor substrate further comprises a plurality of intermediate regions respectively disposed between a pair of the one or more first scribe regions, each of the plurality of intermediate regions comprising an additional connection pad connecting the through-mold via to the additional through-electrode.
9. The semiconductor package of claim 6, wherein
The first semiconductor substrate further comprises at least two intervening regions spaced apart from each other by at least one corresponding first scribe line of the one or more first scribe line regions therebetween,
the filling mold member has a plurality of through-holes in the at least two intermediate regions, the plurality of through-holes accommodating a plurality of through-mold holes connected to the upper semiconductor chip, an
The at least two intervening regions include a plurality of additional through electrodes passing through the first semiconductor substrate and connected to the plurality of through-mold holes.
10. The semiconductor package of claim 6, wherein
The first semiconductor substrate has a recess on a surface facing the second device layer, an
The plurality of lower semiconductor chips are attached to protrusions of the first semiconductor substrate defined by the recesses of the first semiconductor substrate.
11. The semiconductor package of claim 1, further comprising:
a re-routing structure on a first surface of the first device layer opposite a second surface of the first device layer facing the second device layer, the re-routing structure comprising,
a plurality of re-wiring insulating layers,
a plurality of re-wiring conductive patterns respectively located on one of a top surface or a bottom surface of one of the plurality of re-wiring insulating layers, and
a plurality of re-wiring via patterns respectively connecting a pair of vertically adjacent re-wiring conductive patterns of the plurality of re-wiring conductive patterns and passing through at least one of the plurality of re-wiring insulating layers,
wherein the plurality of re-wiring conductive patterns and the plurality of re-wiring via patterns are electrically connected to the plurality of first through electrodes.
12. A semiconductor package, comprising:
a first device layer comprising:
a first semiconductor substrate having an active surface, the first semiconductor substrate comprising:
one or more first scribe areas, and
a plurality of first semiconductor chip regions spaced apart from each other by the one or more first scribe regions therebetween, each of the plurality of first semiconductor chip regions provided with a first semiconductor device on the active surface of the first semiconductor substrate,
a plurality of first through electrodes in the plurality of first semiconductor chip regions and through the first semiconductor substrate, an
A first cover insulating layer covering the active surface of the first semiconductor substrate;
a second device layer comprising:
a second semiconductor substrate comprising an active surface, the second semiconductor substrate comprising:
one or more second scribe areas, and
a plurality of second semiconductor chip regions spaced apart from each other by the one or more second scribe regions therebetween, each of the plurality of second semiconductor chip regions having a second semiconductor device disposed on the active surface of the second semiconductor substrate, the second semiconductor device being of the same type as the first semiconductor device,
a plurality of second through-electrodes located in the plurality of second semiconductor chip regions and penetrating the second semiconductor substrate, an
A second blanket insulating layer overlying the active surface of the second semiconductor substrate and in contact with the first blanket insulating layer;
a third device layer including an upper semiconductor chip on the second device layer and electrically connected to the plurality of second through electrodes; and
a plurality of device bond pads passing through the first and second blanket insulating layers and electrically connecting the first device layer to the second device layer.
13. The semiconductor package of claim 12, wherein
The upper semiconductor chip includes a plurality of chip connection pads, an
The semiconductor package further comprises a plurality of semiconductor chips,
a plurality of upper connection pads on a first surface of the second semiconductor substrate opposite to a second surface of the second semiconductor substrate facing the first device layer, and connected to corresponding through electrodes among the plurality of second through electrodes,
a plurality of chip connection terminals between the plurality of chip connection pads and corresponding upper connection pads of the plurality of upper connection pads, an
A packaging member located on the second semiconductor substrate and surrounding a side surface of the upper semiconductor chip.
14. The semiconductor package of claim 12, wherein
The first semiconductor substrate further includes a first residual scribe line region surrounding the plurality of first semiconductor chip regions at an edge of the first semiconductor substrate,
the second semiconductor substrate further comprises a second residual scribe line region surrounding the plurality of second semiconductor chip regions at an edge of the second semiconductor substrate, an
Each of the one or more first scribe areas and the one or more second scribe areas has a first width, and each of the first residual scribe areas and the second residual scribe areas has a second width that is less than the first width.
15. The semiconductor package of claim 12, further comprising:
a first additional through electrode located in a corresponding first scribe region of the one or more first scribe regions and passing through the first semiconductor substrate;
a second additional through electrode located in a corresponding second scribe line region of the one or more second scribe line regions, passing through the second semiconductor substrate, and electrically connected to the upper semiconductor chip; and
an additional bonding pad passing through the first and second cover insulating layers and electrically connecting the first additional through electrode to the second additional through electrode.
16. The semiconductor package of claim 15, wherein each of the plurality of device bond pads or the additional bond pad is a diffusion bonded unitary structure of two sub-structures.
17. The semiconductor package of claim 12, wherein
The first semiconductor substrate further includes a first intermediate region spaced apart from a corresponding first semiconductor chip region of the plurality of first semiconductor chip regions by a corresponding first scribe region of the one or more first scribe regions interposed therebetween, and
the second semiconductor substrate further comprises a second interposer region spaced apart from corresponding ones of the plurality of second semiconductor chip regions by respective ones of the one or more second scribe line regions interposed therebetween,
the first intermediate region includes a plurality of first additional through electrodes passing through the first semiconductor substrate, an
The second intermediate region includes a plurality of second additional through-electrodes passing through the second semiconductor substrate and electrically connecting the plurality of first additional through-electrodes to the upper semiconductor chip,
the semiconductor package further includes a plurality of additional bonding pads passing through the first and second insulating cover layers and electrically connecting the first additional through electrodes to the second additional through electrodes.
18. A semiconductor package, comprising:
a first semiconductor substrate comprising an active surface, the first semiconductor substrate comprising,
a plurality of scribe line regions, an
A plurality of first semiconductor chip regions spaced apart from each other by corresponding ones of the plurality of scribe line regions therebetween, each of the plurality of first semiconductor chip regions being provided with at least one first semiconductor device on the active surface of the first semiconductor substrate;
a plurality of first through electrodes in the plurality of first semiconductor chip regions and through the first semiconductor substrate;
a first cover insulating layer covering the active surface of the first semiconductor substrate;
a plurality of lower semiconductor chips on the first semiconductor substrate and corresponding to the plurality of first semiconductor chip regions, respectively, each of the plurality of lower semiconductor chips including,
a second semiconductor substrate having an active surface on which at least one second semiconductor device is positioned, the second semiconductor substrate including a plurality of second through-electrodes therethrough, and
a second blanket insulating layer overlying the active surface of the second semiconductor substrate and in contact with the first blanket insulating layer;
a plurality of device bonding pads passing through the first and second cover insulating layers and electrically connecting the plurality of first through electrodes to the plurality of second through electrodes; and
an upper semiconductor chip including a third semiconductor device, the upper semiconductor chip vertically overlapping with at least two of the plurality of lower semiconductor chips and electrically connected to the plurality of second through electrodes.
19. The semiconductor package of claim 18, further comprising:
a filling mold member on the first semiconductor substrate, the filling mold member filling a space between the plurality of lower semiconductor chips.
20. The semiconductor package of claim 18, wherein the first and second semiconductor devices are of the same type, an
The third semiconductor device is of a different type than the first semiconductor device and the second semiconductor device.
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