CN110868227B - Transmission circuit capable of measuring image rejection ratio of transmission end - Google Patents
Transmission circuit capable of measuring image rejection ratio of transmission end Download PDFInfo
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- CN110868227B CN110868227B CN201810992007.4A CN201810992007A CN110868227B CN 110868227 B CN110868227 B CN 110868227B CN 201810992007 A CN201810992007 A CN 201810992007A CN 110868227 B CN110868227 B CN 110868227B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B1/0475—Circuits with means for limiting noise, interference or distortion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
- H04B1/0067—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with one or more circuit blocks in common for different bands
- H04B1/0082—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with one or more circuit blocks in common for different bands with a common local oscillator for more than one band
- H04B1/0085—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with one or more circuit blocks in common for different bands with a common local oscillator for more than one band where one band is the image frequency band of the other and the band selection is done by image rejection
Abstract
The invention provides a transmission circuit capable of measuring the image rejection ratio of a transmission end, comprising: an in-phase signal processing circuit; a quadrature phase signal processing circuit; the analog signal processing circuit is used for generating a corresponding analog signal according to signals output by the in-phase signal processing circuit and the quadrature-phase signal processing circuit; the transmission end control circuit is used for controlling the in-phase signal processing circuit and the quadrature-phase signal processing circuit to be combined with the analog signal processing circuit to generate a first preset signal at a first time point and controlling the in-phase signal processing circuit and the quadrature-phase signal processing circuit to be combined with the analog signal processing circuit to generate a second preset signal at a second time point; and an image rejection ratio measuring circuit for generating an image rejection ratio estimate of the transmission circuit based on the first predetermined signal and the second predetermined signal.
Description
Technical Field
The present invention relates to a transmission circuit, and more particularly, to a transmission circuit capable of measuring an image rejection ratio of a transmission terminal.
Background
The gain and/or phase mismatch between the in-phase signal (in-phase signal) and the quadrature-phase signal (quadrature signal) in the transmission circuit of the wireless communication apparatus, i.e., the so-called in-phase/quadrature mismatch (I/Q mismatch) can be measured by the image rejection ratio of the transmission circuit. The conventional method for measuring the image rejection ratio of the transmission circuit usually uses an external instrument such as a spectrum analyzer to measure the signal at the transmitting end of the transmission circuit.
However, the conventional measurement method depends on external instruments such as a spectrum analyzer, so that the measurement efficiency and convenience are not ideal, and especially when a large number of transmission circuits are required for measurement, much labor and time are required for coupling the transmission circuits to the external instruments such as the spectrum analyzer one by one.
Disclosure of Invention
Therefore, how to effectively improve the efficiency of measuring the image rejection ratio of the transmission circuit is a problem to be solved.
The present specification provides an embodiment of a transmit circuit, comprising: an in-phase signal processing circuit; a quadrature phase signal processing circuit; an analog signal processing circuit, coupled to the output ends of the in-phase signal processing circuit and the quadrature-phase signal processing circuit, configured to generate a corresponding analog signal according to the signals output by the in-phase signal processing circuit and the quadrature-phase signal processing circuit; a transmission end control circuit, coupled to the input ends of the in-phase signal processing circuit and the quadrature-phase signal processing circuit, configured to control the in-phase signal processing circuit and the quadrature-phase signal processing circuit to operate in conjunction with the analog signal processing circuit at a first time point to generate a first predetermined signal, and control the in-phase signal processing circuit and the quadrature-phase signal processing circuit to operate in conjunction with the analog signal processing circuit at a second time point to generate a second predetermined signal; and an image rejection ratio measuring circuit, coupled to the output end of the analog signal processing circuit and the transmitting end control circuit, configured to generate an image rejection ratio estimation value of the transmitting circuit according to the first predetermined signal and the second predetermined signal under the control of the transmitting end control circuit.
One advantage of the above embodiment is that the image rejection ratio estimate generated by the transmission circuit can be used to measure the in-phase/quadrature-phase mismatch of the transmission circuit, so that no external instrument such as a spectrum analyzer is required to measure the transmission circuit.
Other advantages of the present invention will be explained in more detail in conjunction with the following description and the accompanying drawings.
Drawings
Fig. 1 is a simplified functional block diagram of a transmitting circuit according to an embodiment of the present invention.
Fig. 2 is a simplified functional block diagram of the image reject ratio measurement circuit of fig. 1 according to an embodiment.
Fig. 3 is a simplified diagram of an embodiment of the image reject ratio measurement circuit of fig. 1.
Fig. 4 is a simplified diagram of another embodiment of the image reject ratio measurement circuit of fig. 1.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar elements or process flows.
Fig. 1 is a simplified functional block diagram of a transmitting circuit 100 according to an embodiment of the present invention. As shown in fig. 1, the transmission circuit 100 includes an in-phase signal processing circuit 111, a quadrature-phase signal processing circuit 112, an analog signal processing circuit 113, a transmission end control circuit 114, a power amplification circuit 115, a switch 116, and an image rejection ratio measurement circuit 117.
The in-phase signal processing circuit 111 is arranged to process the in-phase signal generated by the transmit side control circuit 114 and the quadrature-phase signal processing circuit 112 is arranged to process the quadrature-phase signal generated by the transmit side control circuit 114.
The analog signal processing circuit 113 is coupled to the output terminals of the in-phase signal processing circuit 111 and the quadrature-phase signal processing circuit 112, and configured to generate a corresponding analog signal according to the signals output by the in-phase signal processing circuit 111 and the quadrature-phase signal processing circuit 112.
The transmitter control circuit 114 is coupled to input terminals of the in-phase signal processing circuit 111 and the quadrature-phase signal processing circuit 112, and configured to generate an in-phase signal required by the in-phase signal processing circuit 111 and a quadrature-phase signal required by the quadrature-phase signal processing circuit 112.
The image rejection ratio measuring circuit 117 is coupled to the output terminal of the analog signal processing circuit 113 and the transmitting terminal control circuit 114, and is configured to generate an image rejection ratio estimation (estimated image rejection ratio) of the transmitting circuit 100 under the control of the transmitting terminal control circuit 114.
The power amplification circuit 115 is located on an output signal path of the amplified analog signal processing circuit 113 and is arranged to amplify an analog signal generated by the analog signal processing circuit 113 to generate a wireless signal to be transmitted through the transmitting antenna 102.
The switch 116 is provided on the output path of the analog signal processing circuit 113 and is controlled by the transmission-side control circuit 114. In the embodiment of fig. 1, the switch 116 is located between the analog signal processing circuit 113 and the power amplification circuit 115.
The in-phase signal processing circuit 111, the quadrature-phase signal processing circuit 112, the analog signal processing circuit 113, and the power amplification circuit 115 can be implemented by various appropriate existing circuits. The transmit side control circuit 114 may be implemented with various suitable circuits having digital signal processing and computing capabilities. The switch 116 may be implemented by a single transistor or a combination of suitable transistors. The image reject ratio measurement circuit 117 may be implemented with suitable circuitry having analog signal processing capability and digital computing capability.
In fact, the different functional blocks of the transmitting circuit 100 can be implemented by different circuits respectively, or can be integrated into a single circuit chip.
In normal operation, the transmitter control circuit 114 turns on the switch 116, so that the analog signal generated by the analog signal processing circuit 113 is input to the power amplifier circuit 115. At this time, the power amplifier circuit 115 generates a wireless signal to be transmitted through the transmitting antenna 102 according to the analog signal generated by the analog signal processing circuit 113.
Before normal operation, the transmitting circuit 100 may adopt various known in-phase/quadrature phase mismatch calibration procedures to mitigate the in-phase/quadrature phase mismatch in the transmitting circuit 100 and generate an image rejection ratio estimate of the transmitting circuit 100, so that the relevant testing personnel or testing equipment can measure the in-phase/quadrature phase mismatch or the calibrated result of the transmitting circuit 100.
In operation, the Tx control circuit 114 controls the in-phase signal processing circuit 111 and the quadrature-phase signal processing circuit 112 to operate in conjunction with the analog signal processing circuit 113 to generate a first predetermined signal Tx1 at a first time point T1, and controls the in-phase signal processing circuit 111 and the quadrature-phase signal processing circuit 112 to operate in conjunction with the analog signal processing circuit 113 to generate a second predetermined signal Tx2 at a second time point T2. The image rejection ratio measuring circuit 117 generates the image rejection ratio estimation value of the transmitting circuit 100 according to the first predetermined signal Tx1 and the second predetermined signal Tx 2.
The embodiment and operation of the image rejection ratio measurement circuit 117 will be further described with reference to fig. 2 and 3. Fig. 2 is a simplified functional block diagram of the image reject ratio measurement circuit 117 of fig. 1. Fig. 3 is a simplified diagram of an embodiment of the image reject ratio measurement circuit 117.
In the embodiment of fig. 2, the image rejection ratio measuring circuit 117 includes an analog down-conversion circuit 210, a gain amplifying circuit 220, an analog-to-digital converter 230, a fourier transform circuit 240, a storage circuit 250, and an image rejection ratio estimating circuit 260.
The analog down converter circuit 210 is coupled to the output terminal of the analog signal processing circuit 113, and configured to generate a down-converted signal according to the signal output by the analog signal processing circuit 113.
The gain amplifier circuit 220 is coupled to the analog down-conversion circuit 210 and configured to generate a corresponding amplified signal according to the down-converted signal outputted by the analog down-conversion circuit 210.
The analog-to-digital converter 230 is coupled to the gain amplifier circuit 220 and configured to generate a corresponding digital signal according to the amplified signal output by the gain amplifier circuit 220.
The fourier transform circuit 240 is coupled to the analog-to-digital converter 230 and configured to generate a corresponding signal energy value according to the digital signal output by the analog-to-digital converter 230.
The storage circuit 250 is coupled to the fourier transform circuit 240 and configured to store a plurality of signal energy values generated by the fourier transform circuit 240 at different time points.
The image rejection ratio estimation circuit 260 is coupled to the storage circuit 250 and the transmission end control circuit 114, and configured to generate the image rejection ratio estimation value of the transmission circuit 100 according to a plurality of signal energy values in the storage circuit 250. The image rejection ratio estimation circuit 260 may be implemented with various suitable circuits having digital operation capabilities.
In practice, the analog down-conversion circuit 210 may be implemented with various suitable down-conversion circuits, for example, the analog down-conversion circuit 210 may be implemented with a self-mixer circuit (self-mixer circuit). The gain amplification circuit 220 may be implemented with various suitable amplification circuits having fixed gain values or adjustable gain values. The fourier transform circuit 240 may be implemented with various suitable circuits having digital computing capabilities. The storage circuit 250 may be implemented with various suitable volatile memory or non-volatile storage circuits. The image rejection ratio estimation circuit 260 may be implemented by various suitable circuits having digital operation capability.
In some embodiments, the image rejection ratio estimation circuit 260 may also be integrated into the transmit-side control circuit 114.
As shown in fig. 2, when the image rejection ratio estimate of the transmission circuit 100 needs to be generated, the transmission end control circuit 114 may transmit a first in-phase signal DI-1 to the in-phase signal processing circuit 111 at the first time point T1, and transmit a first quadrature-phase signal DQ-1 to the quadrature-phase signal processing circuit 112, so that the in-phase signal processing circuit 111 and the quadrature-phase signal processing circuit 112 operate in conjunction with the analog signal processing circuit 113 to generate the first predetermined signal Tx 1.
In this case, the analog down-conversion circuit 210 generates a corresponding first down-converted signal F1 according to the first predetermined signal Tx 1. The gain amplifier circuit 220 generates a corresponding first amplified signal A1 according to the first down-converted signal F1. The adc 230 generates a corresponding first digital signal D1 according to the first amplified signal a 1. The fourier transform circuit 240 generates a corresponding first signal energy value P1 according to the first digital signal D1, and stores the first signal energy value P1 in the storage circuit 250.
Then, the Tx control circuit 114 transmits a second in-phase signal DI-2 to the in-phase signal processing circuit 111 at the second time point T2, but does not transmit any quadrature-phase signal to the quadrature-phase signal processing circuit 112, so that the in-phase signal processing circuit 111 operates in conjunction with the analog signal processing circuit 113 to generate the second predetermined signal Tx 2.
In this case, the analog down-conversion circuit 210 generates a corresponding second down-converted signal F2 according to the second predetermined signal Tx 2. The gain amplifier circuit 220 generates a corresponding second amplified signal A2 according to the second down-converted signal F2. The adc 230 generates a corresponding second digital signal D2 according to the second amplified signal a 2. The fourier transform circuit 240 generates a corresponding second signal energy value P2 according to the second digital signal D2, and stores the second signal energy value P2 in the storage circuit 250.
In this embodiment, the Tx control circuit 114 can appropriately set the signals transmitted to the in-phase signal processing circuit 111 and the quadrature-phase signal processing circuit 112 at the first time point T1 and the second time point T2, such that the first predetermined signal Tx1 is a single-tone signal (single-tone signal), the second predetermined signal Tx2 is a double-tone signal (two-tone signal), and the magnitude of each pulse energy of the second predetermined signal Tx2 is one fourth of the pulse energy of the first predetermined signal Tx 1.
The image rejection ratio estimation circuit 260 generates the image rejection ratio estimation of the transmission circuit 100 according to the first signal energy value P1 and the second signal energy value P2 stored in the storage circuit 250 under the direction of the transmission control circuit 114. For example, the image rejection ratio estimation circuit 260 may generate the image rejection ratio estimate according to the following equation (1):
IMR＝10*log10[16*VP2/VP1]……(1)
where IMR is the magnitude of the image rejection ratio estimate, VP1 is the magnitude of the first signal energy value P1, and VP2 is the magnitude of the second signal energy value P2.
In practice, the tx control circuit 114 may turn off (turn off) the switch 116 at the first time point T1 and the second time point T2, or maintain the switch 116 in the off state during the period from the first time point T1 to the second time point T2, so that the transmitting circuit 100 does not transmit signals through the transmitting antenna 102 during the generation of the image rejection ratio estimate.
Fig. 4 is a simplified diagram of another embodiment of the image reject ratio measurement circuit 117. In the embodiment of fig. 4, the tx control circuit 114 transmits a second quadrature-phase signal DQ-2 to the quadrature-phase signal processing circuit 112 at the aforementioned second time point T2, but does not transmit any in-phase signal to the in-phase signal processing circuit 111. The Tx control circuit 114 may suitably set the second quadrature-phase signal DQ-2 transmitted to the quadrature-phase signal processing circuit 112 at the second time point T2, so that the quadrature-phase signal processing circuit 112 operates in conjunction with the analog signal processing circuit 113 to generate the second predetermined signal Tx 2.
As can be seen from the above description, when the in-phase/quadrature-phase mismatch of the transmission circuit 100 is to be measured, the image rejection ratio measurement circuit 117 can generate an image rejection ratio estimation value for measuring the in-phase/quadrature-phase mismatch of the transmission circuit 100, so that it is not necessary to use an external device such as a spectrum analyzer to measure the transmission circuit 100.
Since the transmission circuit 100 does not need to be coupled to an external instrument such as a spectrum analyzer in the aforementioned process of generating the image rejection ratio estimate of the transmission circuit 100, the labor and the operation time required for obtaining the image rejection ratio of the transmission circuit 100 can be effectively saved.
Certain terms are used throughout the description and claims to refer to particular elements, and those skilled in the art may refer to like elements by different names. In the present specification and claims, the difference in name is not used as a means for distinguishing elements, but the difference in function of the element is used as a reference for distinguishing. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" is intended to include any direct or indirect connection. Therefore, if a first element is coupled to a second element, the first element can be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or indirectly connected to the second element through another element or a connection means.
The description of "and/or" as used in this specification is inclusive of any combination of one or more of the items listed. In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.
The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the present invention.
[ notation ] to show
100 transfer circuit (transmitter circuit)
102 transmitting antenna (transmitting antenna)
111 in-phase signal processing circuit (in-phase signal processing circuit)
112 quadrature phase signal processing circuit (quadrature signal processing circuit)
113 analog signal processing circuit (analog signal processing circuit)
114 transmit control circuit (transmitter control circuit)
115 power amplifier circuit (power amplifier circuit)
116 switch (switch)
117 image rejection ratio measurement circuit (image rejection ratio circuit)
210 analog down converter circuit (analog down-converter circuit)
220 gain amplifier circuit (gain amplifier circuit)
230 analog-to-digital converter (analog-to-digital converter)
240 Fourier transform circuit (Fourier transform circuit)
250 storage circuit (storage circuit)
260 image rejection ratio estimating circuit (image rejection ratio estimating circuit).
Claims (6)
1. A transmit circuit (100), comprising:
an in-phase signal processing circuit (111);
a quadrature phase signal processing circuit (112);
an analog signal processing circuit (113), coupled to the output terminals of the in-phase signal processing circuit (111) and the quadrature-phase signal processing circuit (112), configured to generate a corresponding analog signal according to signals output from the in-phase signal processing circuit (111) and the quadrature-phase signal processing circuit (112);
a transmit end control circuit (114), coupled to the input ends of the in-phase signal processing circuit (111) and the quadrature-phase signal processing circuit (112), configured to control the in-phase signal processing circuit (111) and the quadrature-phase signal processing circuit (112) to operate in conjunction with the analog signal processing circuit (113) at a first time point (T1) to generate a first predetermined signal (Tx1), and control the in-phase signal processing circuit (111) and the quadrature-phase signal processing circuit (112) to operate in conjunction with the analog signal processing circuit (113) at a second time point (T2) to generate a second predetermined signal (Tx 2); and
an image rejection ratio measurement circuit (117), coupled to the output of the analog signal processing circuit (113) and the transmit end control circuit (114), configured to generate an image rejection ratio estimate of the transmit circuit (100) based on the first predetermined signal (Tx1) and the second predetermined signal (Tx2) under the control of the transmit end control circuit (114),
wherein the first predetermined signal (Tx1) is a monotone signal, and the second predetermined signal (Tx2) is a bi-tone signal.
2. The transmission circuit (100) of claim 1, wherein the second predetermined signal (Tx2) has a pulse energy level that is one quarter of the pulse energy level of the first predetermined signal (Tx 1).
3. The transmitting circuit (100) of claim 1, wherein at the first time point (T1), the transmit end control circuit (114) transmits a first in-phase signal (DI-1) to the in-phase signal processing circuit (111) and a first quadrature-phase signal (DQ-1) to the quadrature-phase signal processing circuit (112), and at the second time point (T2), the transmit end control circuit (114) transmits only a second in-phase signal (DI-2) to the in-phase signal processing circuit (111) without transmitting any quadrature-phase signal to the quadrature-phase signal processing circuit (112) or transmits only a second quadrature-phase signal (DQ-2) to the quadrature-phase signal processing circuit (112) without transmitting any in-phase signal to the in-phase signal processing circuit (111).
4. The transmit circuit (100) of claim 1, further comprising:
a switch (116) disposed on the output path of the analog signal processing circuit (113) and controlled by the transmitting end control circuit (114);
wherein the transmitter control circuit (114) turns off the switch (116) at the first time point (T1) and the second time point (T2).
5. The transmission circuit (100) according to any of claims 1 to 4, wherein the image reject ratio measurement circuit (117) comprises:
an analog down-conversion circuit (210) configured to generate a first down-converted signal (F1) according to the first predetermined signal (Tx1) and generate a second down-converted signal (F2) according to the second predetermined signal (Tx 2);
a gain amplification circuit (220), coupled to the analog down-conversion circuit (210), configured to generate a first amplified signal (a1) according to the first down-converted signal (F1), and generate a second amplified signal (a2) according to the second down-converted signal (F2);
an analog-to-digital converter (230), coupled to the gain amplifier circuit (220), configured to generate a first digital signal (D1) according to the first amplified signal (a1), and generate a second digital signal (D2) according to the second amplified signal (a 2);
a Fourier transform circuit (240), coupled to the analog-to-digital converter (230), configured to generate a first signal energy value (P1) according to the first digital signal (D1), and generate a second signal energy value (P2) according to the second digital signal (D2);
a storage circuit (250), coupled to the fourier transform circuit (240), configured to store the first signal energy value (P1) and the second signal energy value (P2); and
an image rejection ratio estimation circuit (260), coupled to the storage circuit (250) and the transmit control circuit (114), is configured to generate the image rejection ratio estimate based on the first signal energy value (P1) and the second signal energy value (P2).
6. The transmission circuit (100) of claim 5, wherein the analog down-conversion circuit (210) is a self-mixing circuit.
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| CN201810992007.4A CN110868227B (en) | 2018-08-28 | 2018-08-28 | Transmission circuit capable of measuring image rejection ratio of transmission end |
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| CN201810992007.4A CN110868227B (en) | 2018-08-28 | 2018-08-28 | Transmission circuit capable of measuring image rejection ratio of transmission end |
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