CN110868055A - Fault current limiter for DC/DC converter - Google Patents
Fault current limiter for DC/DC converter Download PDFInfo
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- CN110868055A CN110868055A CN201911133451.1A CN201911133451A CN110868055A CN 110868055 A CN110868055 A CN 110868055A CN 201911133451 A CN201911133451 A CN 201911133451A CN 110868055 A CN110868055 A CN 110868055A
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- limiting inductor
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/325—Means for protecting converters other than automatic disconnection with means for allowing continuous operation despite a fault, i.e. fault tolerant converters
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Abstract
The invention provides a fault current limiter for a DC/DC converter, which comprises a triple bridge circuit, a current limiting circuit and a capacitor module which are connected, wherein the capacitor module comprises a switch circuit and a super capacitor which are connected in series, and the super capacitor and the current limiting circuit can limit fault current and meet the requirement of a power distribution system on quickly and accurately positioning a fault point. The super capacitor and the switch circuit are arranged, energy can be transmitted to a low-voltage side from a medium-voltage side in time when a fault occurs, so that the fault current limiter can limit the magnitude of fault current, the current can be guaranteed to be maintained for a preset time at 1-1.35pu, and a foundation is provided for fault positioning. The invention determines the inductance values of the current-limiting inductor L1, the current-limiting inductor L2 and the current-limiting inductor L3 based on the fault current rise rate, and determines the nominal capacitance value of the super capacitor based on the initial discharge voltage, the voltage after discharge, the discharge current and the discharge time of the super capacitor, thereby improving the economy under the condition of reducing the input and output characteristics of the original circuit.
Description
Technical Field
The invention relates to the technical field of power transmission and distribution, in particular to a fault current limiter for a DC/DC converter.
Background
As global energy supply changes toward clean, low carbon, electrified directions, the form of distribution networks is rapidly changing. On the power supply side, the proportion of distributed renewable energy resources is continuously improved, and the application of technologies such as distributed power generation, energy storage and comprehensive energy resources promotes the cleanness and diversification of the power supply of the power distribution network; on the load side, a large number of novel load terminals such as data centers and electric vehicles appear, and a deep game with participation of multi-benefit subjects is formed in a market environment, so that the power distribution network is subject to more complicated and interactive service requirements. Compared with the traditional alternating-current power distribution network, the direct-current power distribution network has the characteristics of large power supply capacity, high electric energy quality, small line loss, high power supply reliability, direct-current power distribution to the home and the like, so that the direct-current power distribution network is more and more valued, and the direct-current power distribution demonstration project and the direct-current power distribution network are developed in Jiangsu and other places in China at present and are the development trend in the future.
The DC/DC converter is a core device applied to a high-voltage and high-power alternating current-direct current system such as new energy power generation, electric energy quality control and energy storage system access, and is used for realizing voltage conversion from high-voltage (low-voltage) direct current to low-voltage (high-voltage) direct current in a direct current power distribution network and realizing flexible control of the size and direction of the tide. The topology of the DC/DC Converter mainly includes a Modular Multilevel Converter (MMC), an Input series output Parallel Converter (ISOP), and the like, and most of the current research and application is the ISOP DC/DC Converter, each layer of the ISOP DC/DC Converter is a Dual Active Bridge (DAB), both ends are full bridges, and the middle isolation link adopts a high-frequency transformer. When short-circuit fault occurs on the low-voltage side, the fault current must be limited, and meanwhile, the fault current can be maintained for a period of time, so that a fault point can be quickly and accurately positioned by a power distribution system conveniently.
Disclosure of Invention
In order to overcome the defect that the requirement of a power distribution system for quickly and accurately positioning a fault point is not met in the prior art, the invention provides the fault current limiter for the DC/DC converter, which comprises a triple bridge circuit, a current limiting circuit and a capacitor module which are connected, wherein the capacitor module comprises a switch circuit and a super capacitor which are connected in series, and the super capacitor and the current limiting circuit can limit the fault current and meet the requirement of the power distribution system for quickly and accurately positioning the fault point.
In order to achieve the purpose of the invention, the invention adopts the following technical scheme:
in one aspect, the invention provides a fault current limiter for a DC/DC converter, which comprises a triple bridge circuit, a current limiting circuit and a capacitor module which are connected;
the capacitor module comprises a switch circuit and a super capacitor which are connected in series.
The triple bridge circuit comprises three parallel bridge arms;
each bridge arm comprises an upper bridge arm and a lower bridge arm.
The current limiting circuit comprises a current limiting inductor L1, a current limiting inductor L2 and a current limiting inductor L3;
one end of each of the current-limiting inductor L1, the current-limiting inductor L2 and the current-limiting inductor L3 is connected with the middle point of each of the three bridge arms, and the other end of each of the current-limiting inductor L1, the current-limiting inductor L2 and the current-limiting inductor L3 is connected with the capacitor module.
The inductance values of the current-limiting inductor L1, the current-limiting inductor L2 and the current-limiting inductor L3 are determined based on the fault current rise rate.
The upper bridge arm in each bridge arm comprises a first full-control device and a first diode which is connected with the first full-control device in an anti-parallel mode;
the lower bridge arm in each bridge arm comprises a second fully-controlled device and a second diode connected with the second fully-controlled device in an anti-parallel mode.
The lower leg of each leg includes a second diode.
And the first full-control device and the second full-control device both adopt IGBTs.
The directions of the IGBTs in all the bridge arms are consistent.
The nominal capacity of the super capacitor is determined according to the following formula:
where C is the nominal capacity of the supercapacitor, V0Initial discharge initial voltage, V, for the super capacitorminThe voltage of the super capacitor after discharging, I is the discharge current of the super capacitor, and t is the discharge time of the super capacitor.
Compared with the closest prior art, the technical scheme provided by the invention has the following beneficial effects:
the fault current limiter for the DC/DC converter comprises a triple bridge circuit, a current limiting circuit and a capacitor module which are connected, wherein the capacitor module comprises a switch circuit and a super capacitor which are connected in series;
according to the technical scheme provided by the invention, the super capacitor and the switch circuit are arranged, so that energy can be transmitted to a medium-voltage side and a low-voltage side in time when a fault occurs, a fault current limiter can limit the magnitude of fault current, the current can be ensured to be maintained for a preset time at 1-1.35pu, and a foundation is provided for fault positioning;
the triple bridge circuit adopts a topological structure combining a full-control device and a half-control device (namely, a diode), so that the probability of device damage caused by overlarge bearing stress of the full-control device is greatly reduced;
the invention determines the inductance values of the current-limiting inductor L1, the current-limiting inductor L2 and the current-limiting inductor L3 based on the fault current rise rate, and determines the nominal capacitance value of the super capacitor based on the initial discharge voltage, the voltage after discharge, the discharge current and the discharge time of the super capacitor, thereby improving the economy under the condition of reducing the input and output characteristics of the original circuit.
Drawings
Fig. 1 is a topology structural diagram of a fault current limiter in embodiment 1 of the present invention;
fig. 2 is a schematic view of the installation position of a fault current limiter in the embodiment of the invention;
fig. 3 is a schematic diagram of the working state of the fault current limiter under the normal working condition in embodiment 1 of the present invention;
fig. 4 is a schematic diagram of the working state of the fault current limiter under the fault condition in embodiment 1 of the present invention;
fig. 5 is a topology structure diagram of a fault current limiter in embodiment 2 of the present invention;
fig. 6 is a schematic diagram of the working state of the fault current limiter under the normal working condition in embodiment 2 of the present invention;
fig. 7 is a schematic diagram of the operating state of the fault current limiter under the fault condition in embodiment 2 of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Example 1
Embodiment 1 of the present invention provides a fault current limiter for a DC/DC converter, as shown in fig. 1, including a triple bridge circuit, a current limiting circuit, and a capacitor module connected in parallel in sequence;
the capacitor module comprises a switch circuit and a super capacitor which are connected in series. The switching circuit is realized by adopting a boost circuit, on one hand, the switching circuit is used for controlling charging/discharging of the super capacitor, on the other hand, the switching circuit is used for voltage stabilization control, energy can be timely cut off from transmission from a medium-voltage side to a low-voltage side when a fault occurs through the super capacitor and the switching circuit, so that the fault current limiter can limit the size of the fault current, the current can be maintained for preset time, and a foundation is provided for fault positioning.
The triple bridge circuit comprises three parallel bridge arms, each bridge arm comprises an upper bridge arm and a lower bridge arm, and the triple bridge circuit specifically comprises the following components:
the first bridge arm comprises a first upper bridge arm and a first lower bridge arm, and the first upper bridge arm and the first lower bridge arm are connected through a common point A;
the second bridge arm comprises a second upper bridge arm and a second lower bridge arm which are connected through a common point B;
the third bridge arm comprises a third upper bridge arm and a third lower bridge arm, and the third upper bridge arm and the third lower bridge arm are connected through a common point C.
The current-limiting circuit comprises a current-limiting inductor L1, a current-limiting inductor L2 and a current-limiting inductor L3, wherein one end of each of the current-limiting inductor L1, the current-limiting inductor L2 and the current-limiting inductor L3 is respectively connected with the middle points of three bridge arms, and the other end of each of the current-limiting inductor L1, the current-limiting inductor L2 and the current-limiting inductor L3 is connected with a capacitor module, and the current-limiting circuit specifically comprises:
one end of the current-limiting inductor L1 is connected with the common point A, one end of the current-limiting inductor L2 is connected with the common point B, one end of the current-limiting inductor L3 is connected with the common point C, and the other ends of the current-limiting inductor L1, the current-limiting inductor L2 and the current-limiting inductor L3 are connected with the capacitor module through the common point D.
The inductance values of the current limiting inductor L1, the current limiting inductor L2, and the current limiting inductor L3 are all determined based on the fault current rise rate. If the inductance is too small, at the moment of fault occurrence, when Sa1-Sa3 is not turned off, the current rises too fast, so that the load side is damaged due to too large current, and even Sa1-Sa3 may not be turned off to cause explosion.
The upper bridge arm in each bridge arm comprises a first full-control device and a first diode connected with the first full-control device in an anti-parallel mode, namely the first upper bridge arm, the second upper bridge arm and the third upper bridge arm comprise first full-control devices and first diodes connected with the first full-control devices in an anti-parallel mode, the lower bridge arm in each bridge arm comprises a second full-control device and second diodes connected with the second full-control devices in an anti-parallel mode, namely the first lower bridge arm, the second lower bridge arm and the third lower bridge arm comprise second full-control devices and second diodes connected with the second full-control devices in an anti-parallel mode, and the first full-control devices and the second full-control devices are all Insulated Gate Bipolar Transistors (IGBTs).
The directions of the IGBTs in all the bridge arms are the same, specifically as follows:
the collectors of the IGBTs of the first upper bridge arm, the second upper bridge arm and the third upper bridge arm are connected with a common point M;
the emitting electrodes of the IGBTs of the first lower bridge arm, the second lower bridge arm and the third lower bridge arm are connected with a common point N;
the emitter of the IGBT in the first upper bridge arm and the collector of the IGBT in the first lower bridge arm are both connected with a common point A;
the emitter of the IGBT in the second upper bridge arm and the collector of the IGBT in the second lower bridge arm are both connected with a common point B;
and the emitter of the IGBT in the third upper bridge arm and the collector of the IGBT in the third lower bridge arm are connected with a common point C.
In fig. 1, Sa1 is the IGBT of the first upper arm, Sa2 is the IGBT of the second upper arm, Sa3 is the IGBT of the third upper arm, Sb1 is the IGBT of the first lower arm, Sb2 is the IGBT of the second lower arm, and Sb3 is the IGBT of the third lower arm.
The nominal capacity of the supercapacitor is determined as follows:
where C is the nominal capacity of the supercapacitor, V0Initial discharge initial voltage, V, for the super capacitorminThe voltage of the super capacitor after discharging, I is the discharge current of the super capacitor, and t is the discharge time of the super capacitor.
The common point M and the common point N form an input end of a fault current limiter, the installation position of the fault current limiter is shown in fig. 2, the input end of the fault current limiter is connected with the output end of the DC/DC converter through a triple bridge circuit, the input end of the DC/DC converter is connected with a first direct current bus, the output end of the fault current limiter is connected with a second direct current bus through a capacitor module, and the second direct current bus is connected with a load.
The first direct current bus is a high-voltage direct current bus, and the second direct current bus is a low-voltage direct current bus.
Generally, after a medium-voltage side fault of the DC/DC converter, the DC/DC converter is required to have the capability of blocking a discharge current and maintaining a capacitor voltage, and simultaneously, after the fault is isolated within a short time, rapidly starting grid-connected operation again, and it is considered that a half-bridge module is added in front of each layer of sub-modules. For the low-voltage side fault of the DC/DC converter, the DC/DC converter is required to have the function of limiting the fault current and providing the holding current for a period of time so as to ensure the fault location, and the function is difficult to realize. The fault current limiter provided by embodiment 1 of the present invention fulfills this function and is used in an ISOP-DAB type DC/DC converter.
The working principle of the fault current limiter provided by the embodiment 1 of the invention is as follows:
when the DC/DC converter normally operates, Sa1-Sa3 is in a closed state, Sb1-Sb3 are in an open state, the super capacitor is connected in parallel in the fault current limiter, and the super capacitor is in a charged state. The current running direction is shown by a dotted line in fig. 3, and the current passes through Sa1-Sa3 and L1-L3 in sequence and then flows to the load through the low-voltage direct-current bus.
When the DC/DC converter fails, Sa1-Sa3 is immediately turned off, Sb1-Sb3 continuously keep the off state, and the current on the current-limiting inductor cannot suddenly change, so that the currents on the L1-L3 respectively flow through the diodes of the first lower bridge arm, the second lower bridge arm and the third lower bridge arm, and the current direction is shown by a dotted line in FIG. 4. The super capacitor is put into a discharging state, and adopts current stabilization control, and current is maintained for a period of time by utilizing follow current of the super capacitor, so that fault location is ensured.
Example 2
Embodiment 2 of the present invention provides a fault current limiter for a DC/DC converter, as shown in fig. 5, including a triple bridge circuit, a current limiting circuit, and a capacitor module connected in parallel in sequence;
the capacitor module comprises a switch circuit and a super capacitor which are connected in series, the switch circuit is realized by adopting a boost circuit, the switch circuit is used for controlling the charging/discharging of the super capacitor on the one hand, and is used for voltage stabilization control on the other hand, energy can be timely cut off from a medium-voltage side to a low-voltage side when a fault occurs through the super capacitor and the switch circuit, so that the fault current limiter can limit the size of fault current, the current can be maintained for preset time, and a foundation is provided for fault positioning.
The triple bridge circuit comprises three parallel bridge arms, namely a first bridge arm, a second bridge arm and a third bridge arm;
the first bridge arm comprises a first upper bridge arm and a first lower bridge arm, and the first upper bridge arm and the first lower bridge arm are connected through a common point A;
the second bridge arm comprises a second upper bridge arm and a second lower bridge arm, and the second upper bridge arm and the second lower bridge arm are connected through a common point B;
the third bridge arm comprises a third upper bridge arm and a third lower bridge arm, and the third upper bridge arm and the third lower bridge arm are connected through a common point C.
The current limiting circuit comprises a current limiting inductor L1, a current limiting inductor L2 and a current limiting inductor L3;
one end of the current-limiting inductor L1 is connected with the common point A, one end of the current-limiting inductor L2 is connected with the common point B, one end of the current-limiting inductor L3 is connected with the common point C, and the other ends of the current-limiting inductor L1, the current-limiting inductor L2 and the current-limiting inductor L3 are connected with the capacitor module through the common point D.
The inductance values of the current limiting inductor L1, the current limiting inductor L2, and the current limiting inductor L3 are all determined based on the fault current rise rate. If the inductance is too small, at the moment of fault occurrence, when Sa1-Sa3 is not turned off, the current rises too fast, so that the load side is damaged due to too large current, and even Sa1-Sa3 may not be turned off to cause explosion.
The first upper bridge arm, the second upper bridge arm and the third upper bridge arm respectively comprise a first full-control device and a first diode which is connected with the first full-control device in an anti-parallel mode;
the lower bridge arm of each bridge arm comprises a second diode, namely the first lower bridge arm, the second lower bridge arm and the third lower bridge arm comprise second diodes.
The first full-control device and the second full-control device are both IGBT.
The directions of the IGBTs on all the bridge arms are consistent, and the specific steps are as follows:
the collectors of the IGBTs in the first upper bridge arm, the second upper bridge arm and the third upper bridge arm are all connected with a common point M, and the anodes of the second diodes in the first lower bridge arm, the second lower bridge arm and the third lower bridge arm are all connected with a common point N;
the emitting electrode of the IGBT in the first upper bridge arm and the cathode of the second diode in the first lower bridge arm are both connected with a common point A;
the emitting electrode of the IGBT in the second upper bridge arm and the cathode of the second diode in the second lower bridge arm are both connected with a common point B;
and the emitter of the IGBT in the third upper bridge arm and the cathode of the second diode in the third lower bridge arm are both connected with a common point C.
In fig. 1, Sa1 is the IGBT of the first upper arm, Sa2 is the IGBT of the second upper arm, and Sa3 is the IGBT of the third upper arm.
The nominal capacity of the supercapacitor is determined as follows:
where C is the nominal capacity of the supercapacitor, V0Initial discharge initial voltage, V, for the super capacitorminThe voltage of the super capacitor after discharging, I is the discharge current of the super capacitor, and t is the discharge time of the super capacitor.
The common point M and the common point N form an input end of a fault current limiter, the installation position of the fault current limiter is shown in fig. 2, the input end of the fault current limiter is connected with the output end of the DC/DC converter through a triple bridge circuit, the input end of the DC/DC converter is connected with a first direct current bus, the output end of the fault current limiter is connected with a second direct current bus through a capacitor module, and the second direct current bus is connected with a load.
The first direct current bus is a high-voltage direct current bus, and the second direct current bus is a low-voltage direct current bus.
Generally, after a medium-voltage side fault of the DC/DC converter, the DC/DC converter is required to have the capability of blocking a discharge current and maintaining a capacitor voltage, and simultaneously, after the fault is isolated within a short time, rapidly starting grid-connected operation again, and it is considered that a half-bridge module is added in front of each layer of sub-modules. For the low-voltage side fault of the DC/DC converter, the DC/DC converter is required to have the function of limiting the fault current and providing the holding current for a period of time so as to ensure the fault location, and the function is difficult to realize. The fault current limiter provided by embodiment 2 of the present invention fulfills this function and is used in an ISOP-DAB type DC/DC converter.
The working principle of the fault current limiter provided by the embodiment 2 of the invention is as follows:
when the DC/DC converter normally operates, the Sa1-Sa3 is in a closed state, the super capacitor is connected in parallel in the fault current limiter, and the super capacitor is in a charged state. The current running direction is as shown in fig. 6, and the current passes through Sa1-Sa3 and L1-L3 in sequence and then flows to the load through the low-voltage direct current bus.
When the DC/DC converter fails, Sa1-Sa3 is immediately turned off, and since the current in the current-limiting inductor cannot suddenly change, the currents in L1-L3 freewheel through the diodes of the first lower arm, the second lower arm, and the third lower arm, respectively, and the current directions are as shown in fig. 7. The super capacitor is put into a discharging state, and adopts current stabilization control, and current is maintained for a period of time by utilizing follow current of the super capacitor, so that fault location is ensured.
For convenience of description, each part of the above-described apparatus is separately described as being functionally divided into various modules or units. Of course, the functionality of the various modules or units may be implemented in the same one or more pieces of software or hardware when implementing the present application.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person of ordinary skill in the art can make modifications or equivalents to the specific embodiments of the present invention with reference to the above embodiments, and such modifications or equivalents without departing from the spirit and scope of the present invention are within the scope of the claims of the present invention as set forth in the claims.
Claims (10)
1. A fault current limiter for a DC/DC converter is characterized by comprising a triplex bridge circuit, a current limiting circuit and a capacitance module which are connected;
the capacitor module comprises a switch circuit and a super capacitor which are connected in series.
2. The fault current limiter for a DC/DC converter according to claim 1, wherein the triple bridge circuit comprises three parallel-connected legs; each bridge arm comprises an upper bridge arm and a lower bridge arm.
3. The fault current limiter for a DC/DC converter according to claim 1, wherein the current limiting circuit comprises a current limiting inductor L1, a current limiting inductor L2, and a current limiting inductor L3;
one end of each of the current-limiting inductor L1, the current-limiting inductor L2 and the current-limiting inductor L3 is connected with the middle point of each of the three bridge arms, and the other end of each of the current-limiting inductor L1, the current-limiting inductor L2 and the current-limiting inductor L3 is connected with the capacitor module.
4. The fault current limiter for the DC/DC converter according to claim 3, wherein the inductance values of the current limiting inductor L1, the current limiting inductor L2 and the current limiting inductor L3 are all determined based on a fault current rise rate.
5. A fault current limiter for a DC/DC converter according to claim 2, wherein the upper leg of each leg includes a first fully controlled device and a first diode connected in anti-parallel with the first fully controlled device.
6. The fault current limiter for a DC/DC converter according to claim 5, wherein the lower leg of each leg includes a second fully controlled device and a second diode connected in anti-parallel with the second fully controlled device.
7. A fault current limiter for a DC/DC converter according to claim 5 wherein the lower of each leg includes a second diode.
8. The fault current limiter for a DC/DC converter according to claim 6, wherein the first fully controlled device and the second fully controlled device each employ an IGBT.
9. A fault current limiter for a DC/DC converter according to claim 8, wherein the IGBTs in all legs are oriented in the same direction.
10. A fault current limiter for a DC/DC converter according to claim 1, wherein the nominal capacity of the super capacitor is determined by the following equation:
where C is the nominal capacity of the supercapacitor, V0Initial discharge initial voltage, V, for the super capacitorminThe voltage of the super capacitor after discharging, I is the discharge current of the super capacitor, and t is the discharge time of the super capacitor.
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| CN112803384A (en) * | 2020-12-31 | 2021-05-14 | 国电南瑞科技股份有限公司 | Fault current limiter suitable for low-voltage direct-current system and control method |
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| CN112803384A (en) * | 2020-12-31 | 2021-05-14 | 国电南瑞科技股份有限公司 | Fault current limiter suitable for low-voltage direct-current system and control method |
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