CN110858164A - Inter-process communication method, device and computer readable medium - Google Patents
Inter-process communication method, device and computer readable medium Download PDFInfo
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- CN110858164A CN110858164A CN201810965667.3A CN201810965667A CN110858164A CN 110858164 A CN110858164 A CN 110858164A CN 201810965667 A CN201810965667 A CN 201810965667A CN 110858164 A CN110858164 A CN 110858164A
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/546—Message passing systems or structures, e.g. queues
Abstract
The application discloses a method, a device and a computer readable medium for interprocess communication, wherein the method comprises the following steps: the host writes an activation mark in a target bit corresponding to a target client in a bitmap; the target client is a client to be notified by the host in the virtual machine, and the target bit is used for indicating that the target client is the client to be notified or indicating that the target client is not the client to be notified; the host writes an interrupt command into an interrupt register; the interrupt register is a register shared by the virtual machine and the host machine, the interrupt command comprises an interrupt number, and the interrupt command is used for indicating a client corresponding to the combination of the interrupt number and the target bit to receive a message from a message receiving queue. In the application embodiment, the number of clients to be notified is indicated by the combination of the interrupt number and the bit of the bitmap in which the activation flag is written, so that the number of clients which can be supported by the Ivshmem can be greatly increased, and the implementation is simple.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a communication method, an apparatus, and a computer-readable medium.
Background
With the development of communication technology, when virtualization or cloud computing processing is performed, inter-process communication is often required between processes within an operating system, between a virtual machine/container and a virtual machine, and between a virtual machine/container and a host. The processes are programs which are loaded into the memory and executed independently, each process has own private process space, and the private process space is invisible to other processes. Interprocess communication is a mechanism for separate processes to transfer control information or exchange data with other processes. An IV share memory virtual device (ivshare memory) is a Peripheral Component Interconnect (PCI) device that shares memory inside a virtual machine. The memory sharing between the virtual machines is realized by mapping the memory into the PCI equipment of the process in the virtual machine.
The inter-process communication between the virtual machine and the host machine is mainly realized through an interrupt mechanism provided by the Ivshmem, and the user state of the host machine crosses the kernel state of the virtual machine to inform the user state process of the virtual machine. The host communicates to the virtual machines, i.e. a process in the host wants to wake up a process (client) in the virtual machine correctly, it has to distinguish which process (client) of the virtual machine the message needs to be sent to by means of recognizing an interrupt. However, the Ivshmem supports only 64 interrupts, meaning that only by virtue of the properties of the Ivshmem, the clients of the virtual machine can have only 64. With the development of virtualization technology, the number of clients in a virtual machine is increasing, and 64 interrupts are far from meeting the demand. Therefore, it is necessary to research how to solve the problem that the number of clients supported by the Ivshmem is limited.
Disclosure of Invention
The application provides a method, a device and a computer readable medium for interprocess communication, which are used for solving the problem that the number of clients supported by Ivshmem is limited.
In a first aspect, the present application provides a method for interprocess communication, including:
the host writes an activation mark in a target bit corresponding to a target client in a bitmap; the target client is a client to be notified by the host in the virtual machine, and the target bit is used for indicating that the target client is the client to be notified or indicating that the target client is not the client to be notified;
the host writes an interrupt command into an interrupt register; the interrupt register is a register shared by the virtual machine and the host machine, the interrupt command comprises an interrupt number, and the interrupt command is used for indicating a client corresponding to the combination of the interrupt number and the target bit to receive a message from a message receiving queue.
The host and the virtual machine operate in the same inter-process communication device, which may be a server, a desktop computer, a notebook computer, a mobile phone, or other devices running a host program and a virtual machine program. The execution subject of the embodiment of the application is an interprocess communication device. Optionally, the host and the virtual machine share a memory. The bitmap is located in a shared memory. That is, the bitmap may be accessible to any process in the interprocess communication device or to processes that may access the shared memory. The Ivshmem is a PCI device sharing memory inside the virtual machine, and the communication between the virtual machine and the host machine is mainly realized through an interrupt mechanism provided by the Ivshmem. However, Ivshmem only supports 64 interrupts, one for each interrupt number, and one for each client (process) within a virtual machine, meaning that only by virtue of the Ivshmem characteristics, there can be 64 clients within a virtual machine. The bitmap comprises at least two bits. The number of clients supportable by the Ivshmem can be doubled by combining the interrupt number with the bitmap. For example, Ivshmem supports 64 interrupts, the bitmap contains 64 bits, and the combination of 1 interrupt and 1 bit in the bitmap corresponds to one client, so that the combination of interrupt and bitmap corresponds to 64 × 64 clients.
In the embodiment of the application, the clients to be notified are indicated by the combination of the interrupt number and the bit of the bitmap in which the activation flag is written, so that the number of clients which can be supported by the Ivshmem can be greatly increased, and the implementation is simple.
In an optional implementation manner, the bitmap includes N bits, the target bit occupies at least one bit, the N is an integer greater than 2, and a combination of the interrupt number and the target bit corresponds to the target client.
In the implementation mode, the client to be notified is indicated through the combination of the interrupt number and the target bit, and the implementation is simple.
In an optional implementation manner, the writing, by the host, of the activation flag in the bitmap, in the target bit corresponding to the target client includes:
the host writes the activation flag in the target bit using a compare-and-swap CAS operation.
Compare and Swap (CAS) operations are atomic operations used to guarantee concurrency security. When the target bit is written into the activation mark by the host machine through CAS operation, other processes can be shielded and the bitmap can be operated at the same time, and therefore concurrency safety is guaranteed. The CAS can make atomic modifications to a single value (bit) in the bitmap, reducing the mask granularity to a large extent. In addition, the CAS operation is the operation with the minimum mask granularity, so that the time for idle bitmap can be reduced, and the use frequency of the bitmap can be improved.
In the implementation mode, the host writes the activation flag in the bitmap by adopting CAS, so that the use frequency of the bitmap is improved while the concurrency security is ensured.
In an optional implementation manner, the writing, by the host, of the activation flag in the bitmap, in the target bit corresponding to the target client includes:
and shielding the target operation of the bitmap in an interrupt shielding mode by the host machine in the process of writing the target bit corresponding to the target client in the bitmap into the activation mark, wherein the target operation is the operation except for writing the activation mark into the target bit.
In the implementation mode, the interrupt mask can be used for shielding the operation of other programs on the bitmap, so that the combination of the activation mark and the interrupt number in the bitmap can be ensured to accurately indicate the client to be notified, and the implementation is simple.
In an optional implementation manner, before the host writes the activation flag in the bitmap in the target bit corresponding to the target client, the method further includes:
and the host writes the message into the message receiving queue of the target client.
In the implementation mode, the host writes the message into the message receiving queue of the target client, and indicates the target client through the interrupt number and the target bit corresponding to the target client, so that the target client receives the message, and the implementation is simple.
In a second aspect, the present application provides another inter-process communication method, including:
the peripheral component interconnect standard PCI equipment in a kernel state of the virtual machine obtains an interrupt command in an interrupt register; the interrupt register is a register shared by the virtual machine and the host machine, the interrupt command comprises an interrupt number, the interrupt command is used for indicating a target client to receive a message from a message receiving queue, the target client is a client corresponding to a target combination in the virtual machine, and the target combination is a combination of the interrupt number and a bit of a bitmap, wherein an activation mark is written in the bit of the bitmap;
the PCI equipment reads the bitmap and determines that the target bit in the bitmap is written with the activation mark;
the PCI equipment determines the target client corresponding to the combination of the interrupt number and the target bit;
the PCI device informs the target client to receive the message from the message receive queue.
In the embodiment of the application, the PCI device corresponds to the client to be activated through the combination of the interrupt number and the bit of the bitmap in which the activation flag is written, so that the number of clients that can be supported by the Ivshmem can be greatly increased, and the implementation is simple.
In an optional implementation manner, the notifying, by the PCI device, the target client of receiving the message from the message receiving queue includes:
and the PCI equipment activates the kernel mode semaphore corresponding to the target client.
In this implementation manner, the PCI device releases the waiting state of the user mode of the target client by activating the kernel mode semaphore corresponding to the target client, so that the target client receives the message from the message receiving queue, and the implementation is simple.
In an optional implementation manner, after the PCI device notifies the target client to receive the message from the message receiving queue, the method further includes:
and the target client returns to a user state from a kernel state blocking state and receives the message from the message receiving queue.
In the implementation mode, the target client returns to the user mode from the kernel mode blocking state to activate the flow of receiving the message by the user mode, so that the message can be received in time, and the implementation is simple.
In an optional implementation manner, the bitmap includes N bits, the target bit occupies at least one bit, the N is an integer greater than 2, and a combination of the interrupt number and the target bit corresponds to the target client.
In the implementation mode, the PCI equipment indicates the client to be notified through the combination of the interrupt number and the target bit, and the implementation is simple.
In an optional implementation manner, after the PCI device reads the bitmap, the method further includes:
the PCI device clears the activation flag of the target bit with a Compare-and-Swap CAS operation.
In the implementation mode, the host machine adopts CAS to clear the activation mark in the bitmap, so that the concurrency security can be ensured, and the use frequency of the bitmap is improved.
In a third aspect, the present application provides an inter-process communication apparatus, comprising:
the writing unit is used for writing an activation mark in a target bit corresponding to a target client in the bitmap; the target client is a client to be notified by a host in the virtual machine, and the target bit is used for indicating that the target client is the client to be notified or indicating that the target client is not the client to be notified;
the writing unit is also used for writing an interrupt command into the interrupt register; the interrupt register is a register shared by the virtual machine and the host machine, the interrupt command comprises an interrupt number, and the interrupt command is used for indicating a client corresponding to the combination of the interrupt number and the target bit to receive a message from a message receiving queue.
In the embodiment of the application, the clients to be notified are indicated by the combination of the interrupt number and the bit of the bitmap in which the activation flag is written, so that the number of clients which can be supported by the Ivshmem can be greatly increased, and the implementation is simple.
In an optional implementation manner, the bitmap includes N bits, the target bit occupies at least one bit, the N is an integer greater than 2, and a combination of the interrupt number and the target bit corresponds to the target client.
In the implementation mode, the client to be notified is indicated through the combination of the interrupt number and the target bit, and the implementation is simple.
In an alternative implementation, the write unit is specifically configured to write the activation flag in the target bit using a compare-and-swap CAS.
In the implementation mode, the host writes the activation flag in the bitmap by adopting CAS, so that the use frequency of the bitmap is improved while the concurrency security is ensured.
In an optional implementation, the apparatus further comprises:
and the shielding unit is used for shielding the target operation of the bitmap in an interrupt shielding mode in the process that the host writes the activation flag into the target bit corresponding to the target client in the bitmap, wherein the target operation is the operation except for writing the activation flag into the target bit.
In the implementation mode, the interrupt mask can be used for shielding the operation of other programs on the bitmap, so that the combination of the activation mark and the interrupt number in the bitmap can be ensured to accurately indicate the client to be notified, and the implementation is simple.
In an optional implementation manner, the writing unit is further configured to write the message to the message receiving queue of the target client.
In the implementation mode, the host writes the message into the message receiving queue of the target client, and indicates the target client through the interrupt number and the target bit corresponding to the target client, so that the target client receives the message, and the implementation is simple.
Fourth aspect the present application provides another inter-process communication apparatus, comprising:
peripheral component interconnect standard PCI equipment for obtaining interrupt commands in the interrupt register; the interrupt register is a register shared by the virtual machine and the host machine, the interrupt command comprises an interrupt number, the interrupt command is used for indicating a target client to receive a message from a message receiving queue, the target client is a client corresponding to a target combination in the virtual machine, and the target combination is a combination of the interrupt number and a bit of a bitmap, wherein an activation mark is written in the bit of the bitmap;
the PCI equipment is also used for reading the bitmap and determining that the target bit in the bitmap is written with the activation mark;
the PCI equipment is also used for determining the target client corresponding to the combination of the interrupt number and the target bit;
the PCI equipment is also used for informing the target client to receive the message from the message receiving queue.
In the embodiment of the application, the PCI device corresponds to the client to be activated through the combination of the interrupt number and the bit of the bitmap in which the activation flag is written, so that the number of clients that can be supported by the Ivshmem can be greatly increased, and the implementation is simple.
In an optional implementation manner, the PCI device is specifically configured to activate a kernel mode semaphore corresponding to the target client.
In this implementation manner, the PCI device releases the waiting state of the user mode of the target client by activating the kernel mode semaphore corresponding to the target client, so that the target client receives the message from the message receiving queue, and the implementation is simple.
In an optional implementation, the apparatus further comprises:
the state switching unit is used for controlling the target client to return to a user state from a kernel state blocking state;
a receiving unit, configured to receive the message from the message receiving queue.
In the implementation mode, the target client returns to the user mode from the kernel mode blocking state to activate the flow of receiving the message by the user mode, so that the message can be received in time, and the implementation is simple.
In an optional implementation manner, the bitmap includes N bits, the target bit occupies at least one bit, the N is an integer greater than 2, and a combination of the interrupt number and the target bit corresponds to the target client.
In the implementation mode, the PCI equipment indicates the client to be notified through the combination of the interrupt number and the target bit, and the implementation is simple.
In an alternative implementation, the PCI device is further configured to clear the active flag of the target bit using a compare-and-swap CAS.
In the implementation mode, the host machine adopts CAS to clear the activation mark in the bitmap, so that the concurrency security can be ensured, and the use frequency of the bitmap is improved.
Fifth aspect an embodiment of the present application provides another interprocess communication apparatus, including a processor and a memory, where the processor and the memory are connected to each other, where the memory is used to store a computer program, and the computer program includes program instructions, and the processor is configured to call the program instructions to execute the method of the first aspect, the second aspect, any implementation manner of the first aspect, and any implementation manner of the second aspect.
In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, where the computer program includes program instructions, and the program instructions, when executed by a processor, cause the processor to perform the method of the first aspect, the second aspect, any implementation manner of the first aspect, and any implementation manner of the second aspect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the background art of the present application, the drawings required to be used in the embodiments or the background art of the present application will be described below.
Fig. 1 is a flowchart of an inter-process communication method according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a bitmap provided in an embodiment of the present application;
FIG. 3 is another interprocess communication method provided by an embodiment of the present application;
fig. 4 is a communication flow chart of a server and a client according to an embodiment of the present application;
fig. 5 is a flowchart of a method for a server to notify a client according to an embodiment of the present application;
FIG. 6 is a block diagram of an interprocess communication device according to an embodiment of the present application;
FIG. 7 is another interprocess communication apparatus provided by an embodiment of the present application;
FIG. 8 is a block diagram of another interprocess communication device provided by an embodiment of the present application;
fig. 9 is a diagram of another interprocess communication device according to an embodiment of the present application.
Detailed Description
The terminology used in the description of the embodiments section of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the present application.
The following first presents some of the terms and related knowledge that the present application relates to.
The host machine is a physical basis of the virtual machine, and the virtual machine exists in the host machine and shares hardware with the host machine. The operation of the host machine is the premise and the basis of the operation of the virtual machine. A Virtual Machine (VM) refers to a complete computer system with complete hardware system functions, which is simulated by software and runs in a completely isolated environment.
For safety, the Linux system is divided into a kernel mode and a user mode, and the kernel mode and the user mode respectively run in a kernel space and a user space. The kernel-mode program can execute privileged instructions, in which the operating system itself runs; the user mode does not allow direct access to key resources such as core data and equipment of the operating system, the key resources must be accessed only by entering the kernel mode through system call or interrupt, and when the system call or interrupt returns, the user mode returns to the user space for operation. There is only the notion of a process in user space. For a certain piece of code, it may be executed multiple times in a program, and the process of each execution is called an execution path of the code. A code segment is a critical section when two or more code paths are competing for a common resource. When a critical section is contended by multiple user-mode processes, the best approach is to protect the critical section with a semaphore. And only the process which obtains the semaphore can execute the critical section code, and when the semaphore is not obtained, the process enters a dormant state.
The Ivshmem is a PCI device sharing memory inside the virtual machine, and the communication between the virtual machine and the host machine is mainly realized through an interrupt mechanism provided by the Ivshmem. Communication from the virtual machine to the host machine can directly write an interrupt notification into a service end (server) process of the Ivshmem in the virtual machine process, call the received interrupt notification through a select system in a host machine user mode, and wake up the host machine service end to receive a message from a receiving queue (single linked list). The host machine communicates with the virtual machine, and the server needs to correctly wake up the client process in the virtual machine, so that it is necessary to distinguish to whom the message needs to be sent by identifying the interrupt, where Ivshmem only supports 64 interrupts, which means that there is a limit that the client can only have 64 interrupts only by virtue of the characteristics of the Ivshmem. It will be appreciated that the Ivshmem is used to implement the underlying implementation of interrupt notification between the host machine and the virtual machine.
The semaphore, also known as a semaphore (semaphore), is essentially a sleep lock. If a task attempts to acquire an unavailable (already occupied) semaphore, the semaphore pushes it into a wait queue and then sleeps. The processor is now free to execute other code. When the held semaphore is available (released), the task that is in the wait queue will be awakened and will get the semaphore.
The CAS operation is a mechanism to address the performance penalty of using locks in the case of multithreaded parallelism, and comprises three operands, namely a memory location (V), an expected original value (A), and a new value (B). If the value of the memory location matches the expected original value, the processor automatically updates the location value to a new value. Otherwise, the processor does nothing. In either case, it returns the value of the location prior to the CAS instruction. CAS operation effectively states "I believe that position V should contain the value A; if the value is contained, B is put in this position; otherwise, the position is not changed, and only the current value of the position is told to me. The CAS operation is an atomic operation. The atomic operation bottom is represented as a assembler instruction (ldrex, strex). The atomic operation is not interrupted by another code path during execution.
Fig. 1 is a method for inter-process communication provided by the present application, and as shown in fig. 1, the method may include:
101. and the host writes an activation mark in a target bit corresponding to the target client in the bitmap.
The target client is a client to be notified by the host in the virtual machine, and the target bit is used for indicating that the target client is the client to be notified or indicating that the target client is not the client to be notified. The host and the virtual machine operate in the same inter-process communication device, which may be a server, a desktop computer, a notebook computer, a mobile phone, or other devices running a host program and a virtual machine program. The bitmap is located in a shared memory. In this application, a client refers to a client process in a virtual machine. And when the target bit occupies one bit in the bitmap, the activation flag is 1 or 0. For example, the activation flag is 1, and the host writes the activation flag in the bitmap in the target bit corresponding to the target client, that is, writes 1 in the target bit. For another example, the activation flag is 0, and the host writes the activation flag in the bitmap in the target bit corresponding to the target client, that is, writes 0 in the target bit.
In an optional implementation manner, the bitmap includes N bits, the target bit occupies at least one bit, the N is an integer greater than 2, and a combination of the interrupt number and the target bit corresponds to the target client.
In practical applications, a combination of an interrupt number and M consecutive and non-overlapping bits in a bitmap corresponds to a client (client process) in a virtual machine, where M is an integer no less than 1. It is understood that M consecutive and non-overlapping bits in the bitmap correspond to one client (process), and M may be 1 or an integer greater than 1. That is, the target bit occupies M bits. Fig. 2 is a schematic structural diagram of a bitmap provided in an embodiment of the present application, and as shown in fig. 2, 1 bit in the bitmap corresponds to one client (process), and an activation flag is 1. As can be seen from fig. 2, the second bit of the bitmap is 1 from top to bottom, i.e., the second bit is written with the active flag, and none of the other bits are written with the active flag. For example, the bitmap contains 64 bits, and the combination of an interrupt number and 1 bit in the bitmap corresponds to one client in the virtual machine, so that one interrupt number matches the bitmap and corresponds to 64 clients. Also for example, the bitmap contains 128, and the combination of an interrupt number and 2 bits in the bitmap corresponds to one client in the virtual machine, so that an interrupt number in conjunction with the bitmap corresponds to 64 clients. In the case where the target bit occupies two bits, the activation flag may be any one of 00, 01, 10, and 11. Assuming that the activation flag is 11, the target bit occupies two bits, and the target bit write activation flag corresponding to the target client in the bitmap by the host is written in the target bit 11. In practical applications, one activation flag may occupy three or more bits, and the implementation principle is the same as the implementation principle of occupying one or two bits, and is not described in detail here.
In the implementation mode, the number of clients which can be communicated by the host can be doubled through the combination of the interrupt numbers and the target bits, and the implementation is simple.
In an optional implementation manner, the writing, by the host, of the activation flag in the bitmap, in the target bit corresponding to the target client, includes:
the host writes the active tag to the target bit using a compare-and-swap CAS operation.
When the target bit is written into the activation mark by the host machine through CAS operation, other processes can be shielded and the bitmap can be operated at the same time, and then concurrency security is guaranteed. That is, only one process is allowed to operate on the bitmap at the same time. In addition, the CAS operation is the operation with the minimum mask granularity, so that the time for idle bitmap can be reduced, and the use frequency of the bitmap can be improved. Therefore, the communication efficiency of the host and the client can be improved.
In the implementation mode, the host writes the activation flag in the bitmap by adopting CAS, so that the use frequency of the bitmap is improved while the concurrency security is ensured.
In an optional implementation manner, the writing, by the host, of the activation flag in the bitmap, in the target bit corresponding to the target client, includes:
and in the process of writing the activation flag into the target bit corresponding to the target client in the bitmap, the host masks a target operation on the bitmap in an interrupt masking mode, wherein the target operation is an operation except for writing the activation flag into the target bit.
Interrupts can be divided into two broad categories, depending on whether they can be masked: unmaskable interrupts (also called unmasked interrupts) and maskable interrupts. The CPU must respond unconditionally to a request from a non-maskable interrupt source, and may or may not respond to a request from a maskable interrupt source. For maskable interrupts, in addition to being controlled by the mask bit itself, the maskable interrupts are also controlled by an overall control, that is, an interrupt enable Flag (IF) in a CPU Flag register, where IF is 1, the CPU response can be obtained, otherwise, no response can be obtained.
In the implementation mode, the interrupt mask can be used for shielding the operation of other programs on the bitmap, so that the combination of the activation mark and the interrupt number in the bitmap can be ensured to accurately indicate the client to be notified, and the implementation is simple.
In an optional implementation manner, before the host writes the activation flag in the bitmap in the target bit corresponding to the target client, the method further includes:
and the host writes the message into the message receiving queue of the target client.
In the implementation mode, the host writes the message into the message receiving queue of the target client, and indicates the target client through the interrupt number and the target bit corresponding to the target client, so that the target client receives the message, and the implementation is simple.
102. The host writes an interrupt command into an interrupt register; the interrupt register is a register shared by the virtual machine and the host, and the interrupt command includes an interrupt number, and the interrupt command is used for instructing a client corresponding to the combination of the interrupt number and the target bit to receive a message from a message receiving queue.
In the embodiment of the application, the clients to be notified are indicated by the combination of the interrupt number and the bit of the bitmap in which the activation flag is written, so that the number of clients which can be supported by the Ivshmem can be greatly increased, and the implementation is simple.
Fig. 3 is another inter-process communication method provided in an embodiment of the present application, and as shown in fig. 3, the method may include:
301. the peripheral component interconnect standard PCI device in the kernel state of the virtual machine obtains the interrupt command in the interrupt register.
The interrupt register is a register shared by the virtual machine and the host, the interrupt command includes an interrupt number, the interrupt command is used for instructing a target client to receive a message from a message receiving queue, the target client is a client corresponding to a target combination in the virtual machine, and the target combination is a combination of the interrupt number and a bit of a bitmap, wherein an activation flag is written in the bit of the bitmap.
The PCI device may be an Ivshmem, and may provide an interrupt mechanism required to implement communication between the virtual machine and the host machine. That is, the Ivshmem, i.e., the PCI device, provides the underlying implementation for interrupt notification between the virtual machine and the host. The obtaining of the interrupt command in the interrupt register by the PCI device in the kernel-state peripheral component interconnect standard of the virtual machine may be triggering an interrupt by the PCI device, and invoking a kernel-state interrupt handling function to process the interrupt command. In practical applications, an interrupt command written by the host to the interrupt register may trigger the PCI device to execute a corresponding interrupt handler.
The bitmap occupies at least two bits corresponding to a binary sequence, for example 0000010000000000. In practical applications, a combination of an interrupt number and M bits in a bitmap corresponds to a client (client process) in a virtual machine, where M is an integer no less than 1. It will be appreciated that one activation flag occupies M bits in the bitmap. Fig. 2 is a schematic structural diagram of a bitmap provided in an embodiment of the present application, and as shown in fig. 2, 1 bit in the bitmap corresponds to one client (process). For example, the bitmap contains 64 bits, and the combination of an interrupt number and 1 bit in the bitmap corresponds to one client in the virtual machine, so that one interrupt number matches the bitmap and corresponds to 64 clients. Also for example, the bitmap contains 128, and the combination of an interrupt number and 2 bits in the bitmap corresponds to one client in the virtual machine, so that an interrupt number in conjunction with the bitmap corresponds to 64 clients. The bitmap may contain at most one activation flag. Therefore, the client to be activated can be uniquely determined by the combination of the interrupt number and the bit written with the activation mark, and the method is simple to implement. The activation flag occupies at least one bit in the bitmap. For example, the activation flag is 11, which occupies two bits, and the combination of an interrupt number and two consecutive bits in the bitmap corresponds to one client. For another example, the activation flag is 1, and occupies one bit, and the combination of one interrupt number and one bit in the bitmap corresponds to one client.
302. And the PCI equipment reads the bitmap and determines that the target bit in the bitmap is written with the activation mark.
In practical application, after obtaining the interrupt command, the PCI device reads the target bit in the bitmap, where the activation flag is written, and determines the client corresponding to the combination of the interrupt number included in the interrupt command and the target bit as the client to be activated.
303. The PCI device determines the target client corresponding to the combination of the interrupt number and the target bit.
In an optional implementation manner, the bitmap includes N bits, the target bit occupies at least one bit, the N is an integer greater than 2, and a combination of the interrupt number and the target bit corresponds to the target client.
The PCI device may store a correspondence relationship between the combination of the interrupt number and the target bit and the target client, and may determine the target client corresponding to the combination of the interrupt number and the target bit using the correspondence relationship. In practical applications, the PCI may store or obtain a one-to-one correspondence between each interrupt number and a combination of each bit in the bitmap and the client. For example, the PCI device supports 64 interrupts, the bitmap includes 64 bits, each bit corresponds to an activation flag, and the PCI device can store or retrieve from a register the correspondence between each of the 64 interrupts and the combination of each of the 64 bits and the client. That is, the PCI device stores the correspondence between 64 × 64 interrupt combinations and 64 × 64 clients. Interrupt combination refers to the combination of an interrupt number and each bit set in the bitmap corresponding to the activation flag. Assuming that an active flag occupies two consecutive bits in the bitmap, the two consecutive bits in the bitmap are a bit group corresponding to the active flag, the bitmap includes 64 bits, the bitmap includes 32 bit groups corresponding to the active flag, and an interrupt number and the bitmap can obtain 32 interrupt combinations. In practical applications, the number of clients in a virtual machine may be less than the number of interrupt combinations. For example, there are 156 clients in a virtual machine, and a PCI device supports 256 combinations of interrupts. That is, the number of PCI communicable clients is greater than the number of clients in the virtual machine.
In the implementation mode, the number of clients which can be communicated by the host can be doubled through the combination of the interrupt numbers and the target bits, and the implementation is simple.
In an optional implementation manner, after the PCI device reads the bitmap, the method further includes:
the PCI device clears the activate flag of the target bit using a Compare-and-Swap CAS operation.
In practical application, after the PCI reads the bitmap, the activation flag in the bitmap needs to be cleared, so that the host rewrites the activation flag in the bitmap to notify another client, thereby ensuring the sequential proceeding of the host to the virtual machine communication. In addition, the CAS operation is the operation with the smallest shielding granularity, and the efficiency of clearing the activation mark in the bitmap can be improved by adopting the CAS operation to clear the activation mark in the bitmap.
In the implementation mode, the host machine adopts CAS to clear the activation mark in the bitmap, so that the concurrency security can be ensured, and the use frequency of the bitmap is improved.
304. The PCI device informs the target client to receive the message from the message receiving queue.
In an optional implementation manner, the notifying, by the PCI device, the target client of the reception of the message from the message reception queue includes:
and the PCI equipment activates the kernel mode semaphore corresponding to the target client.
In this implementation manner, the PCI device releases the waiting state of the user mode of the target client by activating the kernel mode semaphore corresponding to the target client, so that the target client receives the message from the message receiving queue, and the implementation is simple.
In an optional implementation manner, after the PCI device notifies the target client to receive the message from the message receiving queue, the method further includes:
and the target client returns to a user mode from the kernel mode blocking state and receives the message from the message receiving queue.
Optionally, the target client uses a timeout waiting mechanism to sense whether the kernel state has a request (kernel state semaphore) through an ioctrl system call. If the kernel mode semaphore is activated, the target client returns to the user mode from the ioctrl block (kernel mode block state) to activate the flow of receiving the message by the user mode.
In the implementation mode, the target client returns to the user mode from the kernel mode blocking state to activate the flow of receiving the message by the user mode, so that the message can be received in time, and the implementation is simple.
In the embodiment of the application, the PCI device corresponds to the client to be activated through the combination of the interrupt number and the bit of the bitmap in which the activation flag is written, so that the number of clients that can be supported by the Ivshmem can be greatly increased, and the implementation is simple.
Fig. 4 is a communication flow diagram of a server and a client according to an embodiment of the present application, and as shown in fig. 4, the method may include:
401. the client obtains the application message.
The client is any client in the virtual machine, namely any client process. The application message is used for applying a certain service to the service terminal. The server is a server in a host machine corresponding to the virtual machine. In practical applications, the client process obtains the application message by calling a function, for example, calls shm _ allc to obtain the application information.
402. The client writes the application message into a message receiving queue of the server and writes an interrupt.
Optionally, the client atom sends the application message to a message receiving queue of the server. In practical application, a client calls a shm _ send interface atom to send an application message to a message receiving queue of a server. The operation of writing an interrupt is implemented by Ivshmem. The communication of the virtual machine to the host machine can directly write an interrupt notification in a virtual machine process (client) to a server (server process) of the Ivshmem. Since sending a message from a client to a server is a common technical means in the field, the detailed description is omitted here.
403. The server side obtains the application message in the message receiving queue.
In practical application, the server receives an interrupt notification through select system call in a host user state, wakes up the server of the host to acquire messages from a message receiving queue, or acquires the messages in the message receiving queue in a polling triggering mode.
404. And the server executes corresponding service processing according to the application message, and writes service information into the message receiving queue of the client.
The service information is obtained by the server side executing corresponding service processing according to the application message. Optionally, the service end atom sends the service information to a message receiving queue of the client. In practical application, a server side calls a shm _ send interface atom to send service information to a message receiving queue of a client side. In practical application, the server listens to the context and writes the messages in the message receiving queue into the service queue so as to execute corresponding service processing on the messages. Optionally, after the service processing is completed, the service end releases the message that the service processing is completed in the service queue.
405. And writing the activation mark into a target bit corresponding to the client in the bitmap by the server.
The target bit is used for indicating that the client is the client to be notified or indicating that the client is not the client to be notified.
406. The server writes an interrupt command to the interrupt register.
The interrupt register is a register shared by the virtual machine and the host machine, the interrupt command includes an interrupt number, and the interrupt command is used for indicating the client corresponding to the combination of the interrupt number and the target bit to receive the message from the message receiving queue.
407. The PCI device in the kernel state of the virtual machine obtains the interrupt command in the interrupt register.
The interrupt command includes an interrupt number. The bitmap includes N bits, the target bit occupies at least one bit, the N is an integer greater than 2, and a combination of the interrupt number and the target bit corresponds to the client.
408. The PCI device reads the bitmap and determines the target bit in the bitmap with the active flag written.
Optionally, after the PCI device reads the bitmap, the PCI device clears the active flag of the target bit by comparing and exchanging CAS operations.
409. And the PCI equipment determines the client corresponding to the combination of the interrupt number and the target bit.
410. And the PCI equipment activates the kernel mode semaphore corresponding to the client.
411. And the client returns to the user mode from the blocking state of the kernel mode and receives the service information from the message receiving queue.
Optionally, the client uses a timeout waiting mechanism to sense whether the kernel state has a request (kernel state semaphore) through an ioctrl system call. If the kernel mode semaphore is activated, the client returns to the user mode from the ioctrl block (kernel mode block state) to activate the flow of receiving messages by the user mode.
412. And the client processes the service information.
In the embodiment of the application, the PCI device corresponds to the client to be activated through the combination of the interrupt number and the bit of the bitmap in which the activation flag is written, so that the number of clients that can be supported by the Ivshmem can be greatly increased, and the implementation is simple.
Fig. 5 is a flowchart of a method for a server to notify a client according to an embodiment of the present application, and as shown in fig. 5, the method may include:
501. and the host writes an activation mark in a target bit corresponding to the target client in the bitmap.
And the target client is a client to be notified in the virtual machine corresponding to the host. For example, the second bit from top to bottom in the bitmap is the target bit, as shown in fig. 5.
502. The host writes an interrupt notification to the interrupt register via the Ivshmem.
The interrupt notification is the above-mentioned interrupt command. The interrupt notification includes an interrupt number. The interrupt register is a register shared by the host machine and the virtual machine.
503. And the interrupt processing unit of the kernel state of the virtual machine acquires the interrupt notification through the Ivshmem and determines an interrupt number contained in the interrupt notification.
In practical applications, the interrupt handling unit may be a hardware unit or a software unit, that is, a piece of code executed by the virtual machine, such as an interrupt handling function.
504. And the interrupt processing unit reads the bitmap and determines the client corresponding to the combination of the target bit written with the activation mark and the interrupt number in the bitmap.
In practical application, the virtual machine may implement the following operations when executing the interrupt processing function in the kernel state: and determining the client corresponding to the combination of the interrupt number and the target bit written with the activation mark in the bitmap, reading the bitmap and determining the interrupt notification.
505. And the interrupt processing unit activates the kernel mode semaphore corresponding to the target client.
In the embodiment of the application, the host indicates the client to be activated through the combination of the interrupt number and the bit of the bitmap with the activation flag, so as to accurately notify the client to be activated, thereby greatly expanding the number of clients which can be supported by the Ivshmem, and the implementation is simple. Client 2 in fig. 5 is the target client.
Fig. 6 is a flowchart of an inter-process communication apparatus according to an embodiment of the present application, where the apparatus includes:
a writing unit 601, configured to write an activation flag in a bitmap in a target bit corresponding to a target client; the target client is a client to be notified by a host in a virtual machine, and the target bit is used for indicating that the target client is the client to be notified or indicating that the target client is not the client to be notified;
the writing unit 601 is further configured to write an interrupt command into the interrupt register; the interrupt register is a register shared by the virtual machine and the host, and the interrupt command includes an interrupt number, and the interrupt command is used for instructing a client corresponding to the combination of the interrupt number and the target bit to receive a message from a message receiving queue.
In the embodiment of the application, the clients to be notified are indicated by the combination of the interrupt number and the bit of the bitmap in which the activation flag is written, so that the number of clients which can be supported by the Ivshmem can be greatly increased, and the implementation is simple.
In an optional implementation manner, the bitmap includes N bits, the target bit occupies at least one bit, the N is an integer greater than 2, and a combination of the interrupt number and the target bit corresponds to the target client.
In the implementation mode, the client to be notified is indicated through the combination of the interrupt number and the target bit, and the implementation is simple.
In an alternative implementation, the writing unit 601 is specifically configured to write the activation flag in the target bit by using a compare-and-swap CAS.
In the implementation mode, the host writes the activation flag in the bitmap by adopting CAS, so that the use frequency of the bitmap is improved while the concurrency security is ensured.
In an optional implementation manner, the apparatus further includes:
a masking unit 602, configured to mask, in a process that the host writes the activation flag into the target bit corresponding to the target client in the bitmap, a target operation on the bitmap in a manner of interrupt masking, where the target operation is an operation other than writing the activation flag into the target bit.
In the implementation mode, the interrupt mask can be used for shielding the operation of other programs on the bitmap, so that the combination of the activation mark and the interrupt number in the bitmap can be ensured to accurately indicate the client to be notified, and the implementation is simple.
In an optional implementation manner, the writing unit 601 is further configured to write the message into the message receiving queue of the target client.
In the implementation mode, the host writes the message into the message receiving queue of the target client, and indicates the target client through the interrupt number and the target bit corresponding to the target client, so that the target client receives the message, and the implementation is simple.
Fig. 7 is a flowchart of an inter-process communication apparatus according to an embodiment of the present application, where the apparatus includes:
a peripheral component interconnect standard PCI device 701 for obtaining an interrupt command in an interrupt register; the interrupt register is a register shared by a virtual machine and a host machine, the interrupt command comprises an interrupt number, the interrupt command is used for indicating a target client to receive a message from a message receiving queue, the target client is a client corresponding to a target combination in the virtual machine, and the target combination is a combination of the interrupt number and a bit of a bitmap, wherein an activation flag is written in the bit of the bitmap;
the PCI device 701 is further configured to read the bitmap, and determine that the target bit in the bitmap is written with the activation flag;
the PCI device 701 is further configured to determine the target client corresponding to the combination of the interrupt number and the target bit;
the PCI device 701 is further configured to notify the target client to receive the message from the message receiving queue.
In the embodiment of the application, the PCI device corresponds to the client to be activated through the combination of the interrupt number and the bit of the bitmap in which the activation flag is written, so that the number of clients that can be supported by the Ivshmem can be greatly increased, and the implementation is simple.
In an optional implementation manner, the PCI device 701 is specifically configured to activate a kernel mode semaphore corresponding to the target client.
In this implementation manner, the PCI device releases the waiting state of the user mode of the target client by activating the kernel mode semaphore corresponding to the target client, so that the target client receives the message from the message receiving queue, and the implementation is simple.
In an optional implementation manner, the apparatus further includes:
a state switching unit 702, configured to control the target client to return to the user state from the kernel state blocking state;
a receiving unit 703 is configured to receive the message from the message receiving queue.
In the implementation mode, the target client returns to the user mode from the kernel mode blocking state to activate the flow of receiving the message by the user mode, so that the message can be received in time, and the implementation is simple.
In an optional implementation manner, the bitmap includes N bits, the target bit occupies at least one bit, the N is an integer greater than 2, and a combination of the interrupt number and the target bit corresponds to the target client.
In the implementation mode, the PCI equipment indicates the client to be notified through the combination of the interrupt number and the target bit, and the implementation is simple.
In an alternative implementation, the PCI device 701 is further configured to clear the active flag of the target bit using a compare-and-swap CAS.
In the implementation mode, the host machine adopts CAS to clear the activation mark in the bitmap, so that the concurrency security can be ensured, and the use frequency of the bitmap is improved.
Fig. 8 is a schematic structural diagram of another interprocess communication apparatus provided in the embodiment of the present application. As shown in fig. 8, the inter-process communication means may include: one or more processors 801 and memory 802. The processor 801 and the memory 802 are connected by a bus 803. The memory 802 is used to store instructions and the processor 801 is used to execute instructions stored by the memory 802. The processor runs a host program and a virtual machine program. The host machine and the virtual machine operated by the processor are communicated in a memory sharing mode. Wherein the processor 801 is configured to implement the following operations: the host writes an activation mark in a target bit corresponding to a target client in a bitmap; the target client is a client to be notified by a host in a virtual machine, and the target bit is used for indicating that the target client is the client to be notified or indicating that the target client is not the client to be notified; writing an interrupt command to an interrupt register; the interrupt register is a register shared by the virtual machine and the host, and the interrupt command includes an interrupt number, and the interrupt command is used for instructing a client corresponding to the combination of the interrupt number and the target bit to receive a message from a message receiving queue.
Alternatively, the processor 801 is configured to implement the following operations: the peripheral component interconnect standard PCI equipment in a kernel state of the virtual machine obtains an interrupt command in an interrupt register; the interrupt register is a register shared by the virtual machine and the host, the interrupt command includes an interrupt number, the interrupt command is used for instructing a target client to receive a message from a message receiving queue, the target client is a client corresponding to a target combination in the virtual machine, and the target combination is a combination of the interrupt number and a bit of a bitmap, wherein an activation flag is written in the bit of the bitmap; the PCI equipment reads the bitmap and determines that the target bit in the bitmap is written with the activation mark; the PCI equipment determines the target client corresponding to the combination of the interrupt number and the target bit; the PCI device informs the target client to receive the message from the message receiving queue.
It should be understood that in the embodiments of the present Application, the Processor 801 may be a Central Processing Unit (CPU), and the Processor may be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The functions of the writing unit 601, the masking unit 602, the state switching unit 702, and the receiving unit 703 may be implemented by the processor 801.
The memory 802 may include both read-only memory and random access memory, and provides instructions and data to the processor 801. A portion of the memory 802 may also include non-volatile random access memory.
Fig. 9 is a schematic diagram of another inter-process communication apparatus 900, which may have a relatively large difference due to different configurations or performances, according to an embodiment of the present application, and may include one or more Central Processing Units (CPUs) 922 (e.g., one or more processors) and a memory 932, and one or more storage media 930 (e.g., one or more mass storage devices) for storing applications 942 or data 944. Memory 932 and storage media 930 can be, among other things, transient storage or persistent storage. The processor 922 runs a host program and a virtual machine program. The program stored on the storage medium 930 may include one or more modules (not shown), each of which may include a series of instructions operating on an interprocess communication means. Still further, a central processor 922 may be provided in communication with the storage medium 930 to execute a series of instruction operations in the storage medium 930 on the interprocess communication apparatus 900.
The interprocess communication device 900 may also include one or more power supplies 926, one or more wired or wireless network interfaces 950, one or more input-output interfaces 958, and/or one or more operating systems 941, such as Windows Server, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.
In an embodiment of the present invention, there is provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements: the host writes an activation mark in a target bit corresponding to a target client in a bitmap; the target client is a client to be notified by a host in a virtual machine, and the target bit is used for indicating that the target client is the client to be notified or indicating that the target client is not the client to be notified; writing an interrupt command to an interrupt register; the interrupt register is a register shared by the virtual machine and the host, and the interrupt command includes an interrupt number, and the interrupt command is used for instructing a client corresponding to the combination of the interrupt number and the target bit to receive a message from a message receiving queue.
In another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, which when executed by a processor implements: the peripheral component interconnect standard PCI equipment in a kernel state of the virtual machine obtains an interrupt command in an interrupt register; the interrupt register is a register shared by the virtual machine and the host, the interrupt command includes an interrupt number, the interrupt command is used for instructing a target client to receive a message from a message receiving queue, the target client is a client corresponding to a target combination in the virtual machine, and the target combination is a combination of the interrupt number and a bit of a bitmap, wherein an activation flag is written in the bit of the bitmap; the PCI equipment reads the bitmap and determines that the target bit in the bitmap is written with the activation mark; the PCI equipment determines the target client corresponding to the combination of the interrupt number and the target bit; the PCI device informs the target client to receive the message from the message receiving queue.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (20)
1. An interprocess communication method, comprising:
the host writes an activation mark in a target bit corresponding to a target client in a bitmap; the target client is a client to be notified by the host in the virtual machine, and the target bit is used for indicating that the target client is the client to be notified or indicating that the target client is not the client to be notified;
the host writes an interrupt command into an interrupt register; the interrupt register is a register shared by the virtual machine and the host machine, the interrupt command comprises an interrupt number, and the interrupt command is used for indicating a client corresponding to the combination of the interrupt number and the target bit to receive a message from a message receiving queue.
2. The method of claim 1, wherein the bitmap comprises N bits, wherein the target bit occupies at least one bit, wherein N is an integer greater than 2, and wherein the combination of the interrupt number and the target bit corresponds to the target client.
3. The method according to claim 1 or 2, wherein writing the activation flag in the bitmap by the host in the target bit corresponding to the target client comprises:
the host writes the activation flag in the target bit using a compare-and-swap CAS operation.
4. The method of claim 3, wherein the host writes the activation flag in the bitmap in a target bit corresponding to the target client, and wherein the method further comprises:
and the host writes the message into the message receiving queue of the target client.
5. An interprocess communication method, comprising:
the peripheral component interconnect standard PCI equipment in a kernel state of the virtual machine obtains an interrupt command in an interrupt register; the interrupt register is a register shared by the virtual machine and the host machine, the interrupt command comprises an interrupt number, the interrupt command is used for indicating a target client to receive a message from a message receiving queue, the target client is a client corresponding to a target combination in the virtual machine, and the target combination is a combination of the interrupt number and a bit of a bitmap, wherein an activation mark is written in the bit of the bitmap;
the PCI equipment reads the bitmap and determines that the target bit in the bitmap is written with the activation mark;
the PCI equipment determines the target client corresponding to the combination of the interrupt number and the target bit;
the PCI device informs the target client to receive the message from the message receive queue.
6. The method of claim 5, wherein the PCI device notifying the target client to receive the message from the message receive queue comprises:
and the PCI equipment activates the kernel mode semaphore corresponding to the target client.
7. The method of claim 6, wherein after the PCI device notifies the target client to receive the message from the message receive queue, the method further comprises:
and the target client returns to a user state from a kernel state blocking state and receives the message from the message receiving queue.
8. The method according to any of claims 5 to 7, wherein the bitmap comprises N bits, the target bit occupies at least one bit, N is an integer greater than 2, and the combination of the interrupt number and the target bit corresponds to the target client.
9. The method of claim 8, wherein after the PCI device reads the bitmap, the method further comprises:
the PCI device clears the activation flag of the target bit with a Compare-and-Swap CAS operation.
10. An interprocess communication apparatus, comprising:
the writing unit is used for writing an activation mark in a target bit corresponding to a target client in the bitmap; the target client is a client to be notified by a host in the virtual machine, and the target bit is used for indicating that the target client is the client to be notified or indicating that the target client is not the client to be notified;
the writing unit is also used for writing an interrupt command into the interrupt register; the interrupt register is a register shared by the virtual machine and the host machine, the interrupt command comprises an interrupt number, and the interrupt command is used for indicating a client corresponding to the combination of the interrupt number and the target bit to receive a message from a message receiving queue.
11. The apparatus of claim 10, wherein the bitmap comprises N bits, wherein the target bit occupies at least one bit, wherein N is an integer greater than 2, and wherein the combination of the interrupt number and the target bit corresponds to the target client.
12. The apparatus of claim 10 or 11,
the write unit is specifically configured to write the activation flag in the target bit using a compare-and-swap CAS operation.
13. The apparatus of claim 12,
the writing unit is further configured to write the message into the message receiving queue of the target client.
14. An interprocess communication apparatus, comprising:
peripheral component interconnect standard PCI equipment for obtaining interrupt commands in the interrupt register; the interrupt register is a register shared by the virtual machine and the host machine, the interrupt command comprises an interrupt number, the interrupt command is used for indicating a target client to receive a message from a message receiving queue, the target client is a client corresponding to a target combination in the virtual machine, and the target combination is a combination of the interrupt number and a bit of a bitmap, wherein an activation mark is written in the bit of the bitmap;
the PCI equipment is also used for reading the bitmap and determining that the target bit in the bitmap is written with the activation mark;
the PCI equipment is also used for determining the target client corresponding to the combination of the interrupt number and the target bit;
the PCI equipment is also used for informing the target client to receive the message from the message receiving queue.
15. The apparatus of claim 14,
the PCI device is specifically configured to activate a kernel mode semaphore corresponding to the target client.
16. The apparatus of claim 15, further comprising:
the state switching unit is used for controlling the target client to return to a user state from a kernel state blocking state;
a receiving unit, configured to receive the message from the message receiving queue.
17. The apparatus of any one of claims 14 to 16, wherein the bitmap comprises N bits, the target bit occupies at least one bit, N is an integer greater than 2, and a combination of the interrupt number and the target bit corresponds to the target client.
18. The apparatus of claim 17,
the PCI device is further configured to clear the activation flag of the target bit using a compare-and-swap CAS operation.
19. An interprocess communication apparatus comprising a processor and a memory, which are interconnected, wherein said memory is adapted to store a computer program comprising program instructions, and wherein said processor is configured to invoke said program instructions to perform the method according to any of claims 1-9.
20. A computer-readable storage medium, characterized in that the computer storage medium stores a computer program comprising program instructions that, when executed by a processor, cause the processor to perform the method according to any of claims 1-10.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112181877A (en) * | 2020-10-28 | 2021-01-05 | 瑞芯微电子股份有限公司 | Display frequency conversion method and system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0355653A (en) * | 1989-06-16 | 1991-03-11 | Internatl Business Mach Corp <Ibm> | System and method for interrupt processing |
| CN101093449A (en) * | 2007-06-22 | 2007-12-26 | 浙江大学 | System of virtual machine based on virtualizing technique of processor, and implementation method |
| CN103150203A (en) * | 2013-03-29 | 2013-06-12 | 北京奇虎科技有限公司 | Virtual machine control system, virtual machine controller and control method |
| CN104123173A (en) * | 2014-07-22 | 2014-10-29 | 华为技术有限公司 | Method and device for achieving communication between virtual machines |
| CN104484219A (en) * | 2014-11-24 | 2015-04-01 | 北京奇虎科技有限公司 | Strategy issuing method and device in virtual platform |
| CN106775919A (en) * | 2015-11-24 | 2017-05-31 | 龙芯中科技术有限公司 | Status information control method and device |
-
2018
- 2018-08-22 CN CN201810965667.3A patent/CN110858164B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0355653A (en) * | 1989-06-16 | 1991-03-11 | Internatl Business Mach Corp <Ibm> | System and method for interrupt processing |
| CN101093449A (en) * | 2007-06-22 | 2007-12-26 | 浙江大学 | System of virtual machine based on virtualizing technique of processor, and implementation method |
| CN103150203A (en) * | 2013-03-29 | 2013-06-12 | 北京奇虎科技有限公司 | Virtual machine control system, virtual machine controller and control method |
| CN104123173A (en) * | 2014-07-22 | 2014-10-29 | 华为技术有限公司 | Method and device for achieving communication between virtual machines |
| CN104484219A (en) * | 2014-11-24 | 2015-04-01 | 北京奇虎科技有限公司 | Strategy issuing method and device in virtual platform |
| CN106775919A (en) * | 2015-11-24 | 2017-05-31 | 龙芯中科技术有限公司 | Status information control method and device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112181877A (en) * | 2020-10-28 | 2021-01-05 | 瑞芯微电子股份有限公司 | Display frequency conversion method and system |
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