CN110853512A - Display device and display panel thereof - Google Patents
Display device and display panel thereof Download PDFInfo
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- CN110853512A CN110853512A CN201911095272.3A CN201911095272A CN110853512A CN 110853512 A CN110853512 A CN 110853512A CN 201911095272 A CN201911095272 A CN 201911095272A CN 110853512 A CN110853512 A CN 110853512A
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Abstract
The invention provides a display device and a display panel thereof, wherein the display panel comprises: a plurality of first sub-pixels and a first pixel driving circuit for driving each first sub-pixel, and a plurality of second sub-pixels and a second pixel driving circuit for driving each second sub-pixel; the first pixel driving circuit corresponding to the first sub-pixel and the second pixel driving circuit corresponding to the second sub-pixel in the same row share the same scanning signal through the first inverter. The common scanning signal can realize the synchronous driving of the first sub-pixel and the second sub-pixel, and the display effect of the full-face screen is improved. The synchronous driving of the first sub-pixel and the second sub-pixel can use the same GIP circuit, and the structure is simple and the cost is low.
Description
Technical Field
The invention relates to the technical field of display equipment, in particular to a display device and a display panel thereof.
Background
Along with the rapid development of display devices, the requirement of users on screen occupation ratio is higher and higher, and elements such as a camera, a sensor and an earphone need to be installed above a screen, so that a part of area is reserved above the screen in the prior art for installing the elements, for example, the area of the front bang of iphoneX of an apple mobile phone, which affects the overall consistency of the screen, and the full-screen display is concerned more and more by the industry.
Disclosure of Invention
The invention aims to provide a display device for a full-face screen and a display panel thereof.
To achieve the above object, a first aspect of the present invention provides a display panel comprising: a plurality of first sub-pixels and a first pixel driving circuit for driving each of the first sub-pixels, and a plurality of second sub-pixels and a second pixel driving circuit for driving each of the second sub-pixels; the first pixel driving circuit corresponding to the first sub-pixel and the second pixel driving circuit corresponding to the second sub-pixel in the same row share the same scanning signal through a first inverter.
Optionally, the display panel includes: a transparent display area and a non-transparent display area; the first sub-pixel and the first pixel driving circuit are positioned in the transparent display area; the second sub-pixel and the second pixel driving circuit are located in the non-transparent display area.
Optionally, the first inverter is located in the non-transparent display area.
Optionally, the display panel further includes a frame region, and the first inverter is located in the frame region.
Optionally, the first inverter includes a first N-type transistor and a first P-type transistor, and a gate of the first N-type transistor is connected to a gate of the first P-type transistor, and is configured to input the scan signal; a first pole of the first N-type transistor is connected with a low level, and a second pole of the first P-type transistor is connected with a high level; the second pole of the first N-type transistor is connected to the first pole of the first P-type transistor and is used for outputting an inverted signal of the scanning signal.
Optionally, the first P-type transistor is a low temperature polysilicon transistor, and the first N-type transistor is a low temperature polysilicon oxide transistor.
Optionally, the first pixel driving circuit comprises a first switching transistor, the second pixel driving circuit comprises a second switching transistor, and the first switching transistor and the second switching transistor are opposite in conductivity type; the first pixel driving circuit and the second pixel driving circuit respectively corresponding to the first sub-pixel and the second sub-pixel in the same row share the same scanning signal through a first inverter.
Optionally, the second switch transistor is a third P-type transistor, and the first switch transistor is a third N-type transistor.
Optionally, the third P-type transistor is a low temperature polysilicon transistor, and the third N-type transistor is a low temperature polysilicon oxide transistor.
Optionally, the first pixel driving circuit further comprises a first light emitting transistor, the second pixel driving circuit further comprises a second light emitting transistor, and the conductivity types of the first light emitting transistor and the second light emitting transistor are opposite; the first light emitting transistor and the second light emitting transistor respectively corresponding to the first sub-pixel and the second sub-pixel in the same row share the same light emitting signal through the second inverter.
Optionally, the second inverter is located in the non-transparent display area.
Optionally, the display panel further includes a frame region, and the second inverter is located in the frame region.
Optionally, the second inverter includes a second N-type transistor and a second P-type transistor, and a gate of the second N-type transistor is connected to a gate of the second P-type transistor, and is configured to input the light emitting signal; the first pole of the second N-type transistor is connected with a low level, and the second pole of the second P-type transistor is connected with a high level; the second pole of the second N-type transistor is connected to the first pole of the second P-type transistor and is used for outputting an inverted signal of the light-emitting signal.
Optionally, the second P-type transistor is a low temperature polysilicon transistor, and the second N-type transistor is a low temperature polysilicon oxide transistor.
Optionally, the first pixel driving circuit further includes a first driving transistor, the first switching transistor is one of a low-temperature polysilicon transistor and a low-temperature polysilicon oxide transistor, and the first driving transistor is the other of the low-temperature polysilicon transistor and the low-temperature polysilicon oxide transistor.
Optionally, the first pixel driving circuit further includes a first light emitting transistor, and the first light emitting transistor is a low temperature polysilicon transistor or a low temperature polysilicon oxide transistor.
Optionally, the first sub-pixel comprises: a first electrode, a first light emitting structure block positioned on the first electrode, and a second electrode positioned on the first light emitting structure block; the first electrode is a counter electrode; the orthographic projection of the low-temperature polycrystalline oxide transistor and the low-temperature polycrystalline silicon transistor on the display panel is at least partially overlapped with the orthographic projection of the first electrode on the display panel.
Optionally, the low-temperature polysilicon transistor is of a top gate structure or a bottom gate structure; and/or the low-temperature polycrystalline oxide transistor is of a top gate structure or a bottom gate structure.
Optionally, the first pixel driving circuit has a 2T1C or 3T1C structure, and the second pixel driving circuit has a 6T1C or 7T1C structure.
A second aspect of the present invention provides a display device comprising:
an apparatus body having a device region;
and the display panel of any one of the above, cover on the said apparatus body;
the device area is located below a transparent display area of the display panel, and a photosensitive device which penetrates through the transparent display area to emit or collect light is arranged in the device area.
Optionally, the photosensitive device comprises: at least one of a camera, an infrared sensor, an infrared lens, a floodlight sensing element, an ambient light sensor and a dot matrix projector.
Compared with the prior art, the invention has the beneficial effects that:
1) in the display panel, the first pixel driving circuit corresponding to the first sub-pixel and the second pixel driving circuit corresponding to the second sub-pixel in the same row share the same scanning signal through the first inverter, and through the first inverter, the first sub-pixel and the second sub-pixel can use the same GIP (Gate in panel technology) circuit in synchronous driving, so that the use of a complex structure is avoided, and the cost is low.
2) In an alternative scheme, the first pixel driving circuit comprises a first switching transistor, the second pixel driving circuit comprises a second switching transistor, and a scanning signal is switched in the second switching transistor of the second sub-pixel in the same row due to the fact that the first switching transistor of the first sub-pixel in the same row is opposite to the second switching transistor of the second sub-pixel in the same row in conduction type; obtaining an inverted signal of the scanning signal through a first inverter, and accessing a first switching transistor of a first sub-pixel positioned in the same row; the synchronous driving of the first sub-pixel and the second sub-pixel can be realized, and the display effect of the full-face screen is improved. In addition, the synchronous driving of the first sub-pixel and the second sub-pixel can use the same GIP (Gate in panel technology) circuit, thereby avoiding the use of a complex structure and having lower cost.
3) In an alternative, the display panel includes: a transparent display area and a non-transparent display area; the first sub-pixel and the first pixel driving circuit are positioned in the transparent display area; the second sub-pixel and the second pixel driving circuit are located in the non-transparent display area. A scanning signal is connected to a second switching transistor of a second sub-pixel positioned in the same row in the non-transparent display area; obtaining an inverted signal of the scanning signal through a first inverter, and accessing the inverted signal to a first switching transistor of a first sub-pixel positioned in the same row in the transparent display area; the synchronous driving of the transparent display area and the non-transparent display area can be realized, and the display effect of the whole screen is improved. In addition, the same GIP (Gate in panel technology) circuit can be used for synchronous driving of the transparent display area and the non-transparent display area, so that the complex structure is avoided, and the cost is low.
4) In an alternative, the first inverter is located in the non-transparent display area. In other alternatives, the first inverter may be located in the transparent display region, or in a transitional display region between the transparent display region and the non-transparent display region. The first phase inverter is arranged in the non-transparent display area or the transition display area, and compared with the transparent display area, the light transmittance of the transparent display area can be prevented from being reduced.
5) In an alternative, the display panel further comprises a frame region, and the first inverter is located in the frame region. The first inverter is arranged in the frame area, and the layout of each second sub-pixel in the non-transparent display area can be prevented from being changed and the pixel density (PPI) of the second sub-pixels can be prevented from being reduced compared with the non-transparent display area.
6) In an alternative scheme, the first inverter comprises a first N-type transistor and a first P-type transistor, and the grid electrode of the first N-type transistor is connected with the grid electrode of the first P-type transistor and used for inputting scanning signals; the first pole of the first N-type transistor is connected with a low level, and the second pole of the first P-type transistor is connected with a high level; the second pole of the first N-type transistor is connected to the first pole of the first P-type transistor and used for outputting an inverted signal of the scanning signal. When the scanning signal is at a high level, the first N-type transistor is turned on, the first P-type transistor is turned off, the first pole and the second pole of the first N-type transistor are conducted, and a low level is output as an inverted signal of the scanning signal. When the scanning signal is at low level, the first P-type transistor is turned on, the first N-type transistor is turned off, the first pole and the second pole of the first P-type transistor are conducted, and the high level is output as the inverted signal of the scanning signal. Compared with inverters with other structures, the inverter is simple in structure and reliable in performance.
7) In an alternative scheme, the first pixel driving circuit further comprises a first light emitting transistor, the second pixel driving circuit further comprises a second light emitting transistor, and the conductivity types of the first light emitting transistor and the second light emitting transistor are opposite; the first light emitting transistor and the second light emitting transistor respectively corresponding to the first sub-pixel and the second sub-pixel in the same row share the same light emitting signal through the second inverter. Connecting a light-emitting signal to a second light-emitting transistor of a second sub-pixel positioned in the same row; obtaining an inverted signal of the luminescent signal through a second inverter, and accessing a first luminescent transistor of a first sub-pixel positioned in the same row; the synchronous light emission of the first sub-pixel and the second sub-pixel can be realized, and the display effect of the full-face screen is improved.
When the first sub-pixel and the first pixel driving circuit are located in the transparent display area, and the second sub-pixel and the second pixel driving circuit are located in the non-transparent display area: connecting a light-emitting signal to a second light-emitting transistor of a second sub-pixel positioned in the same row in the non-transparent display area; obtaining an inverted signal of the luminescent signal through a second inverter, and accessing the first luminescent transistor of the first sub-pixel positioned in the same row in the transparent display area; synchronous light emission of the transparent display area and the non-transparent display area can be realized.
In other alternatives, the conductivity types of the first light emitting transistor and the second light emitting transistor may also be the same, and the first light emitting transistor and the second light emitting transistor respectively corresponding to the first sub-pixel and the second sub-pixel in the same row directly share the same light emitting signal.
8) In an alternative, the second inverter is located in the non-transparent display area. In other alternatives, the second inverter may be located in the transparent display region, or in a transitional display region between the transparent display region and the non-transparent display region. The second inverter is arranged in the non-transparent display area or the transition display area, and compared with the transparent display area, the light transmittance of the transparent display area can be prevented from being reduced.
9) In an alternative, the display panel further comprises a frame area, and the second inverter is located in the frame area. The second inverter is disposed in the frame region, and can avoid changing the layout of each second sub-pixel in the non-transparent display region and reducing the pixel density (PPI) of the second sub-pixels, as compared with the non-transparent display region.
10) In an alternative scheme, the second inverter comprises a second N-type transistor and a second P-type transistor, and the grid electrode of the second N-type transistor is connected with the grid electrode of the second P-type transistor and used for inputting the light-emitting signal; the first pole of the second N-type transistor is connected with the low level, and the second pole of the second P-type transistor is connected with the high level; the second pole of the second N-type transistor is connected with the first pole of the second P-type transistor and used for outputting an inverted signal of the light-emitting signal. When the light-emitting signal is at a high level, the second N-type transistor is turned on, the second P-type transistor is turned off, the first pole and the second pole of the second N-type transistor are conducted, and a low level is output as an inverted signal of the light-emitting signal. When the light-emitting signal is at a low level, the second P-type transistor is turned on, the second N-type transistor is turned off, the first pole and the second pole of the second P-type transistor are conducted, and the high level is output as an inverted signal of the light-emitting signal. Compared with inverters with other structures, the inverter is simple in structure and reliable in performance.
Drawings
Fig. 1 is a top view of a display panel according to a first embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a portion of the area of FIG. 1;
fig. 3 is a circuit diagram of a first pixel driving circuit of a 2T1C configuration;
fig. 4 is a circuit diagram of a second pixel driving circuit of a 7T1C configuration;
FIG. 5 is a circuit diagram of a first inverter;
FIG. 6 is a top view of a display panel according to a second embodiment of the present invention;
fig. 7 is a circuit diagram of a first pixel driving circuit of a 3T1C configuration.
To facilitate an understanding of the invention, all reference numerals appearing in the invention are listed below:
Transparent display region 1a non-transparent display region 1b
First sub-pixel 11 first switching transistor X1
Second switching transistor of second sub-pixel 21, first sub-transistor M1
First electrode 11a of first inverter 31
PDL first light emitting structure block 11b of pixel definition layer
The first storage capacitor C scans the signal lines Sn-1, Sn
Data signal line VData power signal line VDD
Inverse signal of scanning signal
First N-type transistor 311
The first P-type transistor 312 has a low level VGL
High-level VGH low-temperature polysilicon semiconductor active layer 121
First gate insulating layer 122 first gate 123
Second gate insulating layer 132 of low temperature poly-crystalline oxide semiconductor active layer 131
The first light emitting transistor X3 light emitting signal line EMn
Second storage capacitor C' second sub-transistor M2
Third sub-transistor M3 fourth sub-transistor M4
Fifth sub-transistor M5 sixth sub-transistor, second light emitting transistor M6
Initial voltage signal line Vinit of seventh sub-transistor and second driving transistor M7
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a plan view of a display panel according to a first embodiment of the present invention. Fig. 2 is a schematic cross-sectional structure of a part of the region in fig. 1. Fig. 3 is a circuit diagram of a first pixel driving circuit of a 2T1C configuration. Fig. 4 is a circuit diagram of a second pixel driving circuit of a 7T1C configuration.
Referring to fig. 1 to 4, a display panel 1 includes: a plurality of first sub-pixels 11 and a first pixel driving circuit for driving each first sub-pixel 11, and a plurality of second sub-pixels 21 and a second pixel driving circuit for driving each second sub-pixel 21; the first pixel driving circuit corresponding to the first sub-pixel 11 located in the same row and the second pixel driving circuit corresponding to the second sub-pixel 21 share the same scanning signal through the first inverter 31.
Optionally, the first pixel driving circuit comprises a first switching transistor X1, the second pixel driving circuit comprises a second switching transistor M1, and the first switching transistor X1 and the second switching transistor M1 are of opposite conductivity types; the first switching transistor X1 corresponding to the first sub-pixel 11 and the second switching transistor M1 corresponding to the second sub-pixel 21 in the same row share the same scan signal through the first inverter 31.
Referring to fig. 2, the display panel 1 includes: a transparent display region 1a and a non-transparent display region 1 b; the transparent display area 1a includes a plurality of first sub-pixels 11 and a first pixel driving circuit for driving each of the first sub-pixels 11; the non-transparent display region 1b includes a plurality of second sub-pixels 21 and a second pixel driving circuit for driving each of the second sub-pixels 21.
The substrate 10 of the transparent display area 1a has a first electrode 11a, and the first electrode 11a and the substrate 10 not covered by the first electrode 11a are provided with a pixel definition layer PDL; the pixel defining layer PDL has an opening exposing a partial region of the first electrode 11a, the first light emitting structure block 11b is disposed in the opening, and the second electrode 11c is disposed on the first light emitting structure block 11b and the pixel defining layer PDL. The first electrode 11a, the first light-emitting structure block 11b, and the second electrode 11c constitute a first subpixel 11. The first light emitting structure piece 11b may be red, green or blue, and may also be red, green, blue or yellow. The first sub-pixel 11 of the three primary colors of red, green and blue or the four primary colors of red, green, blue and yellow constitutes a first pixel unit. The first light emitting structure piece 11b may be an organic light emitting material layer (OLED). The first electrode 11a may be an anode, and may be a light-transmitting anode, for example, a material such as Indium Tin Oxide (ITO); the anode may be a reflective anode, such as a stacked structure of ITO, metallic silver, and ITO. The second electrode 11c may be a cathode having a function of partially transmitting light and partially reflecting light, and the material is, for example, one or a mixture of metal magnesium and metal silver. The second electrode 11c of each first subpixel 11 may be connected as one surface electrode.
In fig. 2, a first pixel driving circuit is disposed below each first sub-pixel 11. The first pixel driving circuit may be the 2T1C circuit shown in fig. 3.
Referring to fig. 3, the first pixel driving circuit includes a first switching transistor X1, a first driving transistor X2, and a first storage capacitor C.
The gate of the first switching transistor X1 is electrically connected to a row scanning signal line Sn, and when the row scanning signal is a turn-on voltage, the first switching transistor X1 holds a data signal on a column data signal line VData at one plate of the first storage capacitor C; when the scan signal is the off voltage, the data signal retained on the first storage capacitor C keeps the first driving transistor X2 turned on, so that the power signal on the column of the power signal line VDD continuously supplies power to the first electrode 11a of the first sub-pixel 11.
Referring to fig. 2, the non-transparent display region 1b includes a plurality of second pixel units, and each second pixel unit includes a plurality of second sub-pixels 21. The second sub-pixel 21 includes a third electrode 21a, a second light emitting structure block 21b on the third electrode 21a, and a fourth electrode 21c on the second light emitting structure block 21 b. The second light emitting structure piece 21b may be red, green or blue, and may also be red, green, blue or yellow. The second sub-pixel 21 of the three primary colors of red, green and blue or the four primary colors of red, green, blue and yellow constitutes a second pixel unit. The second light emitting structure piece 21b may be an organic light emitting material layer (OLED). The third electrode 21a is a reflective anode, for example, a stacked structure of ITO, metallic silver, and ITO. The fourth electrode 21c may be a cathode, which has a function of partially transmitting light and partially reflecting light, but has a light transmittance smaller than that of the second electrode 11c, and is made of one or a mixture of metal magnesium and metal silver. The fourth electrode 21c of each second subpixel 21 may be connected as one surface electrode.
In fig. 2, a second pixel driving circuit is disposed below each second sub-pixel 21. The second pixel driving circuit may be the 7T1C circuit shown in fig. 4.
Referring to fig. 4, the second pixel driving circuit includes: a first sub transistor M1, a second sub transistor M2, a third sub transistor M3, a fourth sub transistor M4, a fifth sub transistor M5, a sixth sub transistor M6, a seventh sub transistor M7, and a second storage capacitor C';
wherein, the gate of the first sub-transistor M1 is connected to the scan signal line Sn of the pixel row where the second sub-pixel 21 is located and the gate of the second sub-transistor M2, the first pole of the first sub-transistor M1 is connected to the first pole of the sixth sub-transistor M6 and the second pole of the seventh sub-transistor M7, and the second pole of the first sub-transistor M1 is connected to the gate of the seventh sub-transistor M7 and the second pole of the second storage capacitor C';
a first pole of the second sub-transistor M2 is connected to the data signal line VData, and a second pole of the second sub-transistor M2 is connected to a first pole of the seventh sub-transistor M7 and a first pole of the third sub-transistor M3;
the gate of the third sub-transistor M3 is connected to the gate of the sixth sub-transistor M6, the first pole of the third sub-transistor M3 is connected to the first pole of the seventh sub-transistor M7, and the second pole of the third sub-transistor M3 is connected to the first pole plate of the second storage capacitor C';
the gate of the fourth sub-transistor M4 is connected to the scan signal line Sn-1 of the previous pixel row, the first pole of the fourth sub-transistor M4 is connected to the third electrode 21a of the second sub-pixel 21, and the second pole of the fourth sub-transistor M4 is connected to the initial voltage signal line Vinit and the second pole of the fifth sub-transistor M5;
the gate of the fifth sub-transistor M5 is connected to the scan signal line Sn-1 of the previous pixel row, the first pole of the fifth sub-transistor M5 is connected to the gate of the seventh sub-transistor M7 and the second pole of the second storage capacitor C', and the second pole of the fifth sub-transistor M5 is connected to the initial voltage signal line Vinit;
a gate of the sixth sub-transistor M6 is connected to the light emitting signal line EMn, a first pole of the sixth sub-transistor M6 is connected to the second pole of the seventh sub-transistor M7, and a second pole of the sixth sub-transistor M6 is connected to the first pole of the fourth sub-transistor M4;
the first plate of the second storage capacitor C' is connected to the power signal line VDD.
The first pole is one of a source and a drain, and the second pole is the other of the source and the drain. The first polar plate is one of the lower polar plate and the upper polar plate, and the second polar plate is the other one of the lower polar plate and the upper polar plate.
The first sub-transistor M1 is a second switch transistor, the sixth sub-transistor M6 is a second light emitting transistor, and the seventh sub-transistor M7 is a second driving transistor.
The pixel circuit of the 7T1C structure has a threshold voltage compensation process for the driving transistor during light emission, and thus can ensure uniformity of light emission of the second sub-pixel 21. In some embodiments, the second pixel driving circuit may also have a 6T1C structure, and the 6T1C structure is the same as the 7T1C structure, and the second light emitting transistor (the sixth sub-transistor M6) is omitted. In other embodiments, the second pixel driving circuit may have other structures, which is not limited in this embodiment.
In this embodiment, the second switching transistor M1 is a P-type transistor, i.e., it is conducted by hole carriers; the first switching transistor X1 is an N-type transistor, i.e., conducting with electron carriers. In other embodiments, the second switching transistor M1 may be an N-type transistor and the first switching transistor X1 may be a P-type transistor.
Referring to FIG. 1, a scan signal (e.g., S)1) A second switching transistor M1 connected to a second sub-pixel 21 in the same row (e.g., the first row) in the non-transparent display area 1 b; the scan signal (e.g., S) is obtained through the first inverter 311) The first switching transistor X1 of the first sub-pixel 11 in the same row (e.g., the first row) in the transparent display area 1 a; the synchronous driving of the transparent display area 1a and the non-transparent display area 1b can be realized, and the display effect of the display panel 1 used as a full screen is improved. In addition, each first sub-pixel 11 of the transparent display region 1a is non-transparentThe second sub-pixels 21 in the display area 1b can use the same GIP circuit, thereby avoiding the use of a complex structure and having low cost.
Fig. 5 is a circuit diagram of a first inverter. The first inverter 31 includes a first N-type transistor 311 and a first P-type transistor 312, wherein a gate of the first N-type transistor 311 is connected to a gate of the first P-type transistor 312 for inputting the scan signal SmWherein m is any row of the transparent display region 1 a; a first pole of the first N-type transistor 311 is connected to the low level VGL, and a second pole of the first P-type transistor 312 is connected to the high level VGH; the second pole of the first N-type transistor 311 is connected to the first pole of the first P-type transistor 312 for outputting the scan signal SmIs a reverse phase signal of
The first pole is one of a source and a drain, and the second pole is the other of the source and the drain.
Referring to fig. 1, the display panel 1 includes a frame region 1c, and the first inverter 31 is located in the frame region 1 c. In some embodiments, the first inverter 31 may also be located in the non-transparent display region 1 b. By disposing the first inverter 31 in the frame region 1c, it is able to avoid changing the layout of each second sub-pixel 21 in the non-transparent display region 1b and reducing the pixel density (PPI) of the second sub-pixels 21, compared to disposing the first inverter in the non-transparent display region 1 b. In other embodiments, the first inverter 31 may also be located in the transparent display area 1a, or in a transition display area (not shown) between the transparent display area 1a and the non-transparent display area 1 b. The first inverter 31 is disposed in the non-transparent display region 1b or the transition display region, so that the transmittance of the transparent display region 1a can be prevented from being reduced compared to the transparent display region 1 a.
Referring to fig. 2 and 3, it can be seen that the first switching transistor X1 is a low temperature polysilicon oxide transistor, and the second driving transistor X2 is a low temperature polysilicon transistor. Low Temperature polysilicon transistors (LTPS TFTs) are transistors based on Low Temperature polysilicon material as the semiconductor active layer. A Low Temperature Poly Silicon-Oxide TFT (LTPO TFT) is a transistor based on a Low Temperature Poly Oxide material as a semiconductor active layer. The low-temperature polycrystalline Oxide material may be at least one of IGZO (i.e., Indium Gallium Zinc Oxide), IGTO (i.e., Indium Gallium Tin Oxide), and IZTO (i.e., Indium Zinc Tin Oxide).
Referring to fig. 2, the low temperature polysilicon transistor includes, from bottom to top: a low temperature polysilicon semiconductor active layer 121 (a first source region, a first drain region, and a first channel region between the first source region and the first drain region), a first gate insulating layer 122, a first gate electrode 123, a first source electrode 124a connected to the first source region, and a first drain electrode 124b connected to the first drain region.
The first gate electrode 123 and the first gate insulating layer 122 not covering the first gate electrode 123 have an insulating layer 125 thereon. The insulating layer 125 may be an interlayer dielectric layer or a passivation layer.
The low-temperature polycrystalline oxide transistor comprises from bottom to top: a second source 134a connected to the second source region and a second drain 134b connected to the second drain region, an interlayer insulating layer 130, a low temperature poly oxide semiconductor active layer 131 (the second source region, the second drain region, and a second channel region between the second source region and the second drain region), a second gate insulating layer 132, and a second gate electrode 133.
The second gate electrode 133 and the second gate insulating layer 132 not covering the second gate electrode 133 have a planarization layer (PLN layer) thereon. The planarization layer (PLN layer) has an interlayer electrical connection structure connecting the first drain electrode 124b of the low temperature polysilicon transistor and the first electrode 11a (or the third electrode 21 a).
In the embodiment shown in fig. 2, the second drain electrode 134b of the low temperature poly-oxide transistor is electrically connected to the first source electrode 124a of the low temperature poly-silicon transistor through the low temperature poly-oxide semiconductor active layer 131 which is conductively processed. The conductive treatment may be by implantation of boron ions. In other embodiments, the second drain 134b of the low temperature poly-oxide transistor and the first source 124a of the low temperature poly-silicon transistor may be electrically connected through a material with good conductivity, such as a metal.
In the embodiment shown in fig. 2, the first gate electrode 123 of the low temperature polysilicon transistor is located above the low temperature polysilicon semiconductor active layer 121, and is a top gate structure. The second gate electrode 133 of the low temperature poly-oxide transistor is located above the low temperature poly-oxide semiconductor active layer 131, and is also in a top gate structure. In other embodiments, the first gate electrode 123 of the low temperature polysilicon transistor may also be located below the low temperature polysilicon semiconductor active layer 121 and is in a bottom gate structure, and/or the second gate electrode 133 of the low temperature polysilicon transistor may also be located below the low temperature polysilicon semiconductor active layer 131 and is in a bottom gate structure.
In other embodiments, the first switch transistor X1 and the first driving transistor X2 may be both low temperature polysilicon oxide transistors, or both low temperature polysilicon transistors, i.e., the first pixel driving circuit includes only low temperature polysilicon oxide transistors, or only low temperature polysilicon transistors. Compared to the latter embodiment, the low temperature poly-oxide transistor and the low temperature poly-silicon transistor in the embodiment of fig. 2 can be stacked on the upper layer and the lower layer without being limited by the minimum distance between the two low temperature poly-oxide transistors or the minimum distance between the two low temperature poly-silicon transistors, so that the area occupied by the low light transmittance region can be reduced, the light transmittance of the transparent display region 1a can be ensured, and the pixel density (PPI) of the first sub-pixel 11 can be increased.
When the first electrode 11a is a reflective electrode, the orthographic projection of the first switching transistor X1 and the first driving transistor X2 on the substrate 10 at least partially overlaps the orthographic projection of the first electrode 11a on the substrate 10, in other words, the first switching transistor X1 and the first driving transistor X2 are disposed right below the first electrode 11a, so as to further reduce the area occupied by the low light transmittance region and increase the area ratio of the high light transmittance region (e.g., the planarization layer PLN) to the low light transmittance region, thereby further ensuring the light transmittance of the transparent display region 1 a.
In some embodiments, when the camera collects an image through the transparent display area 1a, in order to reduce the diffraction problem of light passing through between the first sub-pixels 11, the orthographic projection of the first electrode 11a on the plane of the substrate 10 may be circular, elliptical, dumbbell-shaped or gourd-shaped. The various patterns described above solve the diffraction problem better than rectangular patterns.
The low-temperature polysilicon transistor in the first pixel driving circuit may be manufactured in synchronization with the low-temperature polysilicon transistor in the first inverter 31; and/or the low-temperature poly-oxide transistor in the first pixel driving circuit can be manufactured synchronously with the low-temperature poly-oxide transistor in the first inverter 31, so that the working procedure is saved, and the process is simplified.
In some embodiments, the first sub-pixels 11 and the second sub-pixels 21 may also be alternately distributed, or distributed regularly or irregularly, and the first pixel driving circuit (specifically, the first switching transistor X1) and the second pixel driving circuit (specifically, the second switching transistor M1) respectively corresponding to the first sub-pixels 11 and the second sub-pixels 21 in the same row share the same scanning signal through the first inverter 31, so that the synchronous driving of the first sub-pixels 11 and the second sub-pixels 21 can be realized.
In the embodiment shown in fig. 1, one side of the transparent display area 1a is adjacent to the frame area 1 c. In other embodiments, the transparent display region 1a may be disposed entirely within the non-transparent display region 1 b. In addition, in the embodiment shown in fig. 1, the transparent display area 1a is shaped like a drop, and in other embodiments, the transparent display area 1a may also be shaped like a rectangle, a circle, an ellipse, a bang, or the like.
Fig. 6 is a top view of a display panel according to a second embodiment of the present invention. Fig. 7 is a circuit diagram of a first pixel driving circuit of a 3T1C configuration. Referring to fig. 6 and 7, the display panel 2 of the present embodiment is substantially the same as the display panel 1 of fig. 1 to 5 except that: the first pixel driving circuit further includes: a first light emitting transistor X3, the first light emitting transistor X3 being located between the first driving transistor X2 and the first sub-pixel 11; the first light emitting transistor X3 has a conductivity type opposite to that of the second light emitting transistor M6; the first light emitting transistor X3 and the second light emitting transistor M6 respectively corresponding to the first sub-pixel 11 and the second sub-pixel 21 in the same row share the same light emitting signal through the second inverter 32.
In this embodiment, the second light emitting transistor M6 is a P-type transistor, and the first light emitting transistor X3 is an N-type transistor. The P-type transistor may be a low temperature polysilicon transistor and the N-type transistor may be a low temperature polysilicon oxide transistor. In other embodiments, the second light emitting transistor M6 may be an N-type transistor, and the first light emitting transistor X3 may be a P-type transistor.
Similar to the first inverter 31 in fig. 5, in an embodiment, the second inverter 32 includes a second N-type transistor and a second P-type transistor, and a gate of the second N-type transistor is connected to a gate of the second P-type transistor for inputting the light emitting signal; the first pole of the second N-type transistor is connected with the low level, and the second pole of the second P-type transistor is connected with the high level; the second pole of the second N-type transistor is connected with the first pole of the second P-type transistor and used for outputting an inverted signal of the light-emitting signal. The first pole is one of a source and a drain, and the second pole is the other of the source and the drain.
When the light-emitting signal is at a high level, the second N-type transistor is turned on, the second P-type transistor is turned off, the first pole and the second pole of the second N-type transistor are conducted, and a low level is output as an inverted signal of the light-emitting signal. When the light-emitting signal is at a low level, the second P-type transistor is turned on, the second N-type transistor is turned off, the first pole and the second pole of the second P-type transistor are conducted, and the high level is output as an inverted signal of the light-emitting signal. Compared with inverters with other structures, the inverter is simple in structure and reliable in performance.
The second P-type transistor may be a low temperature polysilicon transistor and the second N-type transistor may be a low temperature polysilicon oxide transistor.
Referring to fig. 6, the second inverter 32 is located in the frame region 1 c. In some embodiments, the second inverter 32 may also be located in the non-transparent display region 1 b. The second inverter 32 is disposed in the frame region 1c, so as to avoid changing the layout of each second sub-pixel 21 in the non-transparent display region 1b and reduce the pixel density (PPI) of the second sub-pixels 21, compared with the non-transparent display region 1 b. In other embodiments, the second inverter 32 may also be located in the transparent display area 1a, or in a transition display area (not shown) between the transparent display area 1a and the non-transparent display area 1 b. The second inverter 32 is disposed in the non-transparent display region 1b or the transition display region, so that the transmittance of the transparent display region 1a can be prevented from being reduced compared to the transparent display region 1 a.
In other embodiments, the conductivity types of the first light emitting transistor X3 and the second light emitting transistor M6 may be the same, and the first light emitting transistor X3 and the second light emitting transistor M6 respectively corresponding to the first sub-pixel 11 and the second sub-pixel 21 in the same row directly share the same light emitting signal. The first light emitting transistor X3 and the second light emitting transistor M6 may be both P-type transistors or both N-type transistors. The P-type transistor may be a low temperature polysilicon transistor and the N-type transistor may be a low temperature polysilicon oxide transistor.
Based on the display panels 1 and 2, an embodiment of the invention further provides a display device.
The display device can be a display device of a mobile phone, a tablet computer, a vehicle-mounted display screen and the like.
The display device includes:
an apparatus body having a device region;
and any one of the display panels 1 and 2, which is covered on the device body;
the device region is located below the transparent display region 1a of the display panel 1 or 2, and a photosensitive device which transmits or collects light through the transparent display region 1a is arranged in the device region.
The light sensing device may include: at least one of a camera, an infrared sensor, an infrared lens, a floodlight sensing element, an ambient light sensor and a dot matrix projector.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A display panel, comprising: a plurality of first sub-pixels and a first pixel driving circuit for driving each of the first sub-pixels, and a plurality of second sub-pixels and a second pixel driving circuit for driving each of the second sub-pixels; the first pixel driving circuit corresponding to the first sub-pixel and the second pixel driving circuit corresponding to the second sub-pixel in the same row share the same scanning signal through a first inverter.
2. The display panel according to claim 1, characterized in that the display panel comprises: a transparent display area and a non-transparent display area; the first sub-pixel and the first pixel driving circuit are positioned in the transparent display area; the second sub-pixel and the second pixel driving circuit are located in the non-transparent display area.
3. The display panel according to claim 2, wherein the first inverter is located in the non-transparent display region;
or the display panel further comprises a frame area, and the first inverter is positioned in the frame area;
preferably, the first inverter includes a first N-type transistor and a first P-type transistor, and a gate of the first N-type transistor is connected to a gate of the first P-type transistor for inputting the scan signal; a first pole of the first N-type transistor is connected with a low level, and a second pole of the first P-type transistor is connected with a high level; the second pole of the first N-type transistor is connected to the first pole of the first P-type transistor and used for outputting an inverted signal of the scanning signal;
preferably, the first P-type transistor is a low-temperature polysilicon transistor, and the first N-type transistor is a low-temperature polysilicon oxide transistor.
4. The display panel according to claim 1 or 2, wherein the first pixel driving circuit includes a first switching transistor, the second pixel driving circuit includes a second switching transistor, and the first switching transistor and the second switching transistor are opposite in conductivity type; the first pixel driving circuit and the second pixel driving circuit respectively corresponding to the first sub-pixel and the second sub-pixel which are positioned on the same row share the same scanning signal through a first inverter;
preferably, the second switch transistor is a third P-type transistor, and the first switch transistor is a third N-type transistor;
preferably, the third P-type transistor is a low temperature polysilicon transistor, and the third N-type transistor is a low temperature polysilicon oxide transistor.
5. The display panel according to claim 4, wherein the first pixel driving circuit further comprises a first light emitting transistor, wherein the second pixel driving circuit further comprises a second light emitting transistor, and wherein the first light emitting transistor and the second light emitting transistor have opposite conductivity types; the first light emitting transistor and the second light emitting transistor respectively corresponding to the first sub-pixel and the second sub-pixel in the same row share the same light emitting signal through the second inverter.
6. The display panel according to claim 5, wherein the second inverter is located in the non-transparent display region;
or the display panel further comprises a frame area, and the second inverter is positioned in the frame area;
preferably, the second inverter includes a second N-type transistor and a second P-type transistor, and a gate of the second N-type transistor is connected to a gate of the second P-type transistor for inputting the light emitting signal; the first pole of the second N-type transistor is connected with a low level, and the second pole of the second P-type transistor is connected with a high level; the second pole of the second N-type transistor is connected to the first pole of the second P-type transistor and used for outputting an inverted signal of the light-emitting signal;
preferably, the second P-type transistor is a low-temperature polysilicon transistor, and the second N-type transistor is a low-temperature polysilicon oxide transistor.
7. The display panel according to claim 4, wherein the first pixel driving circuit further comprises a first driving transistor, the first switching transistor is one of a low temperature polysilicon transistor and a low temperature polysilicon oxide transistor, and the first driving transistor is the other of the low temperature polysilicon transistor and the low temperature polysilicon oxide transistor.
8. The display panel according to claim 7, wherein the first pixel driving circuit further comprises a first light emitting transistor, and wherein the first light emitting transistor is a low temperature polysilicon transistor or a low temperature poly oxide transistor.
9. The display panel according to claim 7, wherein the first subpixel comprises: a first electrode, a first light emitting structure block positioned on the first electrode, and a second electrode positioned on the first light emitting structure block; the first electrode is a counter electrode; the orthographic projection of the low-temperature polycrystalline oxide transistor and the low-temperature polycrystalline silicon transistor on the display panel is at least partially overlapped with the orthographic projection of the first electrode on the display panel.
10. A display device, comprising:
an apparatus body having a device region;
and the display panel of any one of claims 1 to 9, overlaid on the device body; the device area is located below a transparent display area of the display panel, and a photosensitive device which penetrates through the transparent display area to emit or collect light is arranged in the device area.
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