CN110837490B - FPGA-based servo control method, system and medium - Google Patents

FPGA-based servo control method, system and medium Download PDF

Info

Publication number
CN110837490B
CN110837490B CN201911072138.1A CN201911072138A CN110837490B CN 110837490 B CN110837490 B CN 110837490B CN 201911072138 A CN201911072138 A CN 201911072138A CN 110837490 B CN110837490 B CN 110837490B
Authority
CN
China
Prior art keywords
multiplier
module
accumulation register
servo control
multiplicand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201911072138.1A
Other languages
Chinese (zh)
Other versions
CN110837490A (en
Inventor
张伟
马鹏
许虹梅
康岭
沈宗月
夏小东
朱波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 32 Research Institute
Original Assignee
CETC 32 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 32 Research Institute filed Critical CETC 32 Research Institute
Priority to CN201911072138.1A priority Critical patent/CN110837490B/en
Publication of CN110837490A publication Critical patent/CN110837490A/en
Application granted granted Critical
Publication of CN110837490B publication Critical patent/CN110837490B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0426—Programming the control sequence
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The application provides a servo control method, a servo control system and a servo control medium based on an FPGA, which are characterized by comprising the following steps: the arithmetic operation step: performing improved operation on a servo control formula; multiplier operation step: performing improved operation on the multiplier; the calculation flow operation steps are as follows: performing improved operation on the calculation flow; the result display step: and displaying the calculation result. The method greatly reduces the consumption of FPGA resources in the calculation process of the multiply-add type; the application is directly oriented to hardware programming without operating system software, has simple codes and is convenient for wide application; the application adopts a reasonable simplified formula, and the control precision requirement can be met by the simplified formula, so that the requirement is met, and the application has no too much allowance.

Description

FPGA-based servo control method, system and medium
Technical Field
The application relates to the field of servo control, in particular to a servo control method, a servo control system and a servo control medium based on an FPGA, and particularly relates to a servo control method based on a small-capacity FPGA.
Background
Currently, with the increasing demand for industrial intelligence, particularly in recent years, industrial robots are becoming increasingly popular, so that the demands for servo systems in the core of articulation are increasing. However, the traditional servo control is performed by combining a DSP or an embedded CPU with software, so that huge expenditure is brought to a processor unit, and the calculation instantaneity is influenced by the processor structure and cannot be strictly and accurately achieved.
FPGA (Field Programmable Gate Array) is a product of further development on the basis of programmable devices such as PAL, GAL, etc. The programmable device is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device.
The FPGA enables a plurality of functions to be realized by converting software into hardware, so that the pressure of a CPU can be effectively reduced, and the execution effect of the control function is improved. However, in some specific scenarios, such as a satellite upper stage platform, the available FPGA has limited capacity and limited reliability, and because the space navigation has particularly strict requirements on reliability, the FPGA needs to leave some margin to increase the reliability, and the servo control algorithm usually has a large number of data operations such as floating point multiplication, addition and the like, which extremely consumes FPGA logic resources and generates a relatively large conflict with the current situation and requirements.
How to realize complex algorithm design by using smaller logic and meeting the requirements of performance and reliability are the problems to be solved by the application.
Patent document (application number: CN 201610789235.2) discloses a general servo control arithmetic logic unit, which comprises a pre-adder, a pre-regulator B, a pre-regulator C, a multiplier, a limiter, a multiplexer X, a multiplexer Y, an accumulator and a shifter, wherein signal control ends of the pre-adder, the multiplexer X, the multiplexer Y, the limiter and the accumulator are connected with corresponding output ends of a mode signal regulator for performing delay adjustment on a mode control signal, and configuration relations between an output signal and an input signal are multiple by controlling the control signal output by the mode signal regulator. The application can realize more servo control algorithms on the basis of no need of secondary development, and shortens the development period of FPGA realization. The patent has complex calculation structure, the multiplication execution unit is not optimized, a large amount of FPGA resources are consumed, and the method can not be applied to the scene of a small-capacity FPGA.
The literature "research of dual mode servo control algorithm based on FPGA" (Song Jun, yan Dong, etc., fire and command control, 2015, 1 month, 40 volume, 1 st phase) discloses: the servo system of the gun mainly completes the rotation of the gun turret and the tracking of the target according to the target parameters given by the fire control system. The response performance of the servo system is directly related to the performance and reliability of the combat system, and the control algorithm is one of the cores of the servo control. The servo system based on the dual-mode fusion warships mainly completes rotation of the gun turret and tracking of targets according to target parameters given by a fire control system. The response performance of the servo system is directly related to the performance and reliability of the combat system, and the control algorithm is one of the cores of the servo control. The algorithm design still cannot be applied to the scenes of small-capacity FPGA in the satellite upper-level system, and the application can achieve the aim.
Patent document CN109560745a (application number: 201811638734.7) discloses a servo controller including an ARM processor, an FPGA circuit, a data conversion module, a network communication module, a serial communication module, an encoder interface module, a CAN communication module, an input-output interface module, and a power supply module; the power module is respectively connected with the ARM processor, the FPGA circuit and each module and is used for providing power; the data conversion module, the network communication module, the CAN communication module and the input/output interface module are respectively connected with the ARM processor; the encoder interface module is connected with the FPGA circuit, and the serial communication module is respectively connected with the ARM processor and the FPGA circuit.
Disclosure of Invention
Aiming at the defects in the prior art, the application aims to provide a servo control method, a servo control system and a servo control medium based on an FPGA.
The servo control method based on the FPGA provided by the application comprises the following steps:
a data acquisition step: obtaining servo control data from a central processing unit;
the arithmetic operation step: performing improved operation on a servo control formula;
multiplier operation step: performing improved operation on the multiplier;
the calculation flow operation steps are as follows: performing improved operation on the calculation flow;
the result display step: and displaying the calculation result and feeding back to the servo controller.
Preferably, the servo control formula is:
Up(k)＝Kp·e(k)；
Ux(k)＝K1·Up(k)+K2·Up(k-1)+K3·Up(k-2)+K4·Ux(k-1)+K5·Ux(k-2)；
wherein Up (k) represents an intermediate value at the current time;
e (k) represents an error value at the current time;
ux (k) represents a position loop control output value at the current time;
k-1 represents the previous time;
k-2 represents the first two moments;
kp is an integer coefficient, and K1, K2, K3, K4 and K5 are floating point coefficients;
the formula operation step comprises the following steps:
an operation integer step, comprising:
step 1: multiplying floating point coefficients by 2 n Multiplying the error value by 2 m ；
Step 2: after calculating the intermediate value, the intermediate value is divided by 2 m ；
Step 3: when the proportion is selected, the denominator is amplified to the original 2 n Doubling;
a coefficient normalization step, comprising:
the sum of the floating point coefficients is 1.0, and when the floating point coefficients are amplified, the sum of the floating point coefficients is the amplified coefficient.
Preferably, the multiplier operation step includes:
step 1: when calculation starts, initializing an accumulation register to 0, storing a multiplier and a multiplicand into a multiplier shifter and a multiplicand shifter respectively, and setting the bit width of the accumulation register to be 2 times of the bit width of the multiplier;
setting the bit width of the multiplicand shifter to be 2 times of the multiplicand bit width;
the multiplier is consistent with the multiplicand bit width;
step 2: updating the value of the accumulation register according to the value of the lowest bit of the multiplier;
if the lowest bit of the multiplier is 0, the accumulation register is added with 0 and then stored back into the accumulation register;
if the lowest bit of the multiplier is 1, the accumulation register and the multiplicand are added and stored back into the accumulation register;
after the addition is finished, the multiplier is moved one bit to the right, and the multiplicand is moved one bit to the left;
step 3: taking and storing the high-order numerical value of the accumulation register after all the bits of the multiplier are calculated;
the bit width of the high-order numerical value of the accumulation register is the same as the bit width of the input multiplier.
Preferably, the calculating step includes:
step 1: resetting the accumulator before calculation begins;
step 2: calculating Up (k);
step 3: calculating K1.Up (K), adding the result with an accumulation register, and storing the result into the accumulation register;
step 4: and returning to the step 3, sequentially calculating K2, K3, K4 and K5, and after the calculation and addition of the K5 are finished, finishing the operation to obtain an operation result.
Preferably, the displaying step includes: and outputting the operation result to a display end for editing and extracting, and inputting the operation result to a servo controller for controlling the servo equipment.
According to the present application, there is provided an FPGA-based servo control system comprising:
and a data acquisition module: obtaining servo control data from a central processing unit;
the arithmetic operation module: performing improved operation on a servo control formula;
the multiplier operation module: performing improved operation on the multiplier;
the calculation flow operation module: performing improved operation on the calculation flow;
the result display module: and outputting the operation result to a display end for editing and extracting, and inputting the operation result to a servo controller for controlling the servo equipment.
Preferably, the servo control formula is:
Up(k)＝Kp·e(k)；
Ux(k)＝K1·Up(k)+K2·Up(k-1)+K3·Up(k-2)+K4·Ux(k-1)+K5·Ux(k-2)；
wherein Up (k) represents an intermediate value at the current time;
e (k) represents an error value at the current time;
ux (k) represents a position loop control output value at the current time;
k-1 represents the previous time;
k-2 represents the first two moments;
kp is an integer coefficient, and K1, K2, K3, K4 and K5 are floating point coefficients;
the arithmetic operation module comprises an operation integer module and a coefficient normalization module;
the operation integer module comprises:
module M1: multiplying floating point coefficients by 2 n Multiplying the error value by 2 m ；
Module M2: after calculating the intermediate value, the intermediate value is divided by 2 m ；
Module M3: when the proportion is selected, the denominator is amplified to the original 2 n Doubling;
the coefficient normalization module comprises:
the sum of the floating point coefficients is 1.0, and when the floating point coefficients are amplified, the sum of the floating point coefficients is the amplified coefficient.
Preferably, the multiplier operation module includes:
module N1: when calculation starts, initializing an accumulation register to 0, and storing a multiplier and a multiplicand into a multiplier shifter and a multiplicand shifter respectively, wherein the bit width of the accumulation register is 2 times of the bit width of the multiplier;
the bit width of the multiplicand shifter is 2 times of the multiplicand bit width;
the multiplier is consistent with the multiplicand bit width;
module N2: updating the value of the accumulation register according to the value of the lowest bit of the multiplier;
if the lowest bit of the multiplier is 0, the accumulation register is added with 0 and then stored back into the accumulation register;
if the lowest bit of the multiplier is 1, the accumulation register and the multiplicand are added and stored back into the accumulation register;
after the addition is finished, the multiplier is moved one bit to the right, and the multiplicand is moved one bit to the left;
module N3: taking and storing the high-order numerical value of the accumulation register after all the bits of the multiplier are calculated;
the bit width of the high-order numerical value of the accumulation register is the same as the bit width of the input multiplier.
Preferably, the calculation flow operation module includes:
module P1: resetting the accumulator before calculation begins;
module P2: calculating Up (k);
module P3: calculating K1.Up (K), adding the result with an accumulation register, and storing the result into the accumulation register;
module P4: and calling a module P3, sequentially calculating K2, K3, K4 and K5, and obtaining an operation result after the calculation and addition of the K5 are finished.
Compared with the prior art, the application has the following beneficial effects:
1. the method greatly reduces the consumption of FPGA resources in the calculation process of the multiply-add type;
2. the application is not only applicable to FPGA, but also to ASIC design;
3. the application is directly oriented to hardware programming without operating system software, has simple codes and is convenient for wide application;
4. the application adopts a reasonable simplified formula, and the control precision requirement can be met by the simplified formula without too much allowance;
5. the application can be conveniently realized by using the FPGA of Xilinx, altera, actel, can also be realized by developing a special ASIC chip, and can develop a special servo control system based on the FPGA or the ASIC chip by using the formula.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a diagram of the overall architecture of a servo control algorithm module;
fig. 2 is a schematic diagram of a multiplier.
Detailed Description
The present application will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.
The technical scheme of the application comprises three parts, namely a servo control arithmetic transformation scheme, a multiplier transformation scheme and calculation flow optimization.
The servo control formula is as follows:
equation one: up (k) =Kp.e (k)
Formula II: ux (K) =K1.Up (K) +K2.Up (K-1) +K3.Up (K-2) +K4.Ux (K-1) +K5.Ux (K-2)
Wherein, up (k), up (k-1) and Up (k-2) are respectively the intermediate values of the current time, the previous time and the previous two times; e (k), e (k-1) and e (k-2) are error values (V) at the current time, the previous time and the previous two times respectively; ux (k), ux (k-1), and Ux (k-2) are position loop control output values at the current time, the previous time, and the previous two times, respectively. Kp is an integer coefficient, and K1, K2, K3, K4 and K5 are floating point coefficients.
1. The servo control formula is improved:
the servo control formula transformation scheme adopts two methods of operation integer transformation and coefficient normalization to realize integer transformation of a calculation formula and ensure stability of a calculation result.
Compared with floating point operation, the integer operation can greatly reduce the resource cost of the FPGA, and the specific method comprises the following steps:
(1) Multiplying floating point coefficients K1-K5 by 2 n Multiplying the error value e (k) by 2 m 。
(2) After calculating Up (k), dividing Up (k) by 2 m Ensure that the intermediate quantity calculated by the formula II is only amplified to 2 n Multiple times.
(3) Final calculation2 controlled to actual value n When the subsequent proportion selection is required, the denominator is also amplified to the original 2 n 。
The multiplication and division in the steps 1 and 2 can be realized by operating data bits by utilizing the characteristics of hardware language in actual design without consuming a great deal of logic resources. For example, realizing a [31:0 ]]Divided by 2 16 Only a [31:16 ] needs to be taken]As a result.
Coefficient normalization:
the sum of the coefficients of equation two of the required equation in the PID equation is 1.0, referred to herein as normalization, otherwise the calculation results will be in a divergent state, and jitter will occur when the calculation results control the servo mechanism.
After the coefficient is calculated in an integer manner, the sum of the coefficients must also meet the normalization requirement after the coefficient adjustment, i.e. if the value of the coefficient in an integer manner is 2 n The sum of K1, K2, K3, K4, K5 must be 2 n 。
2. The multiplier transformation scheme comprises the following steps:
the multiplier only provides integer multiplication, the multiplication calculation process is realized in an accumulation mode to save logic resources so as to calculate time-shift logic space, and the structure is shown in figure 2.
The specific implementation mode of the multiplier is as follows:
(1) Initializing an accumulation register to 0 when calculation starts, and storing a multiplier and a multiplicand into a multiplier shifter and a multiplicand shifter respectively, wherein the bit width of the accumulation register is 2 times of the bit width of the data;
(2) Each calculated beat:
updating the value of the accumulation register based on the value of the least significant bit of the multiplier: if the lowest bit of the multiplier is 0, the accumulation register is added with 0 and then stored back into the accumulator; if the lowest order bit of the multiplier is 1, the accumulation register and the multiplicand are added and stored back into the accumulator.
The multiplier is shifted one bit to the right and the multiplicand is shifted one bit to the left.
(3) And after all the bits of the multiplier are calculated, taking the high bits (the bit number is the same as the bit width of the input value) of the accumulation register and outputting the high bits to a calculation result interface.
3. And (3) optimizing a calculation flow:
as shown in the first and second formulas, each calculation needs to perform 6 multiplications, and if a simultaneous calculation mode is adopted, the multiplier resource will be 6 times of that of a single multiplier, and a large amount of FPGA logic resource will be consumed.
The optimization mode of the calculation flow is to calculate each multiplication item successively, call the same multiplier each time, store the result of each multiplication into the accumulator, and the result of the accumulator is the final result after the calculation is finished, see fig. 1. The specific flow is as follows:
(1) Resetting the accumulator after calculation begins;
(2) Calculating Up (k);
(3) Calculating K1.Up (K), adding the result with the accumulator, and storing the result into the accumulator;
(4) Repeating the step 3 to sequentially calculate K2, K3, K4 and K5;
(5) The accumulator result is sent to the output port.
Those skilled in the art will appreciate that the systems, apparatus, and their respective modules provided herein may be implemented entirely by logic programming of method steps such that the systems, apparatus, and their respective modules are implemented as logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc., in addition to the systems, apparatus, and their respective modules being implemented as pure computer readable program code. Therefore, the system, the apparatus, and the respective modules thereof provided by the present application may be regarded as one hardware component, and the modules included therein for implementing various programs may also be regarded as structures within the hardware component; modules for implementing various functions may also be regarded as being either software programs for implementing the methods or structures within hardware components.
The foregoing describes specific embodiments of the present application. It is to be understood that the application is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the application. The embodiments of the application and the features of the embodiments may be combined with each other arbitrarily without conflict.

Claims (6)

1. A servo control method based on an FPGA, comprising:
a data acquisition step: obtaining servo control data from a central processing unit;
the arithmetic operation step: performing improved operation on a servo control formula;
multiplier operation step: performing improved operation on the multiplier;
the calculation flow operation steps are as follows: performing improved operation on the calculation flow;
the result display step: displaying the calculation result and feeding back to the servo controller;
the calculation steps of the calculation flow comprise:
step 1: resetting the accumulator before calculation begins;
step 2: calculating Up (k);
step 3: calculating K1.Up (K), adding the result with an accumulation register, and storing the result into the accumulation register;
step 4: returning to the step 3, sequentially calculating K2, K3, K4 and K5, and finishing the operation after the calculation and addition of the K5 to obtain an operation result;
the servo control formula is:
Up(k)＝Kp·e(k)；
Ux(k)＝K1·Up(k)+K2·Up(k-1)+K3·Up(k-2)+K4·Ux(k-1)+K5·Ux(k-2)；
wherein Up (k) represents an intermediate value at the current time;
e (k) represents an error value at the current time;
ux (k) represents a position loop control output value at the current time;
k-1 represents the previous time;
k-2 represents the first two moments;
kp is an integer coefficient, and K1, K2, K3, K4 and K5 are floating point coefficients;
the formula operation step comprises the following steps:
an operation integer step, comprising:
step 1: multiplying floating point coefficients by 2 n Will be errorValue multiplied by 2 m ；
Step 2: after calculating the intermediate value, the intermediate value is divided by 2 m ；
Step 3: when the proportion is selected, the denominator is amplified to the original 2 n Doubling;
a coefficient normalization step, comprising:
the sum of the floating point coefficients is 1.0, and when the floating point coefficients are amplified, the sum of the floating point coefficients is the amplified coefficient.
2. The FPGA-based servo control method according to claim 1, wherein the multiplier operation step includes:
step 1: when calculation starts, initializing an accumulation register to 0, storing a multiplier and a multiplicand into a multiplier shifter and a multiplicand shifter respectively, and setting the bit width of the accumulation register to be 2 times of the bit width of the multiplier;
setting the bit width of the multiplicand shifter to be 2 times of the multiplicand bit width;
the multiplier is consistent with the multiplicand bit width;
step 2: updating the value of the accumulation register according to the value of the lowest bit of the multiplier;
if the lowest bit of the multiplier is 0, the accumulation register is added with 0 and then stored back into the accumulation register;
if the lowest bit of the multiplier is 1, the accumulation register and the multiplicand are added and stored back into the accumulation register;
after the addition is finished, the multiplier is moved one bit to the right, and the multiplicand is moved one bit to the left;
step 3: taking and storing the high-order numerical value of the accumulation register after all the bits of the multiplier are calculated;
the bit width of the high-order numerical value of the accumulation register is the same as the bit width of the input multiplier.
3. The FPGA-based servo control method of claim 1, wherein the displaying step includes: and outputting the operation result to a display end for editing and extracting, and inputting the operation result to a servo controller for controlling the servo equipment.
4. An FPGA-based servo control system, comprising:
and a data acquisition module: obtaining servo control data from a central processing unit;
the arithmetic operation module: performing improved operation on a servo control formula;
the multiplier operation module: performing improved operation on the multiplier;
the calculation flow operation module: performing improved operation on the calculation flow;
the result display module: outputting the operation result to a display end for editing and extracting, inputting the operation result to a servo controller, and controlling servo equipment;
the calculation flow operation module comprises:
module P1: resetting the accumulator before calculation begins;
module P2: calculating Up (k);
module P3: calculating K1.Up (K), adding the result with an accumulation register, and storing the result into the accumulation register;
module P4: calling a module P3, sequentially calculating K2, K3, K4 and K5, and finishing operation after the calculation and addition of the K5 are finished to obtain an operation result;
the servo control formula is:
Up(k)＝Kp·e(k)；
Ux(k)＝K1·Up(k)+K2·Up(k-1)+K3·Up(k-2)+K4·Ux(k-1)+K5·Ux(k-2)；
wherein Up (k) represents an intermediate value at the current time;
e (k) represents an error value at the current time;
ux (k) represents a position loop control output value at the current time;
k-1 represents the previous time;
k-2 represents the first two moments;
kp is an integer coefficient, and K1, K2, K3, K4 and K5 are floating point coefficients;
the arithmetic operation module comprises an operation integer module and a coefficient normalization module;
the operation integer module comprises:
module M1: multiplying floating point coefficients by 2 n Multiplying the error value by 2 m ；
Module M2: after calculating the intermediate value, the intermediate value is divided by 2 m ；
Module M3: when the proportion is selected, the denominator is amplified to the original 2 n Doubling;
the coefficient normalization module comprises:
the sum of the floating point coefficients is 1.0, and when the floating point coefficients are amplified, the sum of the floating point coefficients is the amplified coefficient.
5. The FPGA-based servo control system of claim 4, wherein the multiplier operation module comprises:
module N1: when calculation starts, initializing an accumulation register to 0, and storing a multiplier and a multiplicand into a multiplier shifter and a multiplicand shifter respectively, wherein the bit width of the accumulation register is 2 times of the bit width of the multiplier;
the bit width of the multiplicand shifter is 2 times of the multiplicand bit width;
the multiplier is consistent with the multiplicand bit width;
module N2: updating the value of the accumulation register according to the value of the lowest bit of the multiplier;
if the lowest bit of the multiplier is 0, the accumulation register is added with 0 and then stored back into the accumulation register;
if the lowest bit of the multiplier is 1, the accumulation register and the multiplicand are added and stored back into the accumulation register;
after the addition is finished, the multiplier is moved one bit to the right, and the multiplicand is moved one bit to the left;
module N3: taking and storing the high-order numerical value of the accumulation register after all the bits of the multiplier are calculated;
the bit width of the high-order numerical value of the accumulation register is the same as the bit width of the input multiplier.
6. A computer-readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the steps of the method of any one of claims 1 to 3.
CN201911072138.1A 2019-11-05 2019-11-05 FPGA-based servo control method, system and medium Active CN110837490B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911072138.1A CN110837490B (en) 2019-11-05 2019-11-05 FPGA-based servo control method, system and medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911072138.1A CN110837490B (en) 2019-11-05 2019-11-05 FPGA-based servo control method, system and medium

Publications (2)

Publication Number Publication Date
CN110837490A CN110837490A (en) 2020-02-25
CN110837490B true CN110837490B (en) 2023-08-11

Family

ID=69576338

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911072138.1A Active CN110837490B (en) 2019-11-05 2019-11-05 FPGA-based servo control method, system and medium

Country Status (1)

Country Link
CN (1) CN110837490B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2867353Y (en) * 2005-04-11 2007-02-07 北京航空航天大学 Receiver of satellite navigation general digital signal processing platform
CN102122964A (en) * 2011-03-31 2011-07-13 西安电子科技大学 Implementation method of high-speed reed-solomon (RS) codec based on field programmable gate array (FPGA)
CN103529833A (en) * 2013-09-24 2014-01-22 苏州工业园区职业技术学院 Dual-core four-wheeled top-speed microcomputer mouse-based diagonal sprint system
CN109960188A (en) * 2017-12-26 2019-07-02 宁波菲仕运动控制技术有限公司 A kind of general-purpose servo control processor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2867353Y (en) * 2005-04-11 2007-02-07 北京航空航天大学 Receiver of satellite navigation general digital signal processing platform
CN102122964A (en) * 2011-03-31 2011-07-13 西安电子科技大学 Implementation method of high-speed reed-solomon (RS) codec based on field programmable gate array (FPGA)
CN103529833A (en) * 2013-09-24 2014-01-22 苏州工业园区职业技术学院 Dual-core four-wheeled top-speed microcomputer mouse-based diagonal sprint system
CN109960188A (en) * 2017-12-26 2019-07-02 宁波菲仕运动控制技术有限公司 A kind of general-purpose servo control processor

Also Published As

Publication number Publication date
CN110837490A (en) 2020-02-25

Similar Documents

Publication Publication Date Title
KR102316670B1 (en) computational accelerator
US20130073599A1 (en) Hardware for performing arithmetic operations
JP2003296096A (en) Serial arithmetic pipeline, arithmetic unit, arithmetic logic circuit, and arithmetic method by serial arithmetic pipeline
US10877733B2 (en) Segment divider, segment division operation method, and electronic device
US8438521B1 (en) Methods and apparatus for implementing application specific processors
CN103984560A (en) Embedded reconfigurable system based on large-scale coarseness and processing method thereof
CN111325332A (en) Convolutional neural network processing method and device
EP4318275A1 (en) Matrix multiplier and method for controlling matrix multiplier
CN110837490B (en) FPGA-based servo control method, system and medium
Huang et al. A high performance multi-bit-width booth vector systolic accelerator for NAS optimized deep learning neural networks
CN102591200B (en) Field programmable gate array (FPGA) control system development platform
TWI537819B (en) Algorithm module, device and system
CN115167815A (en) Multiplier-adder circuit, chip and electronic equipment
US20200311330A1 (en) Method for simulating a dynamic system
CN110750752B (en) Interpolation method and device for analog data
US9836221B1 (en) Configurable high speed FPGA scan mechanism controller
CN113867799A (en) Computing device, integrated circuit chip, board card, electronic equipment and computing method
Milik et al. Hardware mapping strategies of PLC programs in FPGAs
CN114579083B (en) Data processing device and method based on vector processor
WO2022001496A1 (en) Computing apparatus, integrated circuit chip, board card, electronic device, and computing method
CN113033799B (en) Data processor, method, device and chip
CN113031909B (en) Data processor, method, device and chip
WO2023284130A1 (en) Chip and control method for convolution calculation, and electronic device
TWI485558B (en) Fault-tolerant system and fault-tolerant operating method
CN110378478B (en) Multiplier, data processing method, chip and electronic equipment

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant