CN110830113B

CN110830113B - Standard CMOS fully-differential photoelectric integrated receiver for visible light communication

Info

Publication number: CN110830113B
Application number: CN201911061519.XA
Authority: CN
Inventors: 毛陆虹; 丛佳; 谢生; 李佳琦
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2019-11-01
Filing date: 2019-11-01
Publication date: 2022-03-01
Anticipated expiration: 2039-11-01
Also published as: CN110830113A

Abstract

A standard CMOS fully differential optoelectronic integrated receiver for visible light communication comprises the following components connected in sequence: the differential-to-single-ended output buffer stage is used for converting the differential voltage signals output by the fully differential transimpedance preamplifier into a pair of differential voltage signals, the fully differential limiting amplifier is used for amplifying the voltage signals output by the fully differential transimpedance preamplifier into the voltage level required by the digital processing unit, the fully differential equalizer is used for compensating the frequency response characteristic of the signals output by the fully differential limiting amplifier, the differential voltage signals which reach the digital voltage level and are output by the fully differential equalizer are converted into single-ended output voltage signals, the driving capability is provided, the difference is converted into the single end, and the input end of the fully differential transimpedance preamplifier is connected with a pair of fully differential photodetectors which are used for converting the visible light signals transmitted from the outside into the pair of fully differential current signals. The invention realizes the integration of the visible light communication receiver and improves the sensitivity of the receiver.

Description

Standard CMOS fully-differential photoelectric integrated receiver for visible light communication

Technical Field

The invention relates to a receiver for visible light communication. And more particularly to a standard CMOS fully differential optoelectronic integrated receiver for visible light communications.

Background

White-light LEDs (light-emitting diodes) are now widely used in signal-emitting, display-lighting and other fields. Compared with the traditional illumination light source, the white light LED is an outstanding green illumination light source, has high brightness, small size, low power consumption, easy driving, long service life, green and environmental protection, particularly has very high response sensitivity, has good modulation characteristic and can be used for data communication. For the above reasons, Visible Light Communication (VLC) is emerging as an emerging technology in the field of wireless Communication. The indoor visible light communication technology can meet the indoor network requirement and daily indoor lighting. Compared with the traditional communication technology, the method has higher privacy and safety, can utilize a wider frequency band, and can avoid electromagnetic interference; the wireless communication access can be realized, the network coverage is expanded, and the spatial reusability is very good; the LED lamp can emit visible light signals to transmit and exchange information outdoors and among automobiles, so that traffic accidents and the like are avoided.

At the beginning of the development of visible light communication, VLC systems were assembled from discrete optical and electrical components via printed circuit boards. However, the system is huge in volume and expensive in manufacturing cost, so that visible light communication can only be stopped in a laboratory and a high-end application occasion, and cannot be widely popularized. With the continuous progress of the visible light communication technology, the single-chip integrated visible light communication special chip shows great advantages. The monolithic VLC system has the advantages of high speed, high reliability, small volume, light weight and low cost, represents the development direction of the mainstream of photoelectric integration, and can push forward the development of visible light communication technology.

In visible light systems, however, the amount of light reaching the receiver surface is greatly reduced by the diffuse light generated by the LEDs over a distance. Thus, enhancing the sensitivity and signal-to-noise ratio (SNR) of the receiving device is critical to ensuring error-free data communication. The monolithic integration of the optical receiver means that the chip collects less optical power, the detector area must be larger to improve the sensitivity of the receiver, and the large detector area means large junction capacitance and long transit time, which affect the overall bandwidth of the receiver. In addition, there are two problems in applying an integrated visible light receiver, which has been conventionally prepared for a plastic optical fiber, to a visible light communication system using an LED as a light source. First, the responsivity of the Si Photodetector (PD) to infrared light in these optical receivers is generally high. The main communication band of the white light LED which is widely applied at present is in the blue light area. Secondly, most of the integrated visible light receivers prepared by plastic optical fibers are of single-end input type or pseudo-differential type. The single-ended input receiver has a disadvantage of poor high-frequency stability and is liable to self-excitation. The two input ends of the pseudo-differential optical receiver, namely the differential circuit, are connected with the same detector, and the surface of one detector is covered by metal. Although the problem of high-frequency stability of the circuit can be overcome, as described above, the area of the detector for visible light communication is relatively large, and completely covering one of the detectors is a great waste of chip area, which affects the sensitivity of the optical receiver.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a standard CMOS fully differential photoelectric integrated receiver for visible light communication, which can effectively improve the sensitivity of the receiver.

The technical scheme adopted by the invention is as follows: a standard CMOS fully differential optoelectronic integrated receiver for visible light communication comprises the following components connected in sequence: the differential-to-single-ended output buffer stage is used for converting the differential voltage signals output by the fully differential transimpedance preamplifier into a pair of differential voltage signals, the fully differential limiting amplifier is used for amplifying the voltage signals output by the fully differential transimpedance preamplifier to a voltage level required by the digital processing unit, the fully differential equalizer is used for compensating the frequency response characteristic of the signals output by the fully differential limiting amplifier, the differential voltage signals which reach the digital voltage level and are output by the fully differential equalizer are converted into voltage signals output by a single end, and the differential-to-single-ended output buffer stage provides driving capability, and the input end of the fully differential transimpedance preamplifier is connected with a pair of fully differential photodetectors which are used for converting visible light signals transmitted from the outside into a pair of fully differential current signals.

The pair of fully differential photoelectric detectors comprises a first detector and a second detector, the first detector is composed of a P +/N well/P substrate, the anode is connected with one input end of the fully differential transimpedance preamplifier, and the cathode is connected with a power supply VDD; the second detector is composed of an N +/P well/a deep N well/a P substrate, the cathode is grounded, the anode is connected with the other input end of the fully differential trans-impedance preamplifier, the directions of photocurrents generated by the first detector and the second detector are opposite, the first detector and the second detector have the same capacitance and are mutually abutted, and no shading layer is arranged above the first detector and the second detector.

The standard CMOS fully-differential photoelectric integrated receiver for visible light communication realizes integration of the visible light communication receiver on the basis of not increasing the manufacturing cost of an integrated circuit, and improves weak response of the optical receiver due to weak visible light intensity received by the receiver; the problem of chip area waste caused by shielding detectors in the detector response peak non-blue light and pseudo-differential receivers is solved, and the sensitivity of the receivers is effectively improved. The invention has the technical characteristics that:

1. the standard CMOS fully-differential photoelectric integrated receiver for visible light communication provided by the invention is completely compatible with a standard CMOS process, does not generate any other cost increase, is an effective way for realizing the chip formation of the visible light receiver, and can be applied to an indoor visible light communication system.

2. The photoelectric integrated receiver provided by the invention has a fully differential characteristic, namely, two detectors without metal shielding are connected to two ends of a transimpedance preamplifier in a fully differential mode. Therefore, the stability of the optical receiver is improved, the two detectors receive optical signals simultaneously, the sensitivity and the bandwidth can reach twice of those of the existing single photoelectric detector differential receiver, the waste of chip area can be reduced compared with a pseudo-differential optical receiver, and the sensitivity of the receiver is improved.

3. The invention uses the PN junction formed by the P +/N trap of the first detector and the N +/P trap of the second detector as the effective photocurrent generating junction at the two ends of the fully differential circuit. The two junctions are shallow junctions in CMOS technology, and their absorption peak of light is near blue light, which is advantageous for detectors of visible light signals with blue light as the communication wavelength.

4. The first and second detectors proposed by the invention are all large-area detectors composed of a plurality of smaller subunits. The large-area detector is arranged for adapting to weak communication light intensity in a visible light communication system, a large communication area inevitably causes large junction capacitance and large carrier transit time, and the intrinsic bandwidth of the detector is mainly influenced by the carrier transit time. Therefore, the fully differential detector provided by the invention is composed of a plurality of small units, so that the carrier transit time of the detector can be effectively reduced, and the intrinsic bandwidth of the detector can be effectively increased. In addition, the size of the minimum unit of the two detectors is effectively adjusted, so that the intrinsic bandwidths of the two detectors for blue light are the same as much as possible and are higher, and the performance of the fully differential receiver is improved.

Drawings

FIG. 1 is a schematic diagram of a circuit structure of a standard CMOS fully differential optoelectronic integrated receiver for visible light communication according to the present invention;

FIG. 2 is a top view of the structure of the fully differential detector of the present invention;

FIG. 3 is a schematic cross-sectional view A-A of FIG. 2;

FIG. 4a is an equivalent circuit model of the first detector in the normal operation of the fully differential detector of the present invention;

fig. 4b is an equivalent circuit model of the second detector in the normal operation of the fully differential detector of the present invention.

In the drawings

1: p-type substrate 2: n well region

3: deep N-well region 4: p well region

5: first detector cathode 6: second detector cathode

7: the deep N well region is externally connected with an active region 8: first detector anode

9: second detector anode 10: the P-type substrate is externally connected with an active region

12: first detector cathode electrode 13: first detector anode electrode

14: second detector anode electrode 15: second detector cathode electrode

16: deep N-well external electrode 17: external grounding electrode of P-type substrate

Detailed Description

The invention provides a standard CMOS fully differential optoelectronic integrated receiver for visible light communication, which is described in detail below with reference to the embodiments and the accompanying drawings.

As shown in fig. 1, a standard CMOS fully differential optoelectronic integrated receiver for visible light communication according to the present invention includes: a fully differential transimpedance preamplifier DTIA for converting a pair of differential current signals into a pair of differential voltage signals, a fully differential limiting amplifier DLMA for amplifying the voltage signals output from the fully differential transimpedance preamplifier DTIA to a voltage level required by a digital processing unit, a fully differential equalizer DEQU for compensating the frequency response characteristic of the output signals of the fully differential limiting amplifier DLMA to ensure that the bandwidth of the output signals is not lower than the bandwidth of the incident light signals, thereby reducing the loss of high frequency signal components, and a differential to single-ended output buffer stage DFSO for converting the differential voltage signals output by the fully differential equalizer DEQU, which have reached the digital voltage level, into voltage signals output at a single end and providing a driving capability, the input end of the fully differential transimpedance preamplifier DTIA being connected to convert the visible light signals transmitted from the outside into a pair of fully differential current signals, and a pair of fully differential photodetectors PD1, PD2 providing a pair of identical input loads for subsequent differential receiving circuits.

The pair of fully differential photodetectors comprises a first detector PD1 and a second detector PD2, the first detector PD1 is composed of a P +/N well/P substrate, the anode is connected with one input end of a fully differential transimpedance preamplifier DTIA, and the cathode is connected with a power supply VDD; the second detector PD2 is composed of an N +/P well/a deep N well/a P substrate, the cathode is grounded, the anode is connected with the other input end of the fully differential transimpedance preamplifier DTIA, the directions of the photocurrents generated by the first detector PD1 and the second detector PD2 are opposite, the direction of the photocurrent generated by the first detector PD1 flows into the fully differential transimpedance preamplifier DTIA connected with the first detector, and the direction of the photocurrent generated by the second detector PD2 flows out of the fully differential transimpedance preamplifier DTIA connected with the second detector. In addition, in order to provide a symmetrical pair of input loads to the differential circuit, the first detector PD1 and the second detector PD2 have the same capacitance and are in close proximity to each other, and neither has a light shielding layer above them.

The pair of fully differential photodetectors PD1, PD2 are connected to two input terminals of the fully differential transimpedance preamplifier DTIA in a fully differential manner, wherein the photocurrent flowing into the fully differential transimpedance preamplifier DTIA is generated by two PN junctions, i.e., a P +/N well of the first detector PD1 and an N +/P well of the second detector PD2, which are shallow junctions in a standard CMOS process, and have a response peak to the photocurrent of 460nm, i.e., a blue light region. The pair of fully differential detectors PD1, PD2 are fabricated in a standard CMOS process with a deep N-well or similar triple-well structure.

The first detector PD1 with the area of 400 mu m multiplied by 400 mu m consists of a plurality of subunits with the area of 40 mu m multiplied by 40 mu m; the second detector PD2 is 380 μm × 380 μm in area and is composed of a plurality of subunits with 10 μm × 10 μm in area. The two detectors have the same capacitance value, and the transition time of photon-generated carriers can be effectively reduced by dividing the large-area detector into small units. The subunit difference of the two detectors is because the basic structures of the two detectors are different, which causes that the response bandwidths of the two detectors with the same structure to blue light are different. To improve receiver performance, the receiver front-end input is made symmetric, and the sizes of the two detector sub-units are adjusted to make the intrinsic bandwidths of the two identical.

As shown in fig. 2 and fig. 3, the first detector PD1 and the second detector PD2 share a P-type substrate 1, an N-well region 2 and a deep N-well region 3 are embedded side by side on the P-type substrate 1, a P-type substrate external active region 10 is embedded in the P-type substrate 1 around the periphery of the N-well region 2 and the deep N-well region 3 and near the upper end surface of the P-type substrate 1, wherein a plurality of first detector anodes 8 are embedded in the N-well region 2 near the upper end surface, the plurality of first detector anodes 8 form a square matrix structure, a first detector cathode 5 is embedded in the N-well region 2 near the upper end surface and around each first detector anode 8, a P-well region 4 is embedded in the deep N-well region 3 near the upper end surface and around the P-well region 4, a plurality of second detector cathodes 6 are embedded in the P4 near the upper end surface, a plurality of second detector negative pole 6 constitutes the square matrix structure, it all is embedded with second detector positive pole 9 to close on the up end and around every second detector negative pole 6 in the P well region 4, the up end of P type substrate 1, N well region 2 and P well region 4: a P-type substrate external ground electrode 17 is led out corresponding to the external active region 10, a first detector cathode electrode 12 is led out corresponding to the first detector cathode 5, a first detector anode electrode 13 is led out corresponding to each first detector anode 8, a deep N-well external electrode 16 is led out corresponding to the deep N-well region external active region 7, a second detector cathode electrode 15 is led out corresponding to each second detector cathode 6, and a second detector anode electrode 14 is led out corresponding to each second detector anode 9.

The N well region 2 and the first detector anode 8 form a first detector PD1 in the fully differential detector, and a first detector cathode electrode 12 and a first detector anode electrode 13 are led out; the P-well region 4 and the second detector cathode 6 form a second detector PD2 in the fully differential detector, and a second detector anode electrode 14 and a second detector cathode electrode 15 are led out. When the fully differential detector is IN operation, the first detector cathode electrode 12 is connected to the supply voltage VDD, and the first detector anode electrode 13 is connected to one input of the fully differential transimpedance preamplifier (IN 1); the second detector anode electrode 14 is connected to ground GND and the second detector cathode electrode 15 is connected to the other input terminal (IN2) of the fully differential transimpedance preamplifier. At this time, the equivalent circuit model of the pair of fully differential detectors is shown in fig. 4, wherein the photo-generated current generated by the first detector PD1 will flow into the fully differential transimpedance preamplifier DTIA, and the photo-generated current generated by the second detector PD2 will flow out of the fully differential transimpedance preamplifier DTIA. In order to ensure that the fully differential structure of the detector works normally, the dc voltage of the anode electrode 13 of the first detector and the dc voltage of the cathode electrode 15 of the second detector (or the dc voltage of the input terminal of the fully differential transimpedance preamplifier DTIA) need to be VDD/2 during circuit design, so as to ensure that both detectors are under the same reverse bias. Because the two detector surfaces have no metal shielding and have similar structures, equal capacitance and same intrinsic bandwidth, the two detector surfaces have the same optical frequency response characteristic. The two input ends of the fully differential transimpedance preamplifier have equal input loads, so that the sensitivity of the differential receiver of the invention is doubled compared with the sensitivity of an optical receiver integrated with a single photoelectric detector.

The fully differential transimpedance preamplifier DTIA, the fully differential limiting amplifier DLMA, the fully differential equalizer DEQU and the differential-to-single ended output buffer stage DFSO are all implemented using standard CMOS processes. The design of the fully differential transimpedance preamplifier DTIA is to make the direct-current voltages of two input ends of the fully differential transimpedance preamplifier DTIA equal to half of the power supply voltage VDD through parameter adjustment so as to ensure that the pair of fully differential detectors have the same working state and similar equivalent circuits; the full-differential limiting amplifier DLMA is formed by cascading multi-stage low-gain high-bandwidth full-differential amplifiers, has enough large gain and much higher bandwidth than a full-differential transimpedance preamplifier DTIA, and ensures the lossless transmission of signals except amplifying differential voltage signals output by the full-differential transimpedance preamplifier DTIA to the voltage level required by a digital processing unit; the fully differential equalizer DEQU is the key point of circuit design, the area of the photoelectric detector is large, the capacitance is large, the large capacitance will affect the bandwidth of the whole circuit, and the equalizer compensates the frequency response characteristic of the output signal of the fully differential limiting amplifier DLMA through proper design so as to ensure that the bandwidth output by the circuit is not lower than the bandwidth of the incident light signal, thereby reducing the loss of high-frequency signal components. The differential to single ended output buffer stage DFSO, as the last stage of the optical receiver, does not provide gain, but has much higher bandwidth and sufficiently large current than the entire differential optical receiver. The method converts the differential voltage signal output by the fully differential equalizer DEQU into a single-ended voltage signal; and transmits the signal to a subsequent digital processing unit without loss or to an oscilloscope for observation of the transmitted signal.

In addition, each part of the standard CMOS fully differential photoelectric integrated receiver for visible light communication can be realized by adopting a standard CMOS process, so that the cost of the optical receiver can be greatly reduced. As most subsequent digital units realize standard CMOS, the standard CMOS fully differential photoelectric integrated receiver for visible light communication can realize monolithic integration with subsequent digital processing units, thereby conveniently introducing the functions of electronic logic processing, storage, control and the like, and leading the visible light receiver to realize stronger functions. Therefore, the invention has good application prospect.

Claims

1. A standard CMOS fully differential optoelectronic integrated receiver for visible light communication comprises the following components connected in sequence: a fully differential transimpedance preamplifier (DTIA) for converting a pair of differential current signals into a pair of differential voltage signals, a fully differential limiting amplifier (DLMA) for amplifying the voltage signals output from the fully differential transimpedance preamplifier (DTIA) to a voltage level required by a digital processing unit, a fully Differential Equalizer (DEQU) for compensating for the frequency response characteristics of the signals output from the DLMA, and a differential to single-ended output buffer stage (DFSO) for converting the differential voltage signals output from the dlqu, which have reached the digital voltage level, into voltage signals output at a single end and providing a driving capability, wherein the input terminal of the fully differential transimpedance preamplifier (DTIA) is connected to a pair of fully differential photodetectors (PD 1, PD, d, a, d, a d, for converting externally transmitted visible light signals into a pair of fully differential current signals, PD 2);

the pair of fully differential photodetectors comprises a first detector (PD 1) and a second detector (PD 2), wherein the first detector (PD 1) is composed of a P +/N well/P substrate, the anode is connected with one input end of a fully differential transimpedance preamplifier (DTIA), and the cathode is connected with a power supply VDD; the second detector (PD 2) is composed of an N +/P well/a deep N well/a P substrate, the cathode is grounded, the anode is connected with the other input end of the fully differential transimpedance preamplifier (DTIA), the directions of photocurrents generated by the first detector (PD 1) and the second detector (PD 2) are opposite, the capacitances of the first detector (PD 1) and the second detector (PD 2) are the same, the first detector (PD 1) and the second detector (PD 2) are close to each other, and no shading layer is arranged above the first detector (PD 1) and the second detector (PD 2);

first detector (PD 1) and second detector (PD 2) a P type substrate (1) of sharing, it has N well region (2) and dark N well region (3) to imbed side by side on P type substrate (1), enclose in P type substrate (1) the periphery of N well region (2) and dark N well region (3) and the up end embedding that closes on P type substrate (1) have P type substrate external active area (10), wherein, N well region (2) in close to the up end embedding have a plurality of first detector positive pole (8), a plurality of first detector positive pole (8) constitute square matrix structure, N well region (2) in close to the up end and around every first detector positive pole (8) all embed first detector negative pole (5), dark N well region (3) in embedding has P well region (4), dark N well region (3) in close to the up end and around P well region (4) embedding have N well region (7) external active area (7), there is external active area (7) ) The utility model discloses a well region, it has a plurality of second detector negative pole (6) to close on the up end embedding in P well region (4), a plurality of second detector negative pole (6) constitute the square matrix structure, close on the up end in P well region (4) and all embed second detector positive pole (9) around every second detector negative pole (6), the up end of P type substrate (1), N well region (2) and P well region (4): a P-type substrate external grounding electrode (17) is led out corresponding to the P-type substrate external active area (10), a first detector cathode electrode (12) is led out corresponding to the first detector cathode (5), a first detector anode electrode (13) is led out corresponding to each first detector anode (8), a deep N-well external electrode (16) is led out corresponding to the deep N-well region external active area (7), a second detector cathode electrode (15) is led out corresponding to each second detector cathode (6), and a second detector anode electrode (14) is led out corresponding to each second detector anode (9).

2. The standard CMOS fully differential optoelectronic integrated receiver for visible light communication according to claim 1, wherein the pair of fully differential photodetectors (PD 1, PD 2) are connected in fully differential form to two inputs of a fully differential transimpedance preamplifier (DTIA), wherein the photocurrent flowing into the fully differential transimpedance preamplifier (DTIA) is generated by two PN junctions, P +/N well of the first detector (PD 1) and N +/P well of the second detector (PD 2), which are shallow junctions in the standard CMOS process and have a peak value of the response to the photocurrent in 460nm, i.e. blue region.

3. A standard CMOS fully differential optoelectronic integrated receiver for visible light communication as claimed in claim 1 wherein the first detector (PD 1) area 400 μm x 400 μm is composed of several sub-units area 40 μm x 40 μm; the second detector (PD 2) has an area of 380 μm × 380 μm and is composed of a plurality of subunits having an area of 10 μm × 10 μm.